1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Hansson
38 */
39
40/**
41 * @file
42 * DRAMSim2Wrapper declaration
43 */
44
45#ifndef __MEM_DRAMSIM2_WRAPPER_HH__
46#define __MEM_DRAMSIM2_WRAPPER_HH__
47
48#include <string>
49
50#include "DRAMSim2/Callback.h"
51
52/**
53 * Forward declaration to avoid includes
54 */
55namespace DRAMSim {
56
57class MultiChannelMemorySystem;
58
59}
60
61/**
62 * Wrapper class to avoid having DRAMSim2 names like ClockDomain etc
63 * clashing with the normal gem5 world. Many of the DRAMSim2 headers
64 * do not make use of namespaces, and quite a few also open up
65 * std. The only thing that needs to be exposed externally are the
66 * callbacks. This wrapper effectively avoids clashes by not including
67 * any of the conventional gem5 headers (e.g. Packet or SimObject).
68 */
69class DRAMSim2Wrapper
70{
71
72  private:
73
74    DRAMSim::MultiChannelMemorySystem* dramsim;
75
76    double _clockPeriod;
77
78    unsigned int _queueSize;
79
80    unsigned int _burstSize;
81
82    template <typename T>
83    T extractConfig(const std::string& field_name,
84                    const std::string& file_name) const;
85
86  public:
87
88    /**
89     * Create an instance of the DRAMSim2 multi-channel memory
90     * controller using a specific config and system description.
91     *
92     * @param config_file Memory config file
93     * @param system_file Controller config file
94     * @param working_dir Path pre-pended to config files
95     * @param trace_file Output trace file
96     * @param memory_size_mb Total memory size in MByte
97     * @param enable_debug Enable debug output
98     */
99    DRAMSim2Wrapper(const std::string& config_file,
100                    const std::string& system_file,
101                    const std::string& working_dir,
102                    const std::string& trace_file,
103                    unsigned int memory_size_mb,
104                    bool enable_debug);
105    ~DRAMSim2Wrapper();
106
107    /**
108     * Print the stats gathered in DRAMsim2.
109     */
110    void printStats();
111
112    /**
113     * Set the callbacks to use for read and write completion.
114     *
115     * @param read_callback Callback used for read completions
116     * @param write_callback Callback used for write completions
117     */
118    void setCallbacks(DRAMSim::TransactionCompleteCB* read_callback,
119                      DRAMSim::TransactionCompleteCB* write_callback);
120
121    /**
122     * Determine if the controller can accept a new packet or not.
123     *
124     * @return true if the controller can accept transactions
125     */
126    bool canAccept() const;
127
128    /**
129     * Enqueue a packet. This assumes that canAccept has returned true.
130     *
131     * @param pkt Packet to turn into a DRAMSim2 transaction
132     */
133    void enqueue(bool is_write, uint64_t addr);
134
135    /**
136     * Get the internal clock period used by DRAMSim2, specified in
137     * ns.
138     *
139     * @return The clock period of the DRAM interface in ns
140     */
141    double clockPeriod() const;
142
143    /**
144     * Get the transaction queue size used by DRAMSim2.
145     *
146     * @return The queue size counted in number of transactions
147     */
148    unsigned int queueSize() const;
149
150    /**
151     * Get the burst size in bytes used by DRAMSim2.
152     *
153     * @return The burst size in bytes (data width * burst length)
154     */
155    unsigned int burstSize() const;
156
157    /**
158     * Progress the memory controller one cycle
159     */
160    void tick();
161};
162
163#endif //__MEM_DRAMSIM2_WRAPPER_HH__
164