dram_ctrl.hh revision 10286:e95a0ab1d368
114128Sgiacomo.travaglini@arm.com/* 26757SAli.Saidi@ARM.com * Copyright (c) 2012-2014 ARM Limited 36757SAli.Saidi@ARM.com * All rights reserved 47585SAli.Saidi@arm.com * 57585SAli.Saidi@arm.com * The license below extends only to copyright in the software and shall 67585SAli.Saidi@arm.com * not be construed as granting a license to any other intellectual 77585SAli.Saidi@arm.com * property including but not limited to intellectual property relating 87585SAli.Saidi@arm.com * to a hardware implementation of the functionality of the software 97585SAli.Saidi@arm.com * licensed hereunder. You may use the software subject to the license 107585SAli.Saidi@arm.com * terms below provided that you ensure that this notice is replicated 117585SAli.Saidi@arm.com * unmodified and in its entirety in all distributions of the software, 127585SAli.Saidi@arm.com * modified or unmodified, in source code or in binary form. 136757SAli.Saidi@ARM.com * 146757SAli.Saidi@ARM.com * Copyright (c) 2013 Amin Farmahini-Farahani 156757SAli.Saidi@ARM.com * All rights reserved. 166757SAli.Saidi@ARM.com * 176757SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 186757SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 196757SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 206757SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 216757SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 226757SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 236757SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 246757SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 256757SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 266757SAli.Saidi@ARM.com * this software without specific prior written permission. 276757SAli.Saidi@ARM.com * 286757SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296757SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306757SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316757SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326757SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336757SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346757SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356757SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366757SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3712469Sglenn.bergmans@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386757SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396757SAli.Saidi@ARM.com * 4013608Sgiacomo.travaglini@arm.com * Authors: Andreas Hansson 4111988Sandreas.sandberg@arm.com * Ani Udipi 4212469Sglenn.bergmans@arm.com * Neha Agarwal 436757SAli.Saidi@ARM.com */ 4413665Sandreas.sandberg@arm.com 4513665Sandreas.sandberg@arm.com/** 466757SAli.Saidi@ARM.com * @file 477585SAli.Saidi@arm.com * DRAMCtrl declaration 4811238Sandreas.sandberg@arm.com */ 4911238Sandreas.sandberg@arm.com 5011238Sandreas.sandberg@arm.com#ifndef __MEM_DRAM_CTRL_HH__ 5111238Sandreas.sandberg@arm.com#define __MEM_DRAM_CTRL_HH__ 5211238Sandreas.sandberg@arm.com 5311238Sandreas.sandberg@arm.com#include <deque> 547585SAli.Saidi@arm.com 5513759Sgiacomo.gabrielli@arm.com#include "base/statistics.hh" 5613759Sgiacomo.gabrielli@arm.com#include "enums/AddrMap.hh" 576757SAli.Saidi@ARM.com#include "enums/MemSched.hh" 586757SAli.Saidi@ARM.com#include "enums/PageManage.hh" 599338SAndreas.Sandberg@arm.com#include "mem/abstract_mem.hh" 609050Schander.sudanthi@arm.com#include "mem/qport.hh" 6111234Sandreas.sandberg@arm.com#include "params/DRAMCtrl.hh" 6211234Sandreas.sandberg@arm.com#include "sim/eventq.hh" 6311234Sandreas.sandberg@arm.com 6411234Sandreas.sandberg@arm.com/** 658286SAli.Saidi@ARM.com * The DRAM controller is a basic single-channel memory controller 668286SAli.Saidi@ARM.com * aiming to mimic a high-level DRAM controller and the most important 6710037SARM gem5 Developers * timing constraints associated with the DRAM. The focus is really on 6810037SARM gem5 Developers * modelling the impact on the system rather than the DRAM itself, 6910037SARM gem5 Developers * hence the focus is on the controller model and not on the 7010037SARM gem5 Developers * memory. By adhering to the correct timing constraints, ultimately 7113173Sgiacomo.travaglini@arm.com * there is no need for a memory model in addition to the controller 7213173Sgiacomo.travaglini@arm.com * model. 7311506Sandreas.sandberg@arm.com * 7413396Sgiacomo.travaglini@arm.com * As a basic design principle, this controller is not cycle callable, 7513396Sgiacomo.travaglini@arm.com * but instead uses events to decide when new decisions can be made, 7613396Sgiacomo.travaglini@arm.com * when resources become available, when things are to be considered 7713396Sgiacomo.travaglini@arm.com * done, and when to send things back. Through these simple 7810037SARM gem5 Developers * principles, we achieve a performant model that is not 7910037SARM gem5 Developers * cycle-accurate, but enables us to evaluate the system impact of a 8010037SARM gem5 Developers * wide range of memory technologies, and also collect statistics 8110037SARM gem5 Developers * about the use of the memory. 8210037SARM gem5 Developers */ 8310037SARM gem5 Developersclass DRAMCtrl : public AbstractMemory 8410037SARM gem5 Developers{ 8513759Sgiacomo.gabrielli@arm.com 8613759Sgiacomo.gabrielli@arm.com private: 8713759Sgiacomo.gabrielli@arm.com 8813759Sgiacomo.gabrielli@arm.com // For now, make use of a queued slave port to avoid dealing with 8914128Sgiacomo.travaglini@arm.com // flow control for the responses being sent back 9014128Sgiacomo.travaglini@arm.com class MemoryPort : public QueuedSlavePort 916757SAli.Saidi@ARM.com { 9212531Sandreas.sandberg@arm.com 9312531Sandreas.sandberg@arm.com SlavePacketQueue queue; 9412531Sandreas.sandberg@arm.com DRAMCtrl& memory; 9512005Sandreas.sandberg@arm.com 9612005Sandreas.sandberg@arm.com public: 9712005Sandreas.sandberg@arm.com 9812005Sandreas.sandberg@arm.com MemoryPort(const std::string& name, DRAMCtrl& _memory); 9912469Sglenn.bergmans@arm.com 10012469Sglenn.bergmans@arm.com protected: 10112469Sglenn.bergmans@arm.com 10212469Sglenn.bergmans@arm.com Tick recvAtomic(PacketPtr pkt); 10312469Sglenn.bergmans@arm.com 10412469Sglenn.bergmans@arm.com void recvFunctional(PacketPtr pkt); 10512469Sglenn.bergmans@arm.com 10612471Sglenn.bergmans@arm.com bool recvTimingReq(PacketPtr); 10712471Sglenn.bergmans@arm.com 10812471Sglenn.bergmans@arm.com virtual AddrRangeList getAddrRanges() const; 10912471Sglenn.bergmans@arm.com 11012471Sglenn.bergmans@arm.com }; 11112471Sglenn.bergmans@arm.com 11212471Sglenn.bergmans@arm.com /** 11312471Sglenn.bergmans@arm.com * Our incoming port, for a multi-ported controller add a crossbar 11412469Sglenn.bergmans@arm.com * in front of it 11512469Sglenn.bergmans@arm.com */ 11612469Sglenn.bergmans@arm.com MemoryPort port; 11712469Sglenn.bergmans@arm.com 11812471Sglenn.bergmans@arm.com /** 11912471Sglenn.bergmans@arm.com * Remember if we have to retry a request when available. 12012471Sglenn.bergmans@arm.com */ 12112471Sglenn.bergmans@arm.com bool retryRdReq; 12212469Sglenn.bergmans@arm.com bool retryWrReq; 12312469Sglenn.bergmans@arm.com 12412469Sglenn.bergmans@arm.com /** 12512469Sglenn.bergmans@arm.com * Bus state used to control the read/write switching and drive 12612469Sglenn.bergmans@arm.com * the scheduling of the next request. 12712469Sglenn.bergmans@arm.com */ 12812469Sglenn.bergmans@arm.com enum BusState { 12912469Sglenn.bergmans@arm.com READ = 0, 13012469Sglenn.bergmans@arm.com READ_TO_WRITE, 13112469Sglenn.bergmans@arm.com WRITE, 13210810Sbr@bsdpad.com WRITE_TO_READ 13310810Sbr@bsdpad.com }; 13410810Sbr@bsdpad.com 13512153Sandreas.sandberg@arm.com BusState busState; 1367585SAli.Saidi@arm.com 13710037SARM gem5 Developers /** List to keep track of activate ticks */ 13810037SARM gem5 Developers std::vector<std::deque<Tick>> actTicks; 1399261Sdam.sunwoo@arm.com 1409261Sdam.sunwoo@arm.com /** 1419261Sdam.sunwoo@arm.com * A basic class to track the bank state, i.e. what row is 1429261Sdam.sunwoo@arm.com * currently open (if any), when is the bank free to accept a new 1439332Sdam.sunwoo@arm.com * column (read/write) command, when can it be precharged, and 1449649SAndreas.Sandberg@ARM.com * when can it be activated. 1459649SAndreas.Sandberg@ARM.com * 1469649SAndreas.Sandberg@ARM.com * The bank also keeps track of how many bytes have been accessed 1479649SAndreas.Sandberg@ARM.com * in the open row since it was opened. 1489649SAndreas.Sandberg@ARM.com */ 14910810Sbr@bsdpad.com class Bank 15013608Sgiacomo.travaglini@arm.com { 15113608Sgiacomo.travaglini@arm.com 15213608Sgiacomo.travaglini@arm.com public: 15313608Sgiacomo.travaglini@arm.com 15413608Sgiacomo.travaglini@arm.com static const uint32_t NO_ROW = -1; 15513608Sgiacomo.travaglini@arm.com 15613608Sgiacomo.travaglini@arm.com uint32_t openRow; 15713608Sgiacomo.travaglini@arm.com uint8_t rank; 15813608Sgiacomo.travaglini@arm.com uint8_t bank; 15913608Sgiacomo.travaglini@arm.com 16013608Sgiacomo.travaglini@arm.com Tick colAllowedAt; 16113608Sgiacomo.travaglini@arm.com Tick preAllowedAt; 16213608Sgiacomo.travaglini@arm.com Tick actAllowedAt; 16310810Sbr@bsdpad.com 16410810Sbr@bsdpad.com uint32_t rowAccesses; 16510810Sbr@bsdpad.com uint32_t bytesAccessed; 16610810Sbr@bsdpad.com 16711988Sandreas.sandberg@arm.com Bank() : 16811988Sandreas.sandberg@arm.com openRow(NO_ROW), rank(0), bank(0), 16911988Sandreas.sandberg@arm.com colAllowedAt(0), preAllowedAt(0), actAllowedAt(0), 17011988Sandreas.sandberg@arm.com rowAccesses(0), bytesAccessed(0) 17111538Sandreas.sandberg@arm.com { } 17212272SGeoffrey.Blake@arm.com }; 17312272SGeoffrey.Blake@arm.com 17412272SGeoffrey.Blake@arm.com /** 17512272SGeoffrey.Blake@arm.com * A burst helper helps organize and manage a packet that is larger than 17610810Sbr@bsdpad.com * the DRAM burst size. A system packet that is larger than the burst size 17710810Sbr@bsdpad.com * is split into multiple DRAM packets and all those DRAM packets point to 17810810Sbr@bsdpad.com * a single burst helper such that we know when the whole packet is served. 179 */ 180 class BurstHelper { 181 182 public: 183 184 /** Number of DRAM bursts requred for a system packet **/ 185 const unsigned int burstCount; 186 187 /** Number of DRAM bursts serviced so far for a system packet **/ 188 unsigned int burstsServiced; 189 190 BurstHelper(unsigned int _burstCount) 191 : burstCount(_burstCount), burstsServiced(0) 192 { } 193 }; 194 195 /** 196 * A DRAM packet stores packets along with the timestamp of when 197 * the packet entered the queue, and also the decoded address. 198 */ 199 class DRAMPacket { 200 201 public: 202 203 /** When did request enter the controller */ 204 const Tick entryTime; 205 206 /** When will request leave the controller */ 207 Tick readyTime; 208 209 /** This comes from the outside world */ 210 const PacketPtr pkt; 211 212 const bool isRead; 213 214 /** Will be populated by address decoder */ 215 const uint8_t rank; 216 const uint8_t bank; 217 const uint32_t row; 218 219 /** 220 * Bank id is calculated considering banks in all the ranks 221 * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and 222 * bankId = 8 --> rank1, bank0 223 */ 224 const uint16_t bankId; 225 226 /** 227 * The starting address of the DRAM packet. 228 * This address could be unaligned to burst size boundaries. The 229 * reason is to keep the address offset so we can accurately check 230 * incoming read packets with packets in the write queue. 231 */ 232 Addr addr; 233 234 /** 235 * The size of this dram packet in bytes 236 * It is always equal or smaller than DRAM burst size 237 */ 238 unsigned int size; 239 240 /** 241 * A pointer to the BurstHelper if this DRAMPacket is a split packet 242 * If not a split packet (common case), this is set to NULL 243 */ 244 BurstHelper* burstHelper; 245 Bank& bankRef; 246 247 DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank, 248 uint32_t _row, uint16_t bank_id, Addr _addr, 249 unsigned int _size, Bank& bank_ref) 250 : entryTime(curTick()), readyTime(curTick()), 251 pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row), 252 bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL), 253 bankRef(bank_ref) 254 { } 255 256 }; 257 258 /** 259 * Bunch of things requires to setup "events" in gem5 260 * When event "respondEvent" occurs for example, the method 261 * processRespondEvent is called; no parameters are allowed 262 * in these methods 263 */ 264 void processNextReqEvent(); 265 EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent; 266 267 void processRespondEvent(); 268 EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent; 269 270 void processActivateEvent(); 271 EventWrapper<DRAMCtrl, &DRAMCtrl::processActivateEvent> activateEvent; 272 273 void processPrechargeEvent(); 274 EventWrapper<DRAMCtrl, &DRAMCtrl::processPrechargeEvent> prechargeEvent; 275 276 void processRefreshEvent(); 277 EventWrapper<DRAMCtrl, &DRAMCtrl::processRefreshEvent> refreshEvent; 278 279 void processPowerEvent(); 280 EventWrapper<DRAMCtrl,&DRAMCtrl::processPowerEvent> powerEvent; 281 282 /** 283 * Check if the read queue has room for more entries 284 * 285 * @param pktCount The number of entries needed in the read queue 286 * @return true if read queue is full, false otherwise 287 */ 288 bool readQueueFull(unsigned int pktCount) const; 289 290 /** 291 * Check if the write queue has room for more entries 292 * 293 * @param pktCount The number of entries needed in the write queue 294 * @return true if write queue is full, false otherwise 295 */ 296 bool writeQueueFull(unsigned int pktCount) const; 297 298 /** 299 * When a new read comes in, first check if the write q has a 300 * pending request to the same address.\ If not, decode the 301 * address to populate rank/bank/row, create one or mutliple 302 * "dram_pkt", and push them to the back of the read queue.\ 303 * If this is the only 304 * read request in the system, schedule an event to start 305 * servicing it. 306 * 307 * @param pkt The request packet from the outside world 308 * @param pktCount The number of DRAM bursts the pkt 309 * translate to. If pkt size is larger then one full burst, 310 * then pktCount is greater than one. 311 */ 312 void addToReadQueue(PacketPtr pkt, unsigned int pktCount); 313 314 /** 315 * Decode the incoming pkt, create a dram_pkt and push to the 316 * back of the write queue. \If the write q length is more than 317 * the threshold specified by the user, ie the queue is beginning 318 * to get full, stop reads, and start draining writes. 319 * 320 * @param pkt The request packet from the outside world 321 * @param pktCount The number of DRAM bursts the pkt 322 * translate to. If pkt size is larger then one full burst, 323 * then pktCount is greater than one. 324 */ 325 void addToWriteQueue(PacketPtr pkt, unsigned int pktCount); 326 327 /** 328 * Actually do the DRAM access - figure out the latency it 329 * will take to service the req based on bank state, channel state etc 330 * and then update those states to account for this request.\ Based 331 * on this, update the packet's "readyTime" and move it to the 332 * response q from where it will eventually go back to the outside 333 * world. 334 * 335 * @param pkt The DRAM packet created from the outside world pkt 336 */ 337 void doDRAMAccess(DRAMPacket* dram_pkt); 338 339 /** 340 * When a packet reaches its "readyTime" in the response Q, 341 * use the "access()" method in AbstractMemory to actually 342 * create the response packet, and send it back to the outside 343 * world requestor. 344 * 345 * @param pkt The packet from the outside world 346 * @param static_latency Static latency to add before sending the packet 347 */ 348 void accessAndRespond(PacketPtr pkt, Tick static_latency); 349 350 /** 351 * Address decoder to figure out physical mapping onto ranks, 352 * banks, and rows. This function is called multiple times on the same 353 * system packet if the pakcet is larger than burst of the memory. The 354 * dramPktAddr is used for the offset within the packet. 355 * 356 * @param pkt The packet from the outside world 357 * @param dramPktAddr The starting address of the DRAM packet 358 * @param size The size of the DRAM packet in bytes 359 * @param isRead Is the request for a read or a write to DRAM 360 * @return A DRAMPacket pointer with the decoded information 361 */ 362 DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, 363 bool isRead); 364 365 /** 366 * The memory schduler/arbiter - picks which request needs to 367 * go next, based on the specified policy such as FCFS or FR-FCFS 368 * and moves it to the head of the queue. 369 */ 370 void chooseNext(std::deque<DRAMPacket*>& queue); 371 372 /** 373 * For FR-FCFS policy reorder the read/write queue depending on row buffer 374 * hits and earliest banks available in DRAM 375 */ 376 void reorderQueue(std::deque<DRAMPacket*>& queue); 377 378 /** 379 * Find which are the earliest banks ready to issue an activate 380 * for the enqueued requests. Assumes maximum of 64 banks per DIMM 381 * 382 * @param Queued requests to consider 383 * @return One-hot encoded mask of bank indices 384 */ 385 uint64_t minBankActAt(const std::deque<DRAMPacket*>& queue) const; 386 387 /** 388 * Keep track of when row activations happen, in order to enforce 389 * the maximum number of activations in the activation window. The 390 * method updates the time that the banks become available based 391 * on the current limits. 392 * 393 * @param bank Reference to the bank 394 * @param act_tick Time when the activation takes place 395 * @param row Index of the row 396 */ 397 void activateBank(Bank& bank, Tick act_tick, uint32_t row); 398 399 /** 400 * Precharge a given bank and also update when the precharge is 401 * done. This will also deal with any stats related to the 402 * accesses to the open page. 403 * 404 * @param bank_ref The bank to precharge 405 * @param pre_at Time when the precharge takes place 406 * @param trace Is this an auto precharge then do not add to trace 407 */ 408 void prechargeBank(Bank& bank_ref, Tick pre_at, bool trace = true); 409 410 /** 411 * Used for debugging to observe the contents of the queues. 412 */ 413 void printQs() const; 414 415 /** 416 * The controller's main read and write queues 417 */ 418 std::deque<DRAMPacket*> readQueue; 419 std::deque<DRAMPacket*> writeQueue; 420 421 /** 422 * Response queue where read packets wait after we're done working 423 * with them, but it's not time to send the response yet. The 424 * responses are stored seperately mostly to keep the code clean 425 * and help with events scheduling. For all logical purposes such 426 * as sizing the read queue, this and the main read queue need to 427 * be added together. 428 */ 429 std::deque<DRAMPacket*> respQueue; 430 431 /** 432 * If we need to drain, keep the drain manager around until we're 433 * done here. 434 */ 435 DrainManager *drainManager; 436 437 /** 438 * Multi-dimensional vector of banks, first dimension is ranks, 439 * second is bank 440 */ 441 std::vector<std::vector<Bank> > banks; 442 443 /** 444 * The following are basic design parameters of the memory 445 * controller, and are initialized based on parameter values. 446 * The rowsPerBank is determined based on the capacity, number of 447 * ranks and banks, the burst size, and the row buffer size. 448 */ 449 const uint32_t deviceBusWidth; 450 const uint32_t burstLength; 451 const uint32_t deviceRowBufferSize; 452 const uint32_t devicesPerRank; 453 const uint32_t burstSize; 454 const uint32_t rowBufferSize; 455 const uint32_t columnsPerRowBuffer; 456 const uint32_t columnsPerStripe; 457 const uint32_t ranksPerChannel; 458 const uint32_t banksPerRank; 459 const uint32_t channels; 460 uint32_t rowsPerBank; 461 const uint32_t readBufferSize; 462 const uint32_t writeBufferSize; 463 const uint32_t writeHighThreshold; 464 const uint32_t writeLowThreshold; 465 const uint32_t minWritesPerSwitch; 466 uint32_t writesThisTime; 467 uint32_t readsThisTime; 468 469 /** 470 * Basic memory timing parameters initialized based on parameter 471 * values. 472 */ 473 const Tick M5_CLASS_VAR_USED tCK; 474 const Tick tWTR; 475 const Tick tRTW; 476 const Tick tBURST; 477 const Tick tRCD; 478 const Tick tCL; 479 const Tick tRP; 480 const Tick tRAS; 481 const Tick tWR; 482 const Tick tRTP; 483 const Tick tRFC; 484 const Tick tREFI; 485 const Tick tRRD; 486 const Tick tXAW; 487 const uint32_t activationLimit; 488 489 /** 490 * Memory controller configuration initialized based on parameter 491 * values. 492 */ 493 Enums::MemSched memSchedPolicy; 494 Enums::AddrMap addrMapping; 495 Enums::PageManage pageMgmt; 496 497 /** 498 * Max column accesses (read and write) per row, before forefully 499 * closing it. 500 */ 501 const uint32_t maxAccessesPerRow; 502 503 /** 504 * Pipeline latency of the controller frontend. The frontend 505 * contribution is added to writes (that complete when they are in 506 * the write buffer) and reads that are serviced the write buffer. 507 */ 508 const Tick frontendLatency; 509 510 /** 511 * Pipeline latency of the backend and PHY. Along with the 512 * frontend contribution, this latency is added to reads serviced 513 * by the DRAM. 514 */ 515 const Tick backendLatency; 516 517 /** 518 * Till when has the main data bus been spoken for already? 519 */ 520 Tick busBusyUntil; 521 522 /** 523 * Keep track of when a refresh is due. 524 */ 525 Tick refreshDueAt; 526 527 /** 528 * The refresh state is used to control the progress of the 529 * refresh scheduling. When normal operation is in progress the 530 * refresh state is idle. From there, it progresses to the refresh 531 * drain state once tREFI has passed. The refresh drain state 532 * captures the DRAM row active state, as it will stay there until 533 * all ongoing accesses complete. Thereafter all banks are 534 * precharged, and lastly, the DRAM is refreshed. 535 */ 536 enum RefreshState { 537 REF_IDLE = 0, 538 REF_DRAIN, 539 REF_PRE, 540 REF_RUN 541 }; 542 543 RefreshState refreshState; 544 545 /** 546 * The power state captures the different operational states of 547 * the DRAM and interacts with the bus read/write state machine, 548 * and the refresh state machine. In the idle state all banks are 549 * precharged. From there we either go to an auto refresh (as 550 * determined by the refresh state machine), or to a precharge 551 * power down mode. From idle the memory can also go to the active 552 * state (with one or more banks active), and in turn from there 553 * to active power down. At the moment we do not capture the deep 554 * power down and self-refresh state. 555 */ 556 enum PowerState { 557 PWR_IDLE = 0, 558 PWR_REF, 559 PWR_PRE_PDN, 560 PWR_ACT, 561 PWR_ACT_PDN 562 }; 563 564 /** 565 * Since we are taking decisions out of order, we need to keep 566 * track of what power transition is happening at what time, such 567 * that we can go back in time and change history. For example, if 568 * we precharge all banks and schedule going to the idle state, we 569 * might at a later point decide to activate a bank before the 570 * transition to idle would have taken place. 571 */ 572 PowerState pwrStateTrans; 573 574 /** 575 * Current power state. 576 */ 577 PowerState pwrState; 578 579 /** 580 * Schedule a power state transition in the future, and 581 * potentially override an already scheduled transition. 582 * 583 * @param pwr_state Power state to transition to 584 * @param tick Tick when transition should take place 585 */ 586 void schedulePowerEvent(PowerState pwr_state, Tick tick); 587 588 Tick prevArrival; 589 590 /** 591 * The soonest you have to start thinking about the next request 592 * is the longest access time that can occur before 593 * busBusyUntil. Assuming you need to precharge, open a new row, 594 * and access, it is tRP + tRCD + tCL. 595 */ 596 Tick nextReqTime; 597 598 // All statistics that the model needs to capture 599 Stats::Scalar readReqs; 600 Stats::Scalar writeReqs; 601 Stats::Scalar readBursts; 602 Stats::Scalar writeBursts; 603 Stats::Scalar bytesReadDRAM; 604 Stats::Scalar bytesReadWrQ; 605 Stats::Scalar bytesWritten; 606 Stats::Scalar bytesReadSys; 607 Stats::Scalar bytesWrittenSys; 608 Stats::Scalar servicedByWrQ; 609 Stats::Scalar mergedWrBursts; 610 Stats::Scalar neitherReadNorWrite; 611 Stats::Vector perBankRdBursts; 612 Stats::Vector perBankWrBursts; 613 Stats::Scalar numRdRetry; 614 Stats::Scalar numWrRetry; 615 Stats::Scalar totGap; 616 Stats::Vector readPktSize; 617 Stats::Vector writePktSize; 618 Stats::Vector rdQLenPdf; 619 Stats::Vector wrQLenPdf; 620 Stats::Histogram bytesPerActivate; 621 Stats::Histogram rdPerTurnAround; 622 Stats::Histogram wrPerTurnAround; 623 624 // Latencies summed over all requests 625 Stats::Scalar totQLat; 626 Stats::Scalar totMemAccLat; 627 Stats::Scalar totBusLat; 628 629 // Average latencies per request 630 Stats::Formula avgQLat; 631 Stats::Formula avgBusLat; 632 Stats::Formula avgMemAccLat; 633 634 // Average bandwidth 635 Stats::Formula avgRdBW; 636 Stats::Formula avgWrBW; 637 Stats::Formula avgRdBWSys; 638 Stats::Formula avgWrBWSys; 639 Stats::Formula peakBW; 640 Stats::Formula busUtil; 641 Stats::Formula busUtilRead; 642 Stats::Formula busUtilWrite; 643 644 // Average queue lengths 645 Stats::Average avgRdQLen; 646 Stats::Average avgWrQLen; 647 648 // Row hit count and rate 649 Stats::Scalar readRowHits; 650 Stats::Scalar writeRowHits; 651 Stats::Formula readRowHitRate; 652 Stats::Formula writeRowHitRate; 653 Stats::Formula avgGap; 654 655 // DRAM Power Calculation 656 Stats::Formula pageHitRate; 657 Stats::Vector pwrStateTime; 658 659 // Track when we transitioned to the current power state 660 Tick pwrStateTick; 661 662 // To track number of banks which are currently active 663 unsigned int numBanksActive; 664 665 /** @todo this is a temporary workaround until the 4-phase code is 666 * committed. upstream caches needs this packet until true is returned, so 667 * hold onto it for deletion until a subsequent call 668 */ 669 std::vector<PacketPtr> pendingDelete; 670 671 public: 672 673 void regStats(); 674 675 DRAMCtrl(const DRAMCtrlParams* p); 676 677 unsigned int drain(DrainManager* dm); 678 679 virtual BaseSlavePort& getSlavePort(const std::string& if_name, 680 PortID idx = InvalidPortID); 681 682 virtual void init(); 683 virtual void startup(); 684 685 protected: 686 687 Tick recvAtomic(PacketPtr pkt); 688 void recvFunctional(PacketPtr pkt); 689 bool recvTimingReq(PacketPtr pkt); 690 691}; 692 693#endif //__MEM_DRAM_CTRL_HH__ 694