dram_ctrl.hh revision 11678
19243SN/A/* 211675Swendy.elsasser@arm.com * Copyright (c) 2012-2016 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com * Omar Naji 4411555Sjungma@eit.uni-kl.de * Matthias Jung 4511678Swendy.elsasser@arm.com * Wendy Elsasser 469243SN/A */ 479243SN/A 489243SN/A/** 499243SN/A * @file 5010146Sandreas.hansson@arm.com * DRAMCtrl declaration 519243SN/A */ 529243SN/A 5310146Sandreas.hansson@arm.com#ifndef __MEM_DRAM_CTRL_HH__ 5410146Sandreas.hansson@arm.com#define __MEM_DRAM_CTRL_HH__ 559243SN/A 569488SN/A#include <deque> 5710618SOmar.Naji@arm.com#include <string> 5810889Sandreas.hansson@arm.com#include <unordered_set> 599488SN/A 6011677Swendy.elsasser@arm.com#include "base/callback.hh" 619243SN/A#include "base/statistics.hh" 629243SN/A#include "enums/AddrMap.hh" 639243SN/A#include "enums/MemSched.hh" 649243SN/A#include "enums/PageManage.hh" 659243SN/A#include "mem/abstract_mem.hh" 669243SN/A#include "mem/qport.hh" 6710146Sandreas.hansson@arm.com#include "params/DRAMCtrl.hh" 689243SN/A#include "sim/eventq.hh" 6910432SOmar.Naji@arm.com#include "mem/drampower.hh" 709243SN/A 719243SN/A/** 7210287Sandreas.hansson@arm.com * The DRAM controller is a single-channel memory controller capturing 7310287Sandreas.hansson@arm.com * the most important timing constraints associated with a 7410287Sandreas.hansson@arm.com * contemporary DRAM. For multi-channel memory systems, the controller 7510287Sandreas.hansson@arm.com * is combined with a crossbar model, with the channel address 7610287Sandreas.hansson@arm.com * interleaving taking part in the crossbar. 779243SN/A * 7810287Sandreas.hansson@arm.com * As a basic design principle, this controller 7910287Sandreas.hansson@arm.com * model is not cycle callable, but instead uses events to: 1) decide 8010287Sandreas.hansson@arm.com * when new decisions can be made, 2) when resources become available, 8110287Sandreas.hansson@arm.com * 3) when things are to be considered done, and 4) when to send 8210287Sandreas.hansson@arm.com * things back. Through these simple principles, the model delivers 8310287Sandreas.hansson@arm.com * high performance, and lots of flexibility, allowing users to 8410287Sandreas.hansson@arm.com * evaluate the system impact of a wide range of memory technologies, 8510287Sandreas.hansson@arm.com * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC. 8610287Sandreas.hansson@arm.com * 8710287Sandreas.hansson@arm.com * For more details, please see Hansson et al, "Simulating DRAM 8810287Sandreas.hansson@arm.com * controllers for future system architecture exploration", 8910287Sandreas.hansson@arm.com * Proc. ISPASS, 2014. If you use this model as part of your research 9010287Sandreas.hansson@arm.com * please cite the paper. 9111678Swendy.elsasser@arm.com * 9211678Swendy.elsasser@arm.com * The low-power functionality implements a staggered powerdown 9311678Swendy.elsasser@arm.com * similar to that described in "Optimized Active and Power-Down Mode 9411678Swendy.elsasser@arm.com * Refresh Control in 3D-DRAMs" by Jung et al, VLSI-SoC, 2014. 959243SN/A */ 9610146Sandreas.hansson@arm.comclass DRAMCtrl : public AbstractMemory 979243SN/A{ 989243SN/A 999243SN/A private: 1009243SN/A 1019243SN/A // For now, make use of a queued slave port to avoid dealing with 1029243SN/A // flow control for the responses being sent back 1039243SN/A class MemoryPort : public QueuedSlavePort 1049243SN/A { 1059243SN/A 10610713Sandreas.hansson@arm.com RespPacketQueue queue; 10710146Sandreas.hansson@arm.com DRAMCtrl& memory; 1089243SN/A 1099243SN/A public: 1109243SN/A 11110146Sandreas.hansson@arm.com MemoryPort(const std::string& name, DRAMCtrl& _memory); 1129243SN/A 1139243SN/A protected: 1149243SN/A 1159243SN/A Tick recvAtomic(PacketPtr pkt); 1169243SN/A 1179243SN/A void recvFunctional(PacketPtr pkt); 1189243SN/A 1199243SN/A bool recvTimingReq(PacketPtr); 1209243SN/A 1219243SN/A virtual AddrRangeList getAddrRanges() const; 1229243SN/A 1239243SN/A }; 1249243SN/A 1259243SN/A /** 1269243SN/A * Our incoming port, for a multi-ported controller add a crossbar 1279243SN/A * in front of it 1289243SN/A */ 1299243SN/A MemoryPort port; 1309243SN/A 1319243SN/A /** 13210619Sandreas.hansson@arm.com * Remeber if the memory system is in timing mode 13310619Sandreas.hansson@arm.com */ 13410619Sandreas.hansson@arm.com bool isTimingMode; 13510619Sandreas.hansson@arm.com 13610619Sandreas.hansson@arm.com /** 1379243SN/A * Remember if we have to retry a request when available. 1389243SN/A */ 1399243SN/A bool retryRdReq; 1409243SN/A bool retryWrReq; 1419243SN/A 1429243SN/A /** 14310206Sandreas.hansson@arm.com * Bus state used to control the read/write switching and drive 14410206Sandreas.hansson@arm.com * the scheduling of the next request. 1459243SN/A */ 14610206Sandreas.hansson@arm.com enum BusState { 14710206Sandreas.hansson@arm.com READ = 0, 14810206Sandreas.hansson@arm.com WRITE, 14910206Sandreas.hansson@arm.com }; 15010206Sandreas.hansson@arm.com 15110206Sandreas.hansson@arm.com BusState busState; 1529243SN/A 15311678Swendy.elsasser@arm.com /* bus state for next request event triggered */ 15411678Swendy.elsasser@arm.com BusState busStateNext; 15511678Swendy.elsasser@arm.com 1569243SN/A /** 15711675Swendy.elsasser@arm.com * Simple structure to hold the values needed to keep track of 15811675Swendy.elsasser@arm.com * commands for DRAMPower 15911675Swendy.elsasser@arm.com */ 16011675Swendy.elsasser@arm.com struct Command { 16111675Swendy.elsasser@arm.com Data::MemCommand::cmds type; 16211675Swendy.elsasser@arm.com uint8_t bank; 16311675Swendy.elsasser@arm.com Tick timeStamp; 16411675Swendy.elsasser@arm.com 16511675Swendy.elsasser@arm.com constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank, 16611675Swendy.elsasser@arm.com Tick time_stamp) 16711675Swendy.elsasser@arm.com : type(_type), bank(_bank), timeStamp(time_stamp) 16811675Swendy.elsasser@arm.com { } 16911675Swendy.elsasser@arm.com }; 17011675Swendy.elsasser@arm.com 17111675Swendy.elsasser@arm.com /** 17210210Sandreas.hansson@arm.com * A basic class to track the bank state, i.e. what row is 17310210Sandreas.hansson@arm.com * currently open (if any), when is the bank free to accept a new 17410211Sandreas.hansson@arm.com * column (read/write) command, when can it be precharged, and 17510211Sandreas.hansson@arm.com * when can it be activated. 17610210Sandreas.hansson@arm.com * 17710210Sandreas.hansson@arm.com * The bank also keeps track of how many bytes have been accessed 17810210Sandreas.hansson@arm.com * in the open row since it was opened. 1799243SN/A */ 1809243SN/A class Bank 1819243SN/A { 1829243SN/A 1839243SN/A public: 1849243SN/A 18510207Sandreas.hansson@arm.com static const uint32_t NO_ROW = -1; 1869243SN/A 1879243SN/A uint32_t openRow; 18810246Sandreas.hansson@arm.com uint8_t bank; 18910394Swendy.elsasser@arm.com uint8_t bankgr; 1909243SN/A 19110211Sandreas.hansson@arm.com Tick colAllowedAt; 19210210Sandreas.hansson@arm.com Tick preAllowedAt; 1939969SN/A Tick actAllowedAt; 1949243SN/A 19510141SN/A uint32_t rowAccesses; 1969727SN/A uint32_t bytesAccessed; 1979727SN/A 1989727SN/A Bank() : 19910618SOmar.Naji@arm.com openRow(NO_ROW), bank(0), bankgr(0), 20010246Sandreas.hansson@arm.com colAllowedAt(0), preAllowedAt(0), actAllowedAt(0), 20110141SN/A rowAccesses(0), bytesAccessed(0) 2029243SN/A { } 2039243SN/A }; 2049243SN/A 20510618SOmar.Naji@arm.com 20610618SOmar.Naji@arm.com /** 20711678Swendy.elsasser@arm.com * The power state captures the different operational states of 20811678Swendy.elsasser@arm.com * the DRAM and interacts with the bus read/write state machine, 20911678Swendy.elsasser@arm.com * and the refresh state machine. 21011678Swendy.elsasser@arm.com * 21111678Swendy.elsasser@arm.com * PWR_IDLE : The idle state in which all banks are closed 21211678Swendy.elsasser@arm.com * From here can transition to: PWR_REF, PWR_ACT, 21311678Swendy.elsasser@arm.com * PWR_PRE_PDN 21411678Swendy.elsasser@arm.com * 21511678Swendy.elsasser@arm.com * PWR_REF : Auto-refresh state. Will transition when refresh is 21611678Swendy.elsasser@arm.com * complete based on power state prior to PWR_REF 21711678Swendy.elsasser@arm.com * From here can transition to: PWR_IDLE, PWR_PRE_PDN, 21811678Swendy.elsasser@arm.com * PWR_SREF 21911678Swendy.elsasser@arm.com * 22011678Swendy.elsasser@arm.com * PWR_SREF : Self-refresh state. Entered after refresh if 22111678Swendy.elsasser@arm.com * previous state was PWR_PRE_PDN 22211678Swendy.elsasser@arm.com * From here can transition to: PWR_IDLE 22311678Swendy.elsasser@arm.com * 22411678Swendy.elsasser@arm.com * PWR_PRE_PDN : Precharge power down state 22511678Swendy.elsasser@arm.com * From here can transition to: PWR_REF, PWR_IDLE 22611678Swendy.elsasser@arm.com * 22711678Swendy.elsasser@arm.com * PWR_ACT : Activate state in which one or more banks are open 22811678Swendy.elsasser@arm.com * From here can transition to: PWR_IDLE, PWR_ACT_PDN 22911678Swendy.elsasser@arm.com * 23011678Swendy.elsasser@arm.com * PWR_ACT_PDN : Activate power down state 23111678Swendy.elsasser@arm.com * From here can transition to: PWR_ACT 23211678Swendy.elsasser@arm.com */ 23311678Swendy.elsasser@arm.com enum PowerState { 23411678Swendy.elsasser@arm.com PWR_IDLE = 0, 23511678Swendy.elsasser@arm.com PWR_REF, 23611678Swendy.elsasser@arm.com PWR_SREF, 23711678Swendy.elsasser@arm.com PWR_PRE_PDN, 23811678Swendy.elsasser@arm.com PWR_ACT, 23911678Swendy.elsasser@arm.com PWR_ACT_PDN 24011678Swendy.elsasser@arm.com }; 24111678Swendy.elsasser@arm.com 24211678Swendy.elsasser@arm.com /** 24311678Swendy.elsasser@arm.com * The refresh state is used to control the progress of the 24411678Swendy.elsasser@arm.com * refresh scheduling. When normal operation is in progress the 24511678Swendy.elsasser@arm.com * refresh state is idle. Once tREFI has elasped, a refresh event 24611678Swendy.elsasser@arm.com * is triggered to start the following STM transitions which are 24711678Swendy.elsasser@arm.com * used to issue a refresh and return back to normal operation 24811678Swendy.elsasser@arm.com * 24911678Swendy.elsasser@arm.com * REF_IDLE : IDLE state used during normal operation 25011678Swendy.elsasser@arm.com * From here can transition to: REF_DRAIN 25111678Swendy.elsasser@arm.com * 25211678Swendy.elsasser@arm.com * REF_SREF_EXIT : Exiting a self-refresh; refresh event scheduled 25311678Swendy.elsasser@arm.com * after self-refresh exit completes 25411678Swendy.elsasser@arm.com * From here can transition to: REF_DRAIN 25511678Swendy.elsasser@arm.com * 25611678Swendy.elsasser@arm.com * REF_DRAIN : Drain state in which on going accesses complete. 25711678Swendy.elsasser@arm.com * From here can transition to: REF_PD_EXIT 25811678Swendy.elsasser@arm.com * 25911678Swendy.elsasser@arm.com * REF_PD_EXIT : Evaluate pwrState and issue wakeup if needed 26011678Swendy.elsasser@arm.com * Next state dependent on whether banks are open 26111678Swendy.elsasser@arm.com * From here can transition to: REF_PRE, REF_START 26211678Swendy.elsasser@arm.com * 26311678Swendy.elsasser@arm.com * REF_PRE : Close (precharge) all open banks 26411678Swendy.elsasser@arm.com * From here can transition to: REF_START 26511678Swendy.elsasser@arm.com * 26611678Swendy.elsasser@arm.com * REF_START : Issue refresh command and update DRAMPower stats 26711678Swendy.elsasser@arm.com * From here can transition to: REF_RUN 26811678Swendy.elsasser@arm.com * 26911678Swendy.elsasser@arm.com * REF_RUN : Refresh running, waiting for tRFC to expire 27011678Swendy.elsasser@arm.com * From here can transition to: REF_IDLE, REF_SREF_EXIT 27111678Swendy.elsasser@arm.com */ 27211678Swendy.elsasser@arm.com enum RefreshState { 27311678Swendy.elsasser@arm.com REF_IDLE = 0, 27411678Swendy.elsasser@arm.com REF_DRAIN, 27511678Swendy.elsasser@arm.com REF_PD_EXIT, 27611678Swendy.elsasser@arm.com REF_SREF_EXIT, 27711678Swendy.elsasser@arm.com REF_PRE, 27811678Swendy.elsasser@arm.com REF_START, 27911678Swendy.elsasser@arm.com REF_RUN 28011678Swendy.elsasser@arm.com }; 28111678Swendy.elsasser@arm.com 28211678Swendy.elsasser@arm.com /** 28310618SOmar.Naji@arm.com * Rank class includes a vector of banks. Refresh and Power state 28410618SOmar.Naji@arm.com * machines are defined per rank. Events required to change the 28510618SOmar.Naji@arm.com * state of the refresh and power state machine are scheduled per 28610618SOmar.Naji@arm.com * rank. This class allows the implementation of rank-wise refresh 28710618SOmar.Naji@arm.com * and rank-wise power-down. 28810618SOmar.Naji@arm.com */ 28910618SOmar.Naji@arm.com class Rank : public EventManager 29010618SOmar.Naji@arm.com { 29110618SOmar.Naji@arm.com 29210618SOmar.Naji@arm.com private: 29310618SOmar.Naji@arm.com 29410618SOmar.Naji@arm.com /** 29510618SOmar.Naji@arm.com * A reference to the parent DRAMCtrl instance 29610618SOmar.Naji@arm.com */ 29710618SOmar.Naji@arm.com DRAMCtrl& memory; 29810618SOmar.Naji@arm.com 29910618SOmar.Naji@arm.com /** 30010618SOmar.Naji@arm.com * Since we are taking decisions out of order, we need to keep 30111678Swendy.elsasser@arm.com * track of what power transition is happening at what time 30210618SOmar.Naji@arm.com */ 30310618SOmar.Naji@arm.com PowerState pwrStateTrans; 30410618SOmar.Naji@arm.com 30510618SOmar.Naji@arm.com /** 30611678Swendy.elsasser@arm.com * Previous low-power state, which will be re-entered after refresh. 30710618SOmar.Naji@arm.com */ 30811678Swendy.elsasser@arm.com PowerState pwrStatePostRefresh; 30910618SOmar.Naji@arm.com 31010618SOmar.Naji@arm.com /** 31110618SOmar.Naji@arm.com * Track when we transitioned to the current power state 31210618SOmar.Naji@arm.com */ 31310618SOmar.Naji@arm.com Tick pwrStateTick; 31410618SOmar.Naji@arm.com 31510618SOmar.Naji@arm.com /** 31610618SOmar.Naji@arm.com * Keep track of when a refresh is due. 31710618SOmar.Naji@arm.com */ 31810618SOmar.Naji@arm.com Tick refreshDueAt; 31910618SOmar.Naji@arm.com 32010618SOmar.Naji@arm.com /* 32110618SOmar.Naji@arm.com * Command energies 32210618SOmar.Naji@arm.com */ 32310618SOmar.Naji@arm.com Stats::Scalar actEnergy; 32410618SOmar.Naji@arm.com Stats::Scalar preEnergy; 32510618SOmar.Naji@arm.com Stats::Scalar readEnergy; 32610618SOmar.Naji@arm.com Stats::Scalar writeEnergy; 32710618SOmar.Naji@arm.com Stats::Scalar refreshEnergy; 32810618SOmar.Naji@arm.com 32910618SOmar.Naji@arm.com /* 33010618SOmar.Naji@arm.com * Active Background Energy 33110618SOmar.Naji@arm.com */ 33210618SOmar.Naji@arm.com Stats::Scalar actBackEnergy; 33310618SOmar.Naji@arm.com 33410618SOmar.Naji@arm.com /* 33510618SOmar.Naji@arm.com * Precharge Background Energy 33610618SOmar.Naji@arm.com */ 33710618SOmar.Naji@arm.com Stats::Scalar preBackEnergy; 33810618SOmar.Naji@arm.com 33911678Swendy.elsasser@arm.com /* 34011678Swendy.elsasser@arm.com * Active Power-Down Energy 34111678Swendy.elsasser@arm.com */ 34211678Swendy.elsasser@arm.com Stats::Scalar actPowerDownEnergy; 34311678Swendy.elsasser@arm.com 34411678Swendy.elsasser@arm.com /* 34511678Swendy.elsasser@arm.com * Precharge Power-Down Energy 34611678Swendy.elsasser@arm.com */ 34711678Swendy.elsasser@arm.com Stats::Scalar prePowerDownEnergy; 34811678Swendy.elsasser@arm.com 34911678Swendy.elsasser@arm.com /* 35011678Swendy.elsasser@arm.com * self Refresh Energy 35111678Swendy.elsasser@arm.com */ 35211678Swendy.elsasser@arm.com Stats::Scalar selfRefreshEnergy; 35311678Swendy.elsasser@arm.com 35410618SOmar.Naji@arm.com Stats::Scalar totalEnergy; 35510618SOmar.Naji@arm.com Stats::Scalar averagePower; 35610618SOmar.Naji@arm.com 35710618SOmar.Naji@arm.com /** 35811678Swendy.elsasser@arm.com * Stat to track total DRAM idle time 35911678Swendy.elsasser@arm.com * 36011678Swendy.elsasser@arm.com */ 36111678Swendy.elsasser@arm.com Stats::Scalar totalIdleTime; 36211678Swendy.elsasser@arm.com 36311678Swendy.elsasser@arm.com /** 36410618SOmar.Naji@arm.com * Track time spent in each power state. 36510618SOmar.Naji@arm.com */ 36610618SOmar.Naji@arm.com Stats::Vector pwrStateTime; 36710618SOmar.Naji@arm.com 36810618SOmar.Naji@arm.com /** 36910618SOmar.Naji@arm.com * Function to update Power Stats 37010618SOmar.Naji@arm.com */ 37110618SOmar.Naji@arm.com void updatePowerStats(); 37210618SOmar.Naji@arm.com 37310618SOmar.Naji@arm.com /** 37410618SOmar.Naji@arm.com * Schedule a power state transition in the future, and 37510618SOmar.Naji@arm.com * potentially override an already scheduled transition. 37610618SOmar.Naji@arm.com * 37710618SOmar.Naji@arm.com * @param pwr_state Power state to transition to 37810618SOmar.Naji@arm.com * @param tick Tick when transition should take place 37910618SOmar.Naji@arm.com */ 38010618SOmar.Naji@arm.com void schedulePowerEvent(PowerState pwr_state, Tick tick); 38110618SOmar.Naji@arm.com 38210618SOmar.Naji@arm.com public: 38310618SOmar.Naji@arm.com 38410618SOmar.Naji@arm.com /** 38511678Swendy.elsasser@arm.com * Current power state. 38611678Swendy.elsasser@arm.com */ 38711678Swendy.elsasser@arm.com PowerState pwrState; 38811678Swendy.elsasser@arm.com 38911678Swendy.elsasser@arm.com /** 39011678Swendy.elsasser@arm.com * current refresh state 39111678Swendy.elsasser@arm.com */ 39211678Swendy.elsasser@arm.com RefreshState refreshState; 39311678Swendy.elsasser@arm.com 39411678Swendy.elsasser@arm.com /** 39511678Swendy.elsasser@arm.com * rank is in or transitioning to power-down or self-refresh 39611678Swendy.elsasser@arm.com */ 39711678Swendy.elsasser@arm.com bool inLowPowerState; 39811678Swendy.elsasser@arm.com 39911678Swendy.elsasser@arm.com /** 40010618SOmar.Naji@arm.com * Current Rank index 40110618SOmar.Naji@arm.com */ 40210618SOmar.Naji@arm.com uint8_t rank; 40310618SOmar.Naji@arm.com 40411678Swendy.elsasser@arm.com /** 40511678Swendy.elsasser@arm.com * Track number of packets in read queue going to this rank 40611678Swendy.elsasser@arm.com */ 40711678Swendy.elsasser@arm.com uint32_t readEntries; 40811678Swendy.elsasser@arm.com 40911678Swendy.elsasser@arm.com /** 41011678Swendy.elsasser@arm.com * Track number of packets in write queue going to this rank 41111678Swendy.elsasser@arm.com */ 41211678Swendy.elsasser@arm.com uint32_t writeEntries; 41311678Swendy.elsasser@arm.com 41411678Swendy.elsasser@arm.com /** 41511678Swendy.elsasser@arm.com * Number of ACT, RD, and WR events currently scheduled 41611678Swendy.elsasser@arm.com * Incremented when a refresh event is started as well 41711678Swendy.elsasser@arm.com * Used to determine when a low-power state can be entered 41811678Swendy.elsasser@arm.com */ 41911678Swendy.elsasser@arm.com uint8_t outstandingEvents; 42011678Swendy.elsasser@arm.com 42111678Swendy.elsasser@arm.com /** 42211678Swendy.elsasser@arm.com * delay power-down and self-refresh exit until this requirement is met 42311678Swendy.elsasser@arm.com */ 42411678Swendy.elsasser@arm.com Tick wakeUpAllowedAt; 42511678Swendy.elsasser@arm.com 42610618SOmar.Naji@arm.com /** 42710618SOmar.Naji@arm.com * One DRAMPower instance per rank 42810618SOmar.Naji@arm.com */ 42910618SOmar.Naji@arm.com DRAMPower power; 43010618SOmar.Naji@arm.com 43110618SOmar.Naji@arm.com /** 43211675Swendy.elsasser@arm.com * List of comamnds issued, to be sent to DRAMPpower at refresh 43311675Swendy.elsasser@arm.com * and stats dump. Keep commands here since commands to different 43411675Swendy.elsasser@arm.com * banks are added out of order. Will only pass commands up to 43511675Swendy.elsasser@arm.com * curTick() to DRAMPower after sorting. 43611675Swendy.elsasser@arm.com */ 43711675Swendy.elsasser@arm.com std::vector<Command> cmdList; 43811675Swendy.elsasser@arm.com 43911675Swendy.elsasser@arm.com /** 44010618SOmar.Naji@arm.com * Vector of Banks. Each rank is made of several devices which in 44110618SOmar.Naji@arm.com * term are made from several banks. 44210618SOmar.Naji@arm.com */ 44310618SOmar.Naji@arm.com std::vector<Bank> banks; 44410618SOmar.Naji@arm.com 44510618SOmar.Naji@arm.com /** 44610618SOmar.Naji@arm.com * To track number of banks which are currently active for 44710618SOmar.Naji@arm.com * this rank. 44810618SOmar.Naji@arm.com */ 44910618SOmar.Naji@arm.com unsigned int numBanksActive; 45010618SOmar.Naji@arm.com 45110618SOmar.Naji@arm.com /** List to keep track of activate ticks */ 45210618SOmar.Naji@arm.com std::deque<Tick> actTicks; 45310618SOmar.Naji@arm.com 45410618SOmar.Naji@arm.com Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p); 45510618SOmar.Naji@arm.com 45610618SOmar.Naji@arm.com const std::string name() const 45710618SOmar.Naji@arm.com { 45810618SOmar.Naji@arm.com return csprintf("%s_%d", memory.name(), rank); 45910618SOmar.Naji@arm.com } 46010618SOmar.Naji@arm.com 46110618SOmar.Naji@arm.com /** 46210618SOmar.Naji@arm.com * Kick off accounting for power and refresh states and 46310618SOmar.Naji@arm.com * schedule initial refresh. 46410618SOmar.Naji@arm.com * 46510618SOmar.Naji@arm.com * @param ref_tick Tick for first refresh 46610618SOmar.Naji@arm.com */ 46710618SOmar.Naji@arm.com void startup(Tick ref_tick); 46810618SOmar.Naji@arm.com 46910618SOmar.Naji@arm.com /** 47010619Sandreas.hansson@arm.com * Stop the refresh events. 47110619Sandreas.hansson@arm.com */ 47210619Sandreas.hansson@arm.com void suspend(); 47310619Sandreas.hansson@arm.com 47410619Sandreas.hansson@arm.com /** 47510618SOmar.Naji@arm.com * Check if the current rank is available for scheduling. 47611678Swendy.elsasser@arm.com * Rank will be unavailable if refresh is ongoing. 47711678Swendy.elsasser@arm.com * This includes refresh events explicitly scheduled from the the 47811678Swendy.elsasser@arm.com * controller or memory initiated events which will occur during 47911678Swendy.elsasser@arm.com * self-refresh mode. 48010618SOmar.Naji@arm.com * 48110618SOmar.Naji@arm.com * @param Return true if the rank is idle from a refresh point of view 48210618SOmar.Naji@arm.com */ 48310618SOmar.Naji@arm.com bool isAvailable() const { return refreshState == REF_IDLE; } 48410618SOmar.Naji@arm.com 48510618SOmar.Naji@arm.com /** 48611676Swendy.elsasser@arm.com * Check if the current rank has all banks closed and is not 48711676Swendy.elsasser@arm.com * in a low power state 48811676Swendy.elsasser@arm.com * 48911676Swendy.elsasser@arm.com * @param Return true if the rank is idle from a bank 49011676Swendy.elsasser@arm.com * and power point of view 49111676Swendy.elsasser@arm.com */ 49211676Swendy.elsasser@arm.com bool inPwrIdleState() const { return pwrState == PWR_IDLE; } 49311676Swendy.elsasser@arm.com 49411676Swendy.elsasser@arm.com /** 49511678Swendy.elsasser@arm.com * Trigger a self-refresh exit if there are entries enqueued 49611678Swendy.elsasser@arm.com * Exit if there are any read entries regardless of the bus state. 49711678Swendy.elsasser@arm.com * If we are currently issuing write commands, exit if we have any 49811678Swendy.elsasser@arm.com * write commands enqueued as well. 49911678Swendy.elsasser@arm.com * Could expand this in the future to analyze state of entire queue 50011678Swendy.elsasser@arm.com * if needed. 50111678Swendy.elsasser@arm.com * 50211678Swendy.elsasser@arm.com * @return boolean indicating self-refresh exit should be scheduled 50311678Swendy.elsasser@arm.com */ 50411678Swendy.elsasser@arm.com bool forceSelfRefreshExit() const { 50511678Swendy.elsasser@arm.com return (readEntries != 0) || 50611678Swendy.elsasser@arm.com ((memory.busStateNext == WRITE) && (writeEntries != 0)); 50711678Swendy.elsasser@arm.com } 50811678Swendy.elsasser@arm.com 50911678Swendy.elsasser@arm.com /** 51011678Swendy.elsasser@arm.com * Check if the current rank is idle and should enter a low-pwer state 51111678Swendy.elsasser@arm.com * 51211678Swendy.elsasser@arm.com * @param Return true if the there are no read commands in Q 51311678Swendy.elsasser@arm.com * and there are no outstanding events 51411678Swendy.elsasser@arm.com */ 51511678Swendy.elsasser@arm.com bool lowPowerEntryReady() const; 51611678Swendy.elsasser@arm.com 51711678Swendy.elsasser@arm.com /** 51810618SOmar.Naji@arm.com * Let the rank check if it was waiting for requests to drain 51910618SOmar.Naji@arm.com * to allow it to transition states. 52010618SOmar.Naji@arm.com */ 52110618SOmar.Naji@arm.com void checkDrainDone(); 52210618SOmar.Naji@arm.com 52311675Swendy.elsasser@arm.com /** 52411675Swendy.elsasser@arm.com * Push command out of cmdList queue that are scheduled at 52511675Swendy.elsasser@arm.com * or before curTick() to DRAMPower library 52611675Swendy.elsasser@arm.com * All commands before curTick are guaranteed to be complete 52711675Swendy.elsasser@arm.com * and can safely be flushed. 52811675Swendy.elsasser@arm.com */ 52911675Swendy.elsasser@arm.com void flushCmdList(); 53011675Swendy.elsasser@arm.com 53110618SOmar.Naji@arm.com /* 53210618SOmar.Naji@arm.com * Function to register Stats 53310618SOmar.Naji@arm.com */ 53410618SOmar.Naji@arm.com void regStats(); 53510618SOmar.Naji@arm.com 53611677Swendy.elsasser@arm.com /** 53711677Swendy.elsasser@arm.com * Computes stats just prior to dump event 53811677Swendy.elsasser@arm.com */ 53911677Swendy.elsasser@arm.com void computeStats(); 54011677Swendy.elsasser@arm.com 54111678Swendy.elsasser@arm.com /** 54211678Swendy.elsasser@arm.com * Schedule a transition to power-down (sleep) 54311678Swendy.elsasser@arm.com * 54411678Swendy.elsasser@arm.com * @param pwr_state Power state to transition to 54511678Swendy.elsasser@arm.com * @param tick Absolute tick when transition should take place 54611678Swendy.elsasser@arm.com */ 54711678Swendy.elsasser@arm.com void powerDownSleep(PowerState pwr_state, Tick tick); 54811678Swendy.elsasser@arm.com 54911678Swendy.elsasser@arm.com /** 55011678Swendy.elsasser@arm.com * schedule and event to wake-up from power-down or self-refresh 55111678Swendy.elsasser@arm.com * and update bank timing parameters 55211678Swendy.elsasser@arm.com * 55311678Swendy.elsasser@arm.com * @param exit_delay Relative tick defining the delay required between 55411678Swendy.elsasser@arm.com * low-power exit and the next command 55511678Swendy.elsasser@arm.com */ 55611678Swendy.elsasser@arm.com void scheduleWakeUpEvent(Tick exit_delay); 55711678Swendy.elsasser@arm.com 55811678Swendy.elsasser@arm.com void processWriteDoneEvent(); 55911678Swendy.elsasser@arm.com EventWrapper<Rank, &Rank::processWriteDoneEvent> 56011678Swendy.elsasser@arm.com writeDoneEvent; 56111678Swendy.elsasser@arm.com 56210618SOmar.Naji@arm.com void processActivateEvent(); 56310618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processActivateEvent> 56410618SOmar.Naji@arm.com activateEvent; 56510618SOmar.Naji@arm.com 56610618SOmar.Naji@arm.com void processPrechargeEvent(); 56710618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processPrechargeEvent> 56810618SOmar.Naji@arm.com prechargeEvent; 56910618SOmar.Naji@arm.com 57010618SOmar.Naji@arm.com void processRefreshEvent(); 57110618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processRefreshEvent> 57210618SOmar.Naji@arm.com refreshEvent; 57310618SOmar.Naji@arm.com 57410618SOmar.Naji@arm.com void processPowerEvent(); 57510618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processPowerEvent> 57610618SOmar.Naji@arm.com powerEvent; 57710618SOmar.Naji@arm.com 57811678Swendy.elsasser@arm.com void processWakeUpEvent(); 57911678Swendy.elsasser@arm.com EventWrapper<Rank, &Rank::processWakeUpEvent> 58011678Swendy.elsasser@arm.com wakeUpEvent; 58111678Swendy.elsasser@arm.com 58210618SOmar.Naji@arm.com }; 58310618SOmar.Naji@arm.com 58411677Swendy.elsasser@arm.com // define the process to compute stats on simulation exit 58511677Swendy.elsasser@arm.com // defined per rank as the per rank stats are based on state 58611677Swendy.elsasser@arm.com // transition and periodically updated, requiring re-sync at 58711677Swendy.elsasser@arm.com // exit. 58811677Swendy.elsasser@arm.com class RankDumpCallback : public Callback 58911677Swendy.elsasser@arm.com { 59011677Swendy.elsasser@arm.com Rank *ranks; 59111677Swendy.elsasser@arm.com public: 59211677Swendy.elsasser@arm.com RankDumpCallback(Rank *r) : ranks(r) {} 59311677Swendy.elsasser@arm.com virtual void process() { ranks->computeStats(); }; 59411677Swendy.elsasser@arm.com }; 59511677Swendy.elsasser@arm.com 5969243SN/A /** 5979831SN/A * A burst helper helps organize and manage a packet that is larger than 5989831SN/A * the DRAM burst size. A system packet that is larger than the burst size 5999831SN/A * is split into multiple DRAM packets and all those DRAM packets point to 6009831SN/A * a single burst helper such that we know when the whole packet is served. 6019831SN/A */ 6029831SN/A class BurstHelper { 6039831SN/A 6049831SN/A public: 6059831SN/A 6069831SN/A /** Number of DRAM bursts requred for a system packet **/ 6079831SN/A const unsigned int burstCount; 6089831SN/A 6099831SN/A /** Number of DRAM bursts serviced so far for a system packet **/ 6109831SN/A unsigned int burstsServiced; 6119831SN/A 6129831SN/A BurstHelper(unsigned int _burstCount) 6139831SN/A : burstCount(_burstCount), burstsServiced(0) 61410618SOmar.Naji@arm.com { } 6159831SN/A }; 6169831SN/A 6179831SN/A /** 6189243SN/A * A DRAM packet stores packets along with the timestamp of when 6199243SN/A * the packet entered the queue, and also the decoded address. 6209243SN/A */ 6219243SN/A class DRAMPacket { 6229243SN/A 6239243SN/A public: 6249243SN/A 6259243SN/A /** When did request enter the controller */ 6269243SN/A const Tick entryTime; 6279243SN/A 6289243SN/A /** When will request leave the controller */ 6299243SN/A Tick readyTime; 6309243SN/A 6319243SN/A /** This comes from the outside world */ 6329243SN/A const PacketPtr pkt; 6339243SN/A 6349966SN/A const bool isRead; 6359966SN/A 6369243SN/A /** Will be populated by address decoder */ 6379243SN/A const uint8_t rank; 6389967SN/A const uint8_t bank; 63910245Sandreas.hansson@arm.com const uint32_t row; 6409831SN/A 6419831SN/A /** 6429967SN/A * Bank id is calculated considering banks in all the ranks 6439967SN/A * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and 6449967SN/A * bankId = 8 --> rank1, bank0 6459967SN/A */ 6469967SN/A const uint16_t bankId; 6479967SN/A 6489967SN/A /** 6499831SN/A * The starting address of the DRAM packet. 6509831SN/A * This address could be unaligned to burst size boundaries. The 6519831SN/A * reason is to keep the address offset so we can accurately check 6529831SN/A * incoming read packets with packets in the write queue. 6539831SN/A */ 6549832SN/A Addr addr; 6559831SN/A 6569831SN/A /** 6579831SN/A * The size of this dram packet in bytes 6589831SN/A * It is always equal or smaller than DRAM burst size 6599831SN/A */ 6609832SN/A unsigned int size; 6619831SN/A 6629831SN/A /** 6639831SN/A * A pointer to the BurstHelper if this DRAMPacket is a split packet 6649831SN/A * If not a split packet (common case), this is set to NULL 6659831SN/A */ 6669831SN/A BurstHelper* burstHelper; 6679967SN/A Bank& bankRef; 66810618SOmar.Naji@arm.com Rank& rankRef; 6699243SN/A 6709967SN/A DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank, 67110245Sandreas.hansson@arm.com uint32_t _row, uint16_t bank_id, Addr _addr, 67210618SOmar.Naji@arm.com unsigned int _size, Bank& bank_ref, Rank& rank_ref) 6739243SN/A : entryTime(curTick()), readyTime(curTick()), 6749967SN/A pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row), 6759967SN/A bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL), 67610618SOmar.Naji@arm.com bankRef(bank_ref), rankRef(rank_ref) 6779243SN/A { } 6789243SN/A 6799243SN/A }; 6809243SN/A 6819243SN/A /** 6829243SN/A * Bunch of things requires to setup "events" in gem5 68310206Sandreas.hansson@arm.com * When event "respondEvent" occurs for example, the method 68410206Sandreas.hansson@arm.com * processRespondEvent is called; no parameters are allowed 6859243SN/A * in these methods 6869243SN/A */ 68710208Sandreas.hansson@arm.com void processNextReqEvent(); 68810208Sandreas.hansson@arm.com EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent; 68910208Sandreas.hansson@arm.com 6909243SN/A void processRespondEvent(); 69110146Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent; 6929243SN/A 6939243SN/A /** 6949243SN/A * Check if the read queue has room for more entries 6959243SN/A * 6969831SN/A * @param pktCount The number of entries needed in the read queue 6979243SN/A * @return true if read queue is full, false otherwise 6989243SN/A */ 6999831SN/A bool readQueueFull(unsigned int pktCount) const; 7009243SN/A 7019243SN/A /** 7029243SN/A * Check if the write queue has room for more entries 7039243SN/A * 7049831SN/A * @param pktCount The number of entries needed in the write queue 7059243SN/A * @return true if write queue is full, false otherwise 7069243SN/A */ 7079831SN/A bool writeQueueFull(unsigned int pktCount) const; 7089243SN/A 7099243SN/A /** 7109243SN/A * When a new read comes in, first check if the write q has a 7119243SN/A * pending request to the same address.\ If not, decode the 7129831SN/A * address to populate rank/bank/row, create one or mutliple 7139831SN/A * "dram_pkt", and push them to the back of the read queue.\ 7149831SN/A * If this is the only 7159243SN/A * read request in the system, schedule an event to start 7169243SN/A * servicing it. 7179243SN/A * 7189243SN/A * @param pkt The request packet from the outside world 7199831SN/A * @param pktCount The number of DRAM bursts the pkt 7209831SN/A * translate to. If pkt size is larger then one full burst, 7219831SN/A * then pktCount is greater than one. 7229243SN/A */ 7239831SN/A void addToReadQueue(PacketPtr pkt, unsigned int pktCount); 7249243SN/A 7259243SN/A /** 7269243SN/A * Decode the incoming pkt, create a dram_pkt and push to the 7279243SN/A * back of the write queue. \If the write q length is more than 7289243SN/A * the threshold specified by the user, ie the queue is beginning 7299243SN/A * to get full, stop reads, and start draining writes. 7309243SN/A * 7319243SN/A * @param pkt The request packet from the outside world 7329831SN/A * @param pktCount The number of DRAM bursts the pkt 7339831SN/A * translate to. If pkt size is larger then one full burst, 7349831SN/A * then pktCount is greater than one. 7359243SN/A */ 7369831SN/A void addToWriteQueue(PacketPtr pkt, unsigned int pktCount); 7379243SN/A 7389243SN/A /** 7399243SN/A * Actually do the DRAM access - figure out the latency it 7409243SN/A * will take to service the req based on bank state, channel state etc 7419243SN/A * and then update those states to account for this request.\ Based 7429243SN/A * on this, update the packet's "readyTime" and move it to the 7439243SN/A * response q from where it will eventually go back to the outside 7449243SN/A * world. 7459243SN/A * 7469243SN/A * @param pkt The DRAM packet created from the outside world pkt 7479243SN/A */ 7489243SN/A void doDRAMAccess(DRAMPacket* dram_pkt); 7499243SN/A 7509243SN/A /** 7519243SN/A * When a packet reaches its "readyTime" in the response Q, 7529243SN/A * use the "access()" method in AbstractMemory to actually 7539243SN/A * create the response packet, and send it back to the outside 7549243SN/A * world requestor. 7559243SN/A * 7569243SN/A * @param pkt The packet from the outside world 7579726SN/A * @param static_latency Static latency to add before sending the packet 7589243SN/A */ 7599726SN/A void accessAndRespond(PacketPtr pkt, Tick static_latency); 7609243SN/A 7619243SN/A /** 7629243SN/A * Address decoder to figure out physical mapping onto ranks, 7639831SN/A * banks, and rows. This function is called multiple times on the same 7649831SN/A * system packet if the pakcet is larger than burst of the memory. The 7659831SN/A * dramPktAddr is used for the offset within the packet. 7669243SN/A * 7679243SN/A * @param pkt The packet from the outside world 7689831SN/A * @param dramPktAddr The starting address of the DRAM packet 7699831SN/A * @param size The size of the DRAM packet in bytes 7709966SN/A * @param isRead Is the request for a read or a write to DRAM 7719243SN/A * @return A DRAMPacket pointer with the decoded information 7729243SN/A */ 77310143SN/A DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, 77410143SN/A bool isRead); 7759243SN/A 7769243SN/A /** 77710206Sandreas.hansson@arm.com * The memory schduler/arbiter - picks which request needs to 7789567SN/A * go next, based on the specified policy such as FCFS or FR-FCFS 77910206Sandreas.hansson@arm.com * and moves it to the head of the queue. 78010393Swendy.elsasser@arm.com * Prioritizes accesses to the same rank as previous burst unless 78110393Swendy.elsasser@arm.com * controller is switching command type. 78210393Swendy.elsasser@arm.com * 78310393Swendy.elsasser@arm.com * @param queue Queued requests to consider 78410890Swendy.elsasser@arm.com * @param extra_col_delay Any extra delay due to a read/write switch 78510618SOmar.Naji@arm.com * @return true if a packet is scheduled to a rank which is available else 78610618SOmar.Naji@arm.com * false 7879243SN/A */ 78810890Swendy.elsasser@arm.com bool chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay); 7899243SN/A 7909243SN/A /** 7919974SN/A * For FR-FCFS policy reorder the read/write queue depending on row buffer 79210890Swendy.elsasser@arm.com * hits and earliest bursts available in DRAM 79310393Swendy.elsasser@arm.com * 79410393Swendy.elsasser@arm.com * @param queue Queued requests to consider 79510890Swendy.elsasser@arm.com * @param extra_col_delay Any extra delay due to a read/write switch 79610618SOmar.Naji@arm.com * @return true if a packet is scheduled to a rank which is available else 79710618SOmar.Naji@arm.com * false 7989974SN/A */ 79910890Swendy.elsasser@arm.com bool reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay); 8009974SN/A 8019974SN/A /** 80210211Sandreas.hansson@arm.com * Find which are the earliest banks ready to issue an activate 80310211Sandreas.hansson@arm.com * for the enqueued requests. Assumes maximum of 64 banks per DIMM 80410393Swendy.elsasser@arm.com * Also checks if the bank is already prepped. 8059967SN/A * 80610393Swendy.elsasser@arm.com * @param queue Queued requests to consider 80710890Swendy.elsasser@arm.com * @param time of seamless burst command 8089967SN/A * @return One-hot encoded mask of bank indices 80910890Swendy.elsasser@arm.com * @return boolean indicating burst can issue seamlessly, with no gaps 8109967SN/A */ 81110890Swendy.elsasser@arm.com std::pair<uint64_t, bool> minBankPrep(const std::deque<DRAMPacket*>& queue, 81210890Swendy.elsasser@arm.com Tick min_col_at) const; 8139488SN/A 8149488SN/A /** 8159488SN/A * Keep track of when row activations happen, in order to enforce 8169488SN/A * the maximum number of activations in the activation window. The 8179488SN/A * method updates the time that the banks become available based 8189488SN/A * on the current limits. 81910210Sandreas.hansson@arm.com * 82010618SOmar.Naji@arm.com * @param rank_ref Reference to the rank 82110618SOmar.Naji@arm.com * @param bank_ref Reference to the bank 82210210Sandreas.hansson@arm.com * @param act_tick Time when the activation takes place 82310210Sandreas.hansson@arm.com * @param row Index of the row 8249488SN/A */ 82510618SOmar.Naji@arm.com void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick, 82610618SOmar.Naji@arm.com uint32_t row); 82710207Sandreas.hansson@arm.com 82810207Sandreas.hansson@arm.com /** 82910207Sandreas.hansson@arm.com * Precharge a given bank and also update when the precharge is 83010207Sandreas.hansson@arm.com * done. This will also deal with any stats related to the 83110207Sandreas.hansson@arm.com * accesses to the open page. 83210207Sandreas.hansson@arm.com * 83310618SOmar.Naji@arm.com * @param rank_ref The rank to precharge 83410247Sandreas.hansson@arm.com * @param bank_ref The bank to precharge 83510211Sandreas.hansson@arm.com * @param pre_at Time when the precharge takes place 83610247Sandreas.hansson@arm.com * @param trace Is this an auto precharge then do not add to trace 83710207Sandreas.hansson@arm.com */ 83810618SOmar.Naji@arm.com void prechargeBank(Rank& rank_ref, Bank& bank_ref, 83910618SOmar.Naji@arm.com Tick pre_at, bool trace = true); 8409488SN/A 84110143SN/A /** 84210143SN/A * Used for debugging to observe the contents of the queues. 84310143SN/A */ 8449243SN/A void printQs() const; 8459243SN/A 8469243SN/A /** 84710889Sandreas.hansson@arm.com * Burst-align an address. 84810889Sandreas.hansson@arm.com * 84910889Sandreas.hansson@arm.com * @param addr The potentially unaligned address 85010889Sandreas.hansson@arm.com * 85110889Sandreas.hansson@arm.com * @return An address aligned to a DRAM burst 85210889Sandreas.hansson@arm.com */ 85310889Sandreas.hansson@arm.com Addr burstAlign(Addr addr) const { return (addr & ~(Addr(burstSize - 1))); } 85410889Sandreas.hansson@arm.com 85510889Sandreas.hansson@arm.com /** 8569243SN/A * The controller's main read and write queues 8579243SN/A */ 8589833SN/A std::deque<DRAMPacket*> readQueue; 8599833SN/A std::deque<DRAMPacket*> writeQueue; 8609243SN/A 8619243SN/A /** 86210889Sandreas.hansson@arm.com * To avoid iterating over the write queue to check for 86310889Sandreas.hansson@arm.com * overlapping transactions, maintain a set of burst addresses 86410889Sandreas.hansson@arm.com * that are currently queued. Since we merge writes to the same 86510889Sandreas.hansson@arm.com * location we never have more than one address to the same burst 86610889Sandreas.hansson@arm.com * address. 86710889Sandreas.hansson@arm.com */ 86810889Sandreas.hansson@arm.com std::unordered_set<Addr> isInWriteQueue; 86910889Sandreas.hansson@arm.com 87010889Sandreas.hansson@arm.com /** 8719243SN/A * Response queue where read packets wait after we're done working 8729567SN/A * with them, but it's not time to send the response yet. The 8739567SN/A * responses are stored seperately mostly to keep the code clean 8749567SN/A * and help with events scheduling. For all logical purposes such 8759567SN/A * as sizing the read queue, this and the main read queue need to 8769567SN/A * be added together. 8779243SN/A */ 8789833SN/A std::deque<DRAMPacket*> respQueue; 8799243SN/A 8809567SN/A /** 88110618SOmar.Naji@arm.com * Vector of ranks 8829243SN/A */ 88310618SOmar.Naji@arm.com std::vector<Rank*> ranks; 8849243SN/A 8859243SN/A /** 8869243SN/A * The following are basic design parameters of the memory 8879831SN/A * controller, and are initialized based on parameter values. 8889831SN/A * The rowsPerBank is determined based on the capacity, number of 8899831SN/A * ranks and banks, the burst size, and the row buffer size. 8909243SN/A */ 89110489SOmar.Naji@arm.com const uint32_t deviceSize; 8929831SN/A const uint32_t deviceBusWidth; 8939831SN/A const uint32_t burstLength; 8949831SN/A const uint32_t deviceRowBufferSize; 8959831SN/A const uint32_t devicesPerRank; 8969831SN/A const uint32_t burstSize; 8979831SN/A const uint32_t rowBufferSize; 89810140SN/A const uint32_t columnsPerRowBuffer; 89910286Sandreas.hansson@arm.com const uint32_t columnsPerStripe; 9009243SN/A const uint32_t ranksPerChannel; 90110394Swendy.elsasser@arm.com const uint32_t bankGroupsPerRank; 90210394Swendy.elsasser@arm.com const bool bankGroupArch; 9039243SN/A const uint32_t banksPerRank; 9049566SN/A const uint32_t channels; 9059243SN/A uint32_t rowsPerBank; 9069243SN/A const uint32_t readBufferSize; 9079243SN/A const uint32_t writeBufferSize; 90810140SN/A const uint32_t writeHighThreshold; 90910140SN/A const uint32_t writeLowThreshold; 91010140SN/A const uint32_t minWritesPerSwitch; 91110140SN/A uint32_t writesThisTime; 91210147Sandreas.hansson@arm.com uint32_t readsThisTime; 9139243SN/A 9149243SN/A /** 9159243SN/A * Basic memory timing parameters initialized based on parameter 9169243SN/A * values. 9179243SN/A */ 91810286Sandreas.hansson@arm.com const Tick M5_CLASS_VAR_USED tCK; 9199243SN/A const Tick tWTR; 92010206Sandreas.hansson@arm.com const Tick tRTW; 92110393Swendy.elsasser@arm.com const Tick tCS; 9229243SN/A const Tick tBURST; 92310394Swendy.elsasser@arm.com const Tick tCCD_L; 9249243SN/A const Tick tRCD; 9259243SN/A const Tick tCL; 9269243SN/A const Tick tRP; 9279963SN/A const Tick tRAS; 92810210Sandreas.hansson@arm.com const Tick tWR; 92910212Sandreas.hansson@arm.com const Tick tRTP; 9309243SN/A const Tick tRFC; 9319243SN/A const Tick tREFI; 9329971SN/A const Tick tRRD; 93310394Swendy.elsasser@arm.com const Tick tRRD_L; 9349488SN/A const Tick tXAW; 93511673SOmar.Naji@arm.com const Tick tXP; 93611673SOmar.Naji@arm.com const Tick tXS; 9379488SN/A const uint32_t activationLimit; 9389243SN/A 9399243SN/A /** 9409243SN/A * Memory controller configuration initialized based on parameter 9419243SN/A * values. 9429243SN/A */ 9439243SN/A Enums::MemSched memSchedPolicy; 9449243SN/A Enums::AddrMap addrMapping; 9459243SN/A Enums::PageManage pageMgmt; 9469243SN/A 9479243SN/A /** 94810141SN/A * Max column accesses (read and write) per row, before forefully 94910141SN/A * closing it. 95010141SN/A */ 95110141SN/A const uint32_t maxAccessesPerRow; 95210141SN/A 95310141SN/A /** 9549726SN/A * Pipeline latency of the controller frontend. The frontend 9559726SN/A * contribution is added to writes (that complete when they are in 9569726SN/A * the write buffer) and reads that are serviced the write buffer. 9579726SN/A */ 9589726SN/A const Tick frontendLatency; 9599726SN/A 9609726SN/A /** 9619726SN/A * Pipeline latency of the backend and PHY. Along with the 9629726SN/A * frontend contribution, this latency is added to reads serviced 9639726SN/A * by the DRAM. 9649726SN/A */ 9659726SN/A const Tick backendLatency; 9669726SN/A 9679726SN/A /** 9689243SN/A * Till when has the main data bus been spoken for already? 9699243SN/A */ 9709243SN/A Tick busBusyUntil; 9719243SN/A 9729243SN/A Tick prevArrival; 9739243SN/A 97410206Sandreas.hansson@arm.com /** 97510206Sandreas.hansson@arm.com * The soonest you have to start thinking about the next request 97610206Sandreas.hansson@arm.com * is the longest access time that can occur before 97710206Sandreas.hansson@arm.com * busBusyUntil. Assuming you need to precharge, open a new row, 97810206Sandreas.hansson@arm.com * and access, it is tRP + tRCD + tCL. 97910206Sandreas.hansson@arm.com */ 98010206Sandreas.hansson@arm.com Tick nextReqTime; 9819972SN/A 9829243SN/A // All statistics that the model needs to capture 9839243SN/A Stats::Scalar readReqs; 9849243SN/A Stats::Scalar writeReqs; 9859831SN/A Stats::Scalar readBursts; 9869831SN/A Stats::Scalar writeBursts; 9879975SN/A Stats::Scalar bytesReadDRAM; 9889975SN/A Stats::Scalar bytesReadWrQ; 9899243SN/A Stats::Scalar bytesWritten; 9909977SN/A Stats::Scalar bytesReadSys; 9919977SN/A Stats::Scalar bytesWrittenSys; 9929243SN/A Stats::Scalar servicedByWrQ; 9939977SN/A Stats::Scalar mergedWrBursts; 9949243SN/A Stats::Scalar neitherReadNorWrite; 9959977SN/A Stats::Vector perBankRdBursts; 9969977SN/A Stats::Vector perBankWrBursts; 9979243SN/A Stats::Scalar numRdRetry; 9989243SN/A Stats::Scalar numWrRetry; 9999243SN/A Stats::Scalar totGap; 10009243SN/A Stats::Vector readPktSize; 10019243SN/A Stats::Vector writePktSize; 10029243SN/A Stats::Vector rdQLenPdf; 10039243SN/A Stats::Vector wrQLenPdf; 10049727SN/A Stats::Histogram bytesPerActivate; 100510147Sandreas.hansson@arm.com Stats::Histogram rdPerTurnAround; 100610147Sandreas.hansson@arm.com Stats::Histogram wrPerTurnAround; 10079243SN/A 10089243SN/A // Latencies summed over all requests 10099243SN/A Stats::Scalar totQLat; 10109243SN/A Stats::Scalar totMemAccLat; 10119243SN/A Stats::Scalar totBusLat; 10129243SN/A 10139243SN/A // Average latencies per request 10149243SN/A Stats::Formula avgQLat; 10159243SN/A Stats::Formula avgBusLat; 10169243SN/A Stats::Formula avgMemAccLat; 10179243SN/A 10189243SN/A // Average bandwidth 10199243SN/A Stats::Formula avgRdBW; 10209243SN/A Stats::Formula avgWrBW; 10219977SN/A Stats::Formula avgRdBWSys; 10229977SN/A Stats::Formula avgWrBWSys; 10239243SN/A Stats::Formula peakBW; 10249243SN/A Stats::Formula busUtil; 10259975SN/A Stats::Formula busUtilRead; 10269975SN/A Stats::Formula busUtilWrite; 10279243SN/A 10289243SN/A // Average queue lengths 10299243SN/A Stats::Average avgRdQLen; 10309243SN/A Stats::Average avgWrQLen; 10319243SN/A 10329243SN/A // Row hit count and rate 10339243SN/A Stats::Scalar readRowHits; 10349243SN/A Stats::Scalar writeRowHits; 10359243SN/A Stats::Formula readRowHitRate; 10369243SN/A Stats::Formula writeRowHitRate; 10379243SN/A Stats::Formula avgGap; 10389243SN/A 10399975SN/A // DRAM Power Calculation 10409975SN/A Stats::Formula pageHitRate; 10419975SN/A 104210393Swendy.elsasser@arm.com // Holds the value of the rank of burst issued 104310393Swendy.elsasser@arm.com uint8_t activeRank; 104410393Swendy.elsasser@arm.com 104510432SOmar.Naji@arm.com // timestamp offset 104610432SOmar.Naji@arm.com uint64_t timeStampOffset; 104710432SOmar.Naji@arm.com 104811190Sandreas.hansson@arm.com /** 104911190Sandreas.hansson@arm.com * Upstream caches need this packet until true is returned, so 105011190Sandreas.hansson@arm.com * hold it for deletion until a subsequent call 10519349SN/A */ 105211190Sandreas.hansson@arm.com std::unique_ptr<Packet> pendingDelete; 10539349SN/A 105410432SOmar.Naji@arm.com /** 105510618SOmar.Naji@arm.com * This function increments the energy when called. If stats are 105610618SOmar.Naji@arm.com * dumped periodically, note accumulated energy values will 105710618SOmar.Naji@arm.com * appear in the stats (even if the stats are reset). This is a 105810618SOmar.Naji@arm.com * result of the energy values coming from DRAMPower, and there 105910618SOmar.Naji@arm.com * is currently no support for resetting the state. 106010618SOmar.Naji@arm.com * 106110618SOmar.Naji@arm.com * @param rank Currrent rank 106210618SOmar.Naji@arm.com */ 106310618SOmar.Naji@arm.com void updatePowerStats(Rank& rank_ref); 106410432SOmar.Naji@arm.com 106510432SOmar.Naji@arm.com /** 106611675Swendy.elsasser@arm.com * Function for sorting Command structures based on timeStamp 106710432SOmar.Naji@arm.com * 106811675Swendy.elsasser@arm.com * @param a Memory Command 106911675Swendy.elsasser@arm.com * @param next Memory Command 107011675Swendy.elsasser@arm.com * @return true if timeStamp of Command 1 < timeStamp of Command 2 107110432SOmar.Naji@arm.com */ 107211675Swendy.elsasser@arm.com static bool sortTime(const Command& cmd, const Command& cmd_next) { 107311675Swendy.elsasser@arm.com return cmd.timeStamp < cmd_next.timeStamp; 107410432SOmar.Naji@arm.com }; 107510432SOmar.Naji@arm.com 10769243SN/A public: 10779243SN/A 107811169Sandreas.hansson@arm.com void regStats() override; 10799243SN/A 108010146Sandreas.hansson@arm.com DRAMCtrl(const DRAMCtrlParams* p); 10819243SN/A 108211168Sandreas.hansson@arm.com DrainState drain() override; 10839243SN/A 10849294SN/A virtual BaseSlavePort& getSlavePort(const std::string& if_name, 108511169Sandreas.hansson@arm.com PortID idx = InvalidPortID) override; 10869243SN/A 108711168Sandreas.hansson@arm.com virtual void init() override; 108811168Sandreas.hansson@arm.com virtual void startup() override; 108911168Sandreas.hansson@arm.com virtual void drainResume() override; 10909243SN/A 109111676Swendy.elsasser@arm.com /** 109211676Swendy.elsasser@arm.com * Return true once refresh is complete for all ranks and there are no 109311676Swendy.elsasser@arm.com * additional commands enqueued. (only evaluated when draining) 109411676Swendy.elsasser@arm.com * This will ensure that all banks are closed, power state is IDLE, and 109511676Swendy.elsasser@arm.com * power stats have been updated 109611676Swendy.elsasser@arm.com * 109711676Swendy.elsasser@arm.com * @return true if all ranks have refreshed, with no commands enqueued 109811676Swendy.elsasser@arm.com * 109911676Swendy.elsasser@arm.com */ 110011676Swendy.elsasser@arm.com bool allRanksDrained() const; 110111676Swendy.elsasser@arm.com 11029243SN/A protected: 11039243SN/A 11049243SN/A Tick recvAtomic(PacketPtr pkt); 11059243SN/A void recvFunctional(PacketPtr pkt); 11069243SN/A bool recvTimingReq(PacketPtr pkt); 11079243SN/A 11089243SN/A}; 11099243SN/A 111010146Sandreas.hansson@arm.com#endif //__MEM_DRAM_CTRL_HH__ 1111