dram_ctrl.hh revision 10489
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2012-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 439243SN/A */ 449243SN/A 459243SN/A/** 469243SN/A * @file 4710146Sandreas.hansson@arm.com * DRAMCtrl declaration 489243SN/A */ 499243SN/A 5010146Sandreas.hansson@arm.com#ifndef __MEM_DRAM_CTRL_HH__ 5110146Sandreas.hansson@arm.com#define __MEM_DRAM_CTRL_HH__ 529243SN/A 539488SN/A#include <deque> 549488SN/A 559243SN/A#include "base/statistics.hh" 569243SN/A#include "enums/AddrMap.hh" 579243SN/A#include "enums/MemSched.hh" 589243SN/A#include "enums/PageManage.hh" 599243SN/A#include "mem/abstract_mem.hh" 609243SN/A#include "mem/qport.hh" 6110146Sandreas.hansson@arm.com#include "params/DRAMCtrl.hh" 629243SN/A#include "sim/eventq.hh" 6310432SOmar.Naji@arm.com#include "mem/drampower.hh" 649243SN/A 659243SN/A/** 6610287Sandreas.hansson@arm.com * The DRAM controller is a single-channel memory controller capturing 6710287Sandreas.hansson@arm.com * the most important timing constraints associated with a 6810287Sandreas.hansson@arm.com * contemporary DRAM. For multi-channel memory systems, the controller 6910287Sandreas.hansson@arm.com * is combined with a crossbar model, with the channel address 7010287Sandreas.hansson@arm.com * interleaving taking part in the crossbar. 719243SN/A * 7210287Sandreas.hansson@arm.com * As a basic design principle, this controller 7310287Sandreas.hansson@arm.com * model is not cycle callable, but instead uses events to: 1) decide 7410287Sandreas.hansson@arm.com * when new decisions can be made, 2) when resources become available, 7510287Sandreas.hansson@arm.com * 3) when things are to be considered done, and 4) when to send 7610287Sandreas.hansson@arm.com * things back. Through these simple principles, the model delivers 7710287Sandreas.hansson@arm.com * high performance, and lots of flexibility, allowing users to 7810287Sandreas.hansson@arm.com * evaluate the system impact of a wide range of memory technologies, 7910287Sandreas.hansson@arm.com * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC. 8010287Sandreas.hansson@arm.com * 8110287Sandreas.hansson@arm.com * For more details, please see Hansson et al, "Simulating DRAM 8210287Sandreas.hansson@arm.com * controllers for future system architecture exploration", 8310287Sandreas.hansson@arm.com * Proc. ISPASS, 2014. If you use this model as part of your research 8410287Sandreas.hansson@arm.com * please cite the paper. 859243SN/A */ 8610146Sandreas.hansson@arm.comclass DRAMCtrl : public AbstractMemory 879243SN/A{ 889243SN/A 899243SN/A private: 909243SN/A 919243SN/A // For now, make use of a queued slave port to avoid dealing with 929243SN/A // flow control for the responses being sent back 939243SN/A class MemoryPort : public QueuedSlavePort 949243SN/A { 959243SN/A 969243SN/A SlavePacketQueue queue; 9710146Sandreas.hansson@arm.com DRAMCtrl& memory; 989243SN/A 999243SN/A public: 1009243SN/A 10110146Sandreas.hansson@arm.com MemoryPort(const std::string& name, DRAMCtrl& _memory); 1029243SN/A 1039243SN/A protected: 1049243SN/A 1059243SN/A Tick recvAtomic(PacketPtr pkt); 1069243SN/A 1079243SN/A void recvFunctional(PacketPtr pkt); 1089243SN/A 1099243SN/A bool recvTimingReq(PacketPtr); 1109243SN/A 1119243SN/A virtual AddrRangeList getAddrRanges() const; 1129243SN/A 1139243SN/A }; 1149243SN/A 1159243SN/A /** 1169243SN/A * Our incoming port, for a multi-ported controller add a crossbar 1179243SN/A * in front of it 1189243SN/A */ 1199243SN/A MemoryPort port; 1209243SN/A 1219243SN/A /** 1229243SN/A * Remember if we have to retry a request when available. 1239243SN/A */ 1249243SN/A bool retryRdReq; 1259243SN/A bool retryWrReq; 1269243SN/A 1279243SN/A /** 12810206Sandreas.hansson@arm.com * Bus state used to control the read/write switching and drive 12910206Sandreas.hansson@arm.com * the scheduling of the next request. 1309243SN/A */ 13110206Sandreas.hansson@arm.com enum BusState { 13210206Sandreas.hansson@arm.com READ = 0, 13310206Sandreas.hansson@arm.com READ_TO_WRITE, 13410206Sandreas.hansson@arm.com WRITE, 13510206Sandreas.hansson@arm.com WRITE_TO_READ 13610206Sandreas.hansson@arm.com }; 13710206Sandreas.hansson@arm.com 13810206Sandreas.hansson@arm.com BusState busState; 1399243SN/A 1409488SN/A /** List to keep track of activate ticks */ 1419969SN/A std::vector<std::deque<Tick>> actTicks; 1429488SN/A 1439243SN/A /** 14410210Sandreas.hansson@arm.com * A basic class to track the bank state, i.e. what row is 14510210Sandreas.hansson@arm.com * currently open (if any), when is the bank free to accept a new 14610211Sandreas.hansson@arm.com * column (read/write) command, when can it be precharged, and 14710211Sandreas.hansson@arm.com * when can it be activated. 14810210Sandreas.hansson@arm.com * 14910210Sandreas.hansson@arm.com * The bank also keeps track of how many bytes have been accessed 15010210Sandreas.hansson@arm.com * in the open row since it was opened. 1519243SN/A */ 1529243SN/A class Bank 1539243SN/A { 1549243SN/A 1559243SN/A public: 1569243SN/A 15710207Sandreas.hansson@arm.com static const uint32_t NO_ROW = -1; 1589243SN/A 1599243SN/A uint32_t openRow; 16010246Sandreas.hansson@arm.com uint8_t rank; 16110246Sandreas.hansson@arm.com uint8_t bank; 16210394Swendy.elsasser@arm.com uint8_t bankgr; 1639243SN/A 16410211Sandreas.hansson@arm.com Tick colAllowedAt; 16510210Sandreas.hansson@arm.com Tick preAllowedAt; 1669969SN/A Tick actAllowedAt; 1679243SN/A 16810141SN/A uint32_t rowAccesses; 1699727SN/A uint32_t bytesAccessed; 1709727SN/A 1719727SN/A Bank() : 17210394Swendy.elsasser@arm.com openRow(NO_ROW), rank(0), bank(0), bankgr(0), 17310246Sandreas.hansson@arm.com colAllowedAt(0), preAllowedAt(0), actAllowedAt(0), 17410141SN/A rowAccesses(0), bytesAccessed(0) 1759243SN/A { } 1769243SN/A }; 1779243SN/A 1789243SN/A /** 1799831SN/A * A burst helper helps organize and manage a packet that is larger than 1809831SN/A * the DRAM burst size. A system packet that is larger than the burst size 1819831SN/A * is split into multiple DRAM packets and all those DRAM packets point to 1829831SN/A * a single burst helper such that we know when the whole packet is served. 1839831SN/A */ 1849831SN/A class BurstHelper { 1859831SN/A 1869831SN/A public: 1879831SN/A 1889831SN/A /** Number of DRAM bursts requred for a system packet **/ 1899831SN/A const unsigned int burstCount; 1909831SN/A 1919831SN/A /** Number of DRAM bursts serviced so far for a system packet **/ 1929831SN/A unsigned int burstsServiced; 1939831SN/A 1949831SN/A BurstHelper(unsigned int _burstCount) 1959831SN/A : burstCount(_burstCount), burstsServiced(0) 1969831SN/A { } 1979831SN/A }; 1989831SN/A 1999831SN/A /** 2009243SN/A * A DRAM packet stores packets along with the timestamp of when 2019243SN/A * the packet entered the queue, and also the decoded address. 2029243SN/A */ 2039243SN/A class DRAMPacket { 2049243SN/A 2059243SN/A public: 2069243SN/A 2079243SN/A /** When did request enter the controller */ 2089243SN/A const Tick entryTime; 2099243SN/A 2109243SN/A /** When will request leave the controller */ 2119243SN/A Tick readyTime; 2129243SN/A 2139243SN/A /** This comes from the outside world */ 2149243SN/A const PacketPtr pkt; 2159243SN/A 2169966SN/A const bool isRead; 2179966SN/A 2189243SN/A /** Will be populated by address decoder */ 2199243SN/A const uint8_t rank; 2209967SN/A const uint8_t bank; 22110245Sandreas.hansson@arm.com const uint32_t row; 2229831SN/A 2239831SN/A /** 2249967SN/A * Bank id is calculated considering banks in all the ranks 2259967SN/A * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and 2269967SN/A * bankId = 8 --> rank1, bank0 2279967SN/A */ 2289967SN/A const uint16_t bankId; 2299967SN/A 2309967SN/A /** 2319831SN/A * The starting address of the DRAM packet. 2329831SN/A * This address could be unaligned to burst size boundaries. The 2339831SN/A * reason is to keep the address offset so we can accurately check 2349831SN/A * incoming read packets with packets in the write queue. 2359831SN/A */ 2369832SN/A Addr addr; 2379831SN/A 2389831SN/A /** 2399831SN/A * The size of this dram packet in bytes 2409831SN/A * It is always equal or smaller than DRAM burst size 2419831SN/A */ 2429832SN/A unsigned int size; 2439831SN/A 2449831SN/A /** 2459831SN/A * A pointer to the BurstHelper if this DRAMPacket is a split packet 2469831SN/A * If not a split packet (common case), this is set to NULL 2479831SN/A */ 2489831SN/A BurstHelper* burstHelper; 2499967SN/A Bank& bankRef; 2509243SN/A 2519967SN/A DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank, 25210245Sandreas.hansson@arm.com uint32_t _row, uint16_t bank_id, Addr _addr, 2539967SN/A unsigned int _size, Bank& bank_ref) 2549243SN/A : entryTime(curTick()), readyTime(curTick()), 2559967SN/A pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row), 2569967SN/A bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL), 2579967SN/A bankRef(bank_ref) 2589243SN/A { } 2599243SN/A 2609243SN/A }; 2619243SN/A 2629243SN/A /** 2639243SN/A * Bunch of things requires to setup "events" in gem5 26410206Sandreas.hansson@arm.com * When event "respondEvent" occurs for example, the method 26510206Sandreas.hansson@arm.com * processRespondEvent is called; no parameters are allowed 2669243SN/A * in these methods 2679243SN/A */ 26810208Sandreas.hansson@arm.com void processNextReqEvent(); 26910208Sandreas.hansson@arm.com EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent; 27010208Sandreas.hansson@arm.com 2719243SN/A void processRespondEvent(); 27210146Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent; 2739243SN/A 27410208Sandreas.hansson@arm.com void processActivateEvent(); 27510208Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processActivateEvent> activateEvent; 27610208Sandreas.hansson@arm.com 27710208Sandreas.hansson@arm.com void processPrechargeEvent(); 27810208Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processPrechargeEvent> prechargeEvent; 27910208Sandreas.hansson@arm.com 2809243SN/A void processRefreshEvent(); 28110146Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processRefreshEvent> refreshEvent; 2829243SN/A 28310208Sandreas.hansson@arm.com void processPowerEvent(); 28410208Sandreas.hansson@arm.com EventWrapper<DRAMCtrl,&DRAMCtrl::processPowerEvent> powerEvent; 2859243SN/A 2869243SN/A /** 2879243SN/A * Check if the read queue has room for more entries 2889243SN/A * 2899831SN/A * @param pktCount The number of entries needed in the read queue 2909243SN/A * @return true if read queue is full, false otherwise 2919243SN/A */ 2929831SN/A bool readQueueFull(unsigned int pktCount) const; 2939243SN/A 2949243SN/A /** 2959243SN/A * Check if the write queue has room for more entries 2969243SN/A * 2979831SN/A * @param pktCount The number of entries needed in the write queue 2989243SN/A * @return true if write queue is full, false otherwise 2999243SN/A */ 3009831SN/A bool writeQueueFull(unsigned int pktCount) const; 3019243SN/A 3029243SN/A /** 3039243SN/A * When a new read comes in, first check if the write q has a 3049243SN/A * pending request to the same address.\ If not, decode the 3059831SN/A * address to populate rank/bank/row, create one or mutliple 3069831SN/A * "dram_pkt", and push them to the back of the read queue.\ 3079831SN/A * If this is the only 3089243SN/A * read request in the system, schedule an event to start 3099243SN/A * servicing it. 3109243SN/A * 3119243SN/A * @param pkt The request packet from the outside world 3129831SN/A * @param pktCount The number of DRAM bursts the pkt 3139831SN/A * translate to. If pkt size is larger then one full burst, 3149831SN/A * then pktCount is greater than one. 3159243SN/A */ 3169831SN/A void addToReadQueue(PacketPtr pkt, unsigned int pktCount); 3179243SN/A 3189243SN/A /** 3199243SN/A * Decode the incoming pkt, create a dram_pkt and push to the 3209243SN/A * back of the write queue. \If the write q length is more than 3219243SN/A * the threshold specified by the user, ie the queue is beginning 3229243SN/A * to get full, stop reads, and start draining writes. 3239243SN/A * 3249243SN/A * @param pkt The request packet from the outside world 3259831SN/A * @param pktCount The number of DRAM bursts the pkt 3269831SN/A * translate to. If pkt size is larger then one full burst, 3279831SN/A * then pktCount is greater than one. 3289243SN/A */ 3299831SN/A void addToWriteQueue(PacketPtr pkt, unsigned int pktCount); 3309243SN/A 3319243SN/A /** 3329243SN/A * Actually do the DRAM access - figure out the latency it 3339243SN/A * will take to service the req based on bank state, channel state etc 3349243SN/A * and then update those states to account for this request.\ Based 3359243SN/A * on this, update the packet's "readyTime" and move it to the 3369243SN/A * response q from where it will eventually go back to the outside 3379243SN/A * world. 3389243SN/A * 3399243SN/A * @param pkt The DRAM packet created from the outside world pkt 3409243SN/A */ 3419243SN/A void doDRAMAccess(DRAMPacket* dram_pkt); 3429243SN/A 3439243SN/A /** 3449243SN/A * When a packet reaches its "readyTime" in the response Q, 3459243SN/A * use the "access()" method in AbstractMemory to actually 3469243SN/A * create the response packet, and send it back to the outside 3479243SN/A * world requestor. 3489243SN/A * 3499243SN/A * @param pkt The packet from the outside world 3509726SN/A * @param static_latency Static latency to add before sending the packet 3519243SN/A */ 3529726SN/A void accessAndRespond(PacketPtr pkt, Tick static_latency); 3539243SN/A 3549243SN/A /** 3559243SN/A * Address decoder to figure out physical mapping onto ranks, 3569831SN/A * banks, and rows. This function is called multiple times on the same 3579831SN/A * system packet if the pakcet is larger than burst of the memory. The 3589831SN/A * dramPktAddr is used for the offset within the packet. 3599243SN/A * 3609243SN/A * @param pkt The packet from the outside world 3619831SN/A * @param dramPktAddr The starting address of the DRAM packet 3629831SN/A * @param size The size of the DRAM packet in bytes 3639966SN/A * @param isRead Is the request for a read or a write to DRAM 3649243SN/A * @return A DRAMPacket pointer with the decoded information 3659243SN/A */ 36610143SN/A DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, 36710143SN/A bool isRead); 3689243SN/A 3699243SN/A /** 37010206Sandreas.hansson@arm.com * The memory schduler/arbiter - picks which request needs to 3719567SN/A * go next, based on the specified policy such as FCFS or FR-FCFS 37210206Sandreas.hansson@arm.com * and moves it to the head of the queue. 37310393Swendy.elsasser@arm.com * Prioritizes accesses to the same rank as previous burst unless 37410393Swendy.elsasser@arm.com * controller is switching command type. 37510393Swendy.elsasser@arm.com * 37610393Swendy.elsasser@arm.com * @param queue Queued requests to consider 37710393Swendy.elsasser@arm.com * @param switched_cmd_type Command type is changing 3789243SN/A */ 37910393Swendy.elsasser@arm.com void chooseNext(std::deque<DRAMPacket*>& queue, bool switched_cmd_type); 3809243SN/A 3819243SN/A /** 3829974SN/A * For FR-FCFS policy reorder the read/write queue depending on row buffer 3839974SN/A * hits and earliest banks available in DRAM 38410393Swendy.elsasser@arm.com * Prioritizes accesses to the same rank as previous burst unless 38510393Swendy.elsasser@arm.com * controller is switching command type. 38610393Swendy.elsasser@arm.com * 38710393Swendy.elsasser@arm.com * @param queue Queued requests to consider 38810393Swendy.elsasser@arm.com * @param switched_cmd_type Command type is changing 3899974SN/A */ 39010393Swendy.elsasser@arm.com void reorderQueue(std::deque<DRAMPacket*>& queue, bool switched_cmd_type); 3919974SN/A 3929974SN/A /** 39310211Sandreas.hansson@arm.com * Find which are the earliest banks ready to issue an activate 39410211Sandreas.hansson@arm.com * for the enqueued requests. Assumes maximum of 64 banks per DIMM 39510393Swendy.elsasser@arm.com * Also checks if the bank is already prepped. 3969967SN/A * 39710393Swendy.elsasser@arm.com * @param queue Queued requests to consider 39810393Swendy.elsasser@arm.com * @param switched_cmd_type Command type is changing 3999967SN/A * @return One-hot encoded mask of bank indices 4009967SN/A */ 40110393Swendy.elsasser@arm.com uint64_t minBankPrep(const std::deque<DRAMPacket*>& queue, 40210393Swendy.elsasser@arm.com bool switched_cmd_type) const; 4039488SN/A 4049488SN/A /** 4059488SN/A * Keep track of when row activations happen, in order to enforce 4069488SN/A * the maximum number of activations in the activation window. The 4079488SN/A * method updates the time that the banks become available based 4089488SN/A * on the current limits. 40910210Sandreas.hansson@arm.com * 41010246Sandreas.hansson@arm.com * @param bank Reference to the bank 41110210Sandreas.hansson@arm.com * @param act_tick Time when the activation takes place 41210210Sandreas.hansson@arm.com * @param row Index of the row 4139488SN/A */ 41410246Sandreas.hansson@arm.com void activateBank(Bank& bank, Tick act_tick, uint32_t row); 41510207Sandreas.hansson@arm.com 41610207Sandreas.hansson@arm.com /** 41710207Sandreas.hansson@arm.com * Precharge a given bank and also update when the precharge is 41810207Sandreas.hansson@arm.com * done. This will also deal with any stats related to the 41910207Sandreas.hansson@arm.com * accesses to the open page. 42010207Sandreas.hansson@arm.com * 42110247Sandreas.hansson@arm.com * @param bank_ref The bank to precharge 42210211Sandreas.hansson@arm.com * @param pre_at Time when the precharge takes place 42310247Sandreas.hansson@arm.com * @param trace Is this an auto precharge then do not add to trace 42410207Sandreas.hansson@arm.com */ 42510247Sandreas.hansson@arm.com void prechargeBank(Bank& bank_ref, Tick pre_at, bool trace = true); 4269488SN/A 42710143SN/A /** 42810143SN/A * Used for debugging to observe the contents of the queues. 42910143SN/A */ 4309243SN/A void printQs() const; 4319243SN/A 4329243SN/A /** 4339243SN/A * The controller's main read and write queues 4349243SN/A */ 4359833SN/A std::deque<DRAMPacket*> readQueue; 4369833SN/A std::deque<DRAMPacket*> writeQueue; 4379243SN/A 4389243SN/A /** 4399243SN/A * Response queue where read packets wait after we're done working 4409567SN/A * with them, but it's not time to send the response yet. The 4419567SN/A * responses are stored seperately mostly to keep the code clean 4429567SN/A * and help with events scheduling. For all logical purposes such 4439567SN/A * as sizing the read queue, this and the main read queue need to 4449567SN/A * be added together. 4459243SN/A */ 4469833SN/A std::deque<DRAMPacket*> respQueue; 4479243SN/A 4489567SN/A /** 4499567SN/A * If we need to drain, keep the drain manager around until we're 4509567SN/A * done here. 4519243SN/A */ 4529342SN/A DrainManager *drainManager; 4539243SN/A 4549243SN/A /** 4559243SN/A * Multi-dimensional vector of banks, first dimension is ranks, 4569243SN/A * second is bank 4579243SN/A */ 4589243SN/A std::vector<std::vector<Bank> > banks; 4599243SN/A 4609243SN/A /** 4619243SN/A * The following are basic design parameters of the memory 4629831SN/A * controller, and are initialized based on parameter values. 4639831SN/A * The rowsPerBank is determined based on the capacity, number of 4649831SN/A * ranks and banks, the burst size, and the row buffer size. 4659243SN/A */ 46610489SOmar.Naji@arm.com const uint32_t deviceSize; 4679831SN/A const uint32_t deviceBusWidth; 4689831SN/A const uint32_t burstLength; 4699831SN/A const uint32_t deviceRowBufferSize; 4709831SN/A const uint32_t devicesPerRank; 4719831SN/A const uint32_t burstSize; 4729831SN/A const uint32_t rowBufferSize; 47310140SN/A const uint32_t columnsPerRowBuffer; 47410286Sandreas.hansson@arm.com const uint32_t columnsPerStripe; 4759243SN/A const uint32_t ranksPerChannel; 47610394Swendy.elsasser@arm.com const uint32_t bankGroupsPerRank; 47710394Swendy.elsasser@arm.com const bool bankGroupArch; 4789243SN/A const uint32_t banksPerRank; 4799566SN/A const uint32_t channels; 4809243SN/A uint32_t rowsPerBank; 4819243SN/A const uint32_t readBufferSize; 4829243SN/A const uint32_t writeBufferSize; 48310140SN/A const uint32_t writeHighThreshold; 48410140SN/A const uint32_t writeLowThreshold; 48510140SN/A const uint32_t minWritesPerSwitch; 48610140SN/A uint32_t writesThisTime; 48710147Sandreas.hansson@arm.com uint32_t readsThisTime; 4889243SN/A 4899243SN/A /** 4909243SN/A * Basic memory timing parameters initialized based on parameter 4919243SN/A * values. 4929243SN/A */ 49310286Sandreas.hansson@arm.com const Tick M5_CLASS_VAR_USED tCK; 4949243SN/A const Tick tWTR; 49510206Sandreas.hansson@arm.com const Tick tRTW; 49610393Swendy.elsasser@arm.com const Tick tCS; 4979243SN/A const Tick tBURST; 49810394Swendy.elsasser@arm.com const Tick tCCD_L; 4999243SN/A const Tick tRCD; 5009243SN/A const Tick tCL; 5019243SN/A const Tick tRP; 5029963SN/A const Tick tRAS; 50310210Sandreas.hansson@arm.com const Tick tWR; 50410212Sandreas.hansson@arm.com const Tick tRTP; 5059243SN/A const Tick tRFC; 5069243SN/A const Tick tREFI; 5079971SN/A const Tick tRRD; 50810394Swendy.elsasser@arm.com const Tick tRRD_L; 5099488SN/A const Tick tXAW; 5109488SN/A const uint32_t activationLimit; 5119243SN/A 5129243SN/A /** 5139243SN/A * Memory controller configuration initialized based on parameter 5149243SN/A * values. 5159243SN/A */ 5169243SN/A Enums::MemSched memSchedPolicy; 5179243SN/A Enums::AddrMap addrMapping; 5189243SN/A Enums::PageManage pageMgmt; 5199243SN/A 5209243SN/A /** 52110141SN/A * Max column accesses (read and write) per row, before forefully 52210141SN/A * closing it. 52310141SN/A */ 52410141SN/A const uint32_t maxAccessesPerRow; 52510141SN/A 52610141SN/A /** 5279726SN/A * Pipeline latency of the controller frontend. The frontend 5289726SN/A * contribution is added to writes (that complete when they are in 5299726SN/A * the write buffer) and reads that are serviced the write buffer. 5309726SN/A */ 5319726SN/A const Tick frontendLatency; 5329726SN/A 5339726SN/A /** 5349726SN/A * Pipeline latency of the backend and PHY. Along with the 5359726SN/A * frontend contribution, this latency is added to reads serviced 5369726SN/A * by the DRAM. 5379726SN/A */ 5389726SN/A const Tick backendLatency; 5399726SN/A 5409726SN/A /** 5419243SN/A * Till when has the main data bus been spoken for already? 5429243SN/A */ 5439243SN/A Tick busBusyUntil; 5449243SN/A 54510207Sandreas.hansson@arm.com /** 54610207Sandreas.hansson@arm.com * Keep track of when a refresh is due. 54710207Sandreas.hansson@arm.com */ 54810207Sandreas.hansson@arm.com Tick refreshDueAt; 54910207Sandreas.hansson@arm.com 55010207Sandreas.hansson@arm.com /** 55110207Sandreas.hansson@arm.com * The refresh state is used to control the progress of the 55210207Sandreas.hansson@arm.com * refresh scheduling. When normal operation is in progress the 55310207Sandreas.hansson@arm.com * refresh state is idle. From there, it progresses to the refresh 55410207Sandreas.hansson@arm.com * drain state once tREFI has passed. The refresh drain state 55510207Sandreas.hansson@arm.com * captures the DRAM row active state, as it will stay there until 55610207Sandreas.hansson@arm.com * all ongoing accesses complete. Thereafter all banks are 55710207Sandreas.hansson@arm.com * precharged, and lastly, the DRAM is refreshed. 55810207Sandreas.hansson@arm.com */ 55910207Sandreas.hansson@arm.com enum RefreshState { 56010207Sandreas.hansson@arm.com REF_IDLE = 0, 56110207Sandreas.hansson@arm.com REF_DRAIN, 56210207Sandreas.hansson@arm.com REF_PRE, 56310207Sandreas.hansson@arm.com REF_RUN 56410207Sandreas.hansson@arm.com }; 56510207Sandreas.hansson@arm.com 56610207Sandreas.hansson@arm.com RefreshState refreshState; 56710207Sandreas.hansson@arm.com 56810208Sandreas.hansson@arm.com /** 56910208Sandreas.hansson@arm.com * The power state captures the different operational states of 57010208Sandreas.hansson@arm.com * the DRAM and interacts with the bus read/write state machine, 57110208Sandreas.hansson@arm.com * and the refresh state machine. In the idle state all banks are 57210208Sandreas.hansson@arm.com * precharged. From there we either go to an auto refresh (as 57310208Sandreas.hansson@arm.com * determined by the refresh state machine), or to a precharge 57410208Sandreas.hansson@arm.com * power down mode. From idle the memory can also go to the active 57510208Sandreas.hansson@arm.com * state (with one or more banks active), and in turn from there 57610208Sandreas.hansson@arm.com * to active power down. At the moment we do not capture the deep 57710208Sandreas.hansson@arm.com * power down and self-refresh state. 57810208Sandreas.hansson@arm.com */ 57910208Sandreas.hansson@arm.com enum PowerState { 58010208Sandreas.hansson@arm.com PWR_IDLE = 0, 58110208Sandreas.hansson@arm.com PWR_REF, 58210208Sandreas.hansson@arm.com PWR_PRE_PDN, 58310208Sandreas.hansson@arm.com PWR_ACT, 58410208Sandreas.hansson@arm.com PWR_ACT_PDN 58510208Sandreas.hansson@arm.com }; 58610208Sandreas.hansson@arm.com 58710208Sandreas.hansson@arm.com /** 58810208Sandreas.hansson@arm.com * Since we are taking decisions out of order, we need to keep 58910208Sandreas.hansson@arm.com * track of what power transition is happening at what time, such 59010208Sandreas.hansson@arm.com * that we can go back in time and change history. For example, if 59110208Sandreas.hansson@arm.com * we precharge all banks and schedule going to the idle state, we 59210208Sandreas.hansson@arm.com * might at a later point decide to activate a bank before the 59310208Sandreas.hansson@arm.com * transition to idle would have taken place. 59410208Sandreas.hansson@arm.com */ 59510208Sandreas.hansson@arm.com PowerState pwrStateTrans; 59610208Sandreas.hansson@arm.com 59710208Sandreas.hansson@arm.com /** 59810208Sandreas.hansson@arm.com * Current power state. 59910208Sandreas.hansson@arm.com */ 60010208Sandreas.hansson@arm.com PowerState pwrState; 60110208Sandreas.hansson@arm.com 60210208Sandreas.hansson@arm.com /** 60310208Sandreas.hansson@arm.com * Schedule a power state transition in the future, and 60410208Sandreas.hansson@arm.com * potentially override an already scheduled transition. 60510208Sandreas.hansson@arm.com * 60610208Sandreas.hansson@arm.com * @param pwr_state Power state to transition to 60710208Sandreas.hansson@arm.com * @param tick Tick when transition should take place 60810208Sandreas.hansson@arm.com */ 60910208Sandreas.hansson@arm.com void schedulePowerEvent(PowerState pwr_state, Tick tick); 61010208Sandreas.hansson@arm.com 6119243SN/A Tick prevArrival; 6129243SN/A 61310206Sandreas.hansson@arm.com /** 61410206Sandreas.hansson@arm.com * The soonest you have to start thinking about the next request 61510206Sandreas.hansson@arm.com * is the longest access time that can occur before 61610206Sandreas.hansson@arm.com * busBusyUntil. Assuming you need to precharge, open a new row, 61710206Sandreas.hansson@arm.com * and access, it is tRP + tRCD + tCL. 61810206Sandreas.hansson@arm.com */ 61910206Sandreas.hansson@arm.com Tick nextReqTime; 6209972SN/A 6219243SN/A // All statistics that the model needs to capture 6229243SN/A Stats::Scalar readReqs; 6239243SN/A Stats::Scalar writeReqs; 6249831SN/A Stats::Scalar readBursts; 6259831SN/A Stats::Scalar writeBursts; 6269975SN/A Stats::Scalar bytesReadDRAM; 6279975SN/A Stats::Scalar bytesReadWrQ; 6289243SN/A Stats::Scalar bytesWritten; 6299977SN/A Stats::Scalar bytesReadSys; 6309977SN/A Stats::Scalar bytesWrittenSys; 6319243SN/A Stats::Scalar servicedByWrQ; 6329977SN/A Stats::Scalar mergedWrBursts; 6339243SN/A Stats::Scalar neitherReadNorWrite; 6349977SN/A Stats::Vector perBankRdBursts; 6359977SN/A Stats::Vector perBankWrBursts; 6369243SN/A Stats::Scalar numRdRetry; 6379243SN/A Stats::Scalar numWrRetry; 6389243SN/A Stats::Scalar totGap; 6399243SN/A Stats::Vector readPktSize; 6409243SN/A Stats::Vector writePktSize; 6419243SN/A Stats::Vector rdQLenPdf; 6429243SN/A Stats::Vector wrQLenPdf; 6439727SN/A Stats::Histogram bytesPerActivate; 64410147Sandreas.hansson@arm.com Stats::Histogram rdPerTurnAround; 64510147Sandreas.hansson@arm.com Stats::Histogram wrPerTurnAround; 6469243SN/A 6479243SN/A // Latencies summed over all requests 6489243SN/A Stats::Scalar totQLat; 6499243SN/A Stats::Scalar totMemAccLat; 6509243SN/A Stats::Scalar totBusLat; 6519243SN/A 6529243SN/A // Average latencies per request 6539243SN/A Stats::Formula avgQLat; 6549243SN/A Stats::Formula avgBusLat; 6559243SN/A Stats::Formula avgMemAccLat; 6569243SN/A 6579243SN/A // Average bandwidth 6589243SN/A Stats::Formula avgRdBW; 6599243SN/A Stats::Formula avgWrBW; 6609977SN/A Stats::Formula avgRdBWSys; 6619977SN/A Stats::Formula avgWrBWSys; 6629243SN/A Stats::Formula peakBW; 6639243SN/A Stats::Formula busUtil; 6649975SN/A Stats::Formula busUtilRead; 6659975SN/A Stats::Formula busUtilWrite; 6669243SN/A 6679243SN/A // Average queue lengths 6689243SN/A Stats::Average avgRdQLen; 6699243SN/A Stats::Average avgWrQLen; 6709243SN/A 6719243SN/A // Row hit count and rate 6729243SN/A Stats::Scalar readRowHits; 6739243SN/A Stats::Scalar writeRowHits; 6749243SN/A Stats::Formula readRowHitRate; 6759243SN/A Stats::Formula writeRowHitRate; 6769243SN/A Stats::Formula avgGap; 6779243SN/A 6789975SN/A // DRAM Power Calculation 6799975SN/A Stats::Formula pageHitRate; 68010208Sandreas.hansson@arm.com Stats::Vector pwrStateTime; 6819975SN/A 68210432SOmar.Naji@arm.com //Command energies 68310432SOmar.Naji@arm.com Stats::Vector actEnergy; 68410432SOmar.Naji@arm.com Stats::Vector preEnergy; 68510432SOmar.Naji@arm.com Stats::Vector readEnergy; 68610432SOmar.Naji@arm.com Stats::Vector writeEnergy; 68710432SOmar.Naji@arm.com Stats::Vector refreshEnergy; 68810432SOmar.Naji@arm.com //Active Background Energy 68910432SOmar.Naji@arm.com Stats::Vector actBackEnergy; 69010432SOmar.Naji@arm.com //Precharge Background Energy 69110432SOmar.Naji@arm.com Stats::Vector preBackEnergy; 69210432SOmar.Naji@arm.com Stats::Vector totalEnergy; 69310432SOmar.Naji@arm.com //Power Consumed 69410432SOmar.Naji@arm.com Stats::Vector averagePower; 69510432SOmar.Naji@arm.com 69610208Sandreas.hansson@arm.com // Track when we transitioned to the current power state 69710208Sandreas.hansson@arm.com Tick pwrStateTick; 69810207Sandreas.hansson@arm.com 6999975SN/A // To track number of banks which are currently active 7009975SN/A unsigned int numBanksActive; 7019975SN/A 70210393Swendy.elsasser@arm.com // Holds the value of the rank of burst issued 70310393Swendy.elsasser@arm.com uint8_t activeRank; 70410393Swendy.elsasser@arm.com 70510432SOmar.Naji@arm.com // timestamp offset 70610432SOmar.Naji@arm.com uint64_t timeStampOffset; 70710432SOmar.Naji@arm.com 7089349SN/A /** @todo this is a temporary workaround until the 4-phase code is 7099349SN/A * committed. upstream caches needs this packet until true is returned, so 7109349SN/A * hold onto it for deletion until a subsequent call 7119349SN/A */ 7129349SN/A std::vector<PacketPtr> pendingDelete; 7139349SN/A 71410432SOmar.Naji@arm.com // One DRAMPower instance per rank 71510432SOmar.Naji@arm.com std::vector<DRAMPower> rankPower; 71610432SOmar.Naji@arm.com 71710432SOmar.Naji@arm.com /** 71810432SOmar.Naji@arm.com * This function increments the energy when called. If stats are 71910432SOmar.Naji@arm.com * dumped periodically, note accumulated energy values will 72010432SOmar.Naji@arm.com * appear in the stats (even if the stats are reset). This is a 72110432SOmar.Naji@arm.com * result of the energy values coming from DRAMPower, and there 72210432SOmar.Naji@arm.com * is currently no support for resetting the state. 72310432SOmar.Naji@arm.com * 72410432SOmar.Naji@arm.com * @param rank Currrent rank 72510432SOmar.Naji@arm.com */ 72610432SOmar.Naji@arm.com void updatePowerStats(uint8_t rank); 72710432SOmar.Naji@arm.com 72810432SOmar.Naji@arm.com /** 72910432SOmar.Naji@arm.com * Function for sorting commands in the command list of DRAMPower. 73010432SOmar.Naji@arm.com * 73110432SOmar.Naji@arm.com * @param a Memory Command in command list of DRAMPower library 73210432SOmar.Naji@arm.com * @param next Memory Command in command list of DRAMPower 73310432SOmar.Naji@arm.com * @return true if timestamp of Command 1 < timestamp of Command 2 73410432SOmar.Naji@arm.com */ 73510432SOmar.Naji@arm.com static bool sortTime(const Data::MemCommand& m1, 73610432SOmar.Naji@arm.com const Data::MemCommand& m2) { 73710432SOmar.Naji@arm.com return m1.getTime() < m2.getTime(); 73810432SOmar.Naji@arm.com }; 73910432SOmar.Naji@arm.com 74010432SOmar.Naji@arm.com 7419243SN/A public: 7429243SN/A 7439243SN/A void regStats(); 7449243SN/A 74510146Sandreas.hansson@arm.com DRAMCtrl(const DRAMCtrlParams* p); 7469243SN/A 7479342SN/A unsigned int drain(DrainManager* dm); 7489243SN/A 7499294SN/A virtual BaseSlavePort& getSlavePort(const std::string& if_name, 7509294SN/A PortID idx = InvalidPortID); 7519243SN/A 7529243SN/A virtual void init(); 7539243SN/A virtual void startup(); 7549243SN/A 7559243SN/A protected: 7569243SN/A 7579243SN/A Tick recvAtomic(PacketPtr pkt); 7589243SN/A void recvFunctional(PacketPtr pkt); 7599243SN/A bool recvTimingReq(PacketPtr pkt); 7609243SN/A 7619243SN/A}; 7629243SN/A 76310146Sandreas.hansson@arm.com#endif //__MEM_DRAM_CTRL_HH__ 764