coherent_xbar.cc revision 2548
17404SAli.Saidi@ARM.com/* 211574SCurtis.Dunham@arm.com * Copyright (c) 2006 The Regents of The University of Michigan 37404SAli.Saidi@ARM.com * All rights reserved. 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 147404SAli.Saidi@ARM.com * this software without specific prior written permission. 157404SAli.Saidi@ARM.com * 167404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277404SAli.Saidi@ARM.com */ 287404SAli.Saidi@ARM.com 297404SAli.Saidi@ARM.com/** 307404SAli.Saidi@ARM.com * @file Definition of a bus object. 317404SAli.Saidi@ARM.com */ 327404SAli.Saidi@ARM.com 337404SAli.Saidi@ARM.com 347404SAli.Saidi@ARM.com#include "base/trace.hh" 357404SAli.Saidi@ARM.com#include "mem/bus.hh" 367404SAli.Saidi@ARM.com#include "sim/builder.hh" 377404SAli.Saidi@ARM.com 3810037SARM gem5 Developers/** Function called by the port when the bus is recieving a Timing 397404SAli.Saidi@ARM.com * transaction.*/ 4010873Sandreas.sandberg@arm.combool 417404SAli.Saidi@ARM.comBus::recvTiming(Packet &pkt, int id) 4210474Sandreas.hansson@arm.com{ 4310474Sandreas.hansson@arm.com 447404SAli.Saidi@ARM.com panic("I need to be implemented, but not right now."); 4510037SARM gem5 Developers} 4610037SARM gem5 Developers 477404SAli.Saidi@ARM.comPort * 487728SAli.Saidi@ARM.comBus::findPort(Addr addr, int id) 497404SAli.Saidi@ARM.com{ 508245Snate@binkert.org /* An interval tree would be a better way to do this. --ali. */ 519152Satgutier@umich.edu int dest_id = -1; 528245Snate@binkert.org int i = 0; 538245Snate@binkert.org bool found = false; 5410873Sandreas.sandberg@arm.com 557748SAli.Saidi@ARM.com while (i < portList.size() && !found) 567404SAli.Saidi@ARM.com { 577404SAli.Saidi@ARM.com if (portList[i].range == addr) { 587404SAli.Saidi@ARM.com dest_id = portList[i].portId; 597404SAli.Saidi@ARM.com found = true; 6010913Sandreas.sandberg@arm.com } 6110717Sandreas.hansson@arm.com i++; 6210717Sandreas.hansson@arm.com } 6310717Sandreas.hansson@arm.com if (dest_id == -1) 649258SAli.Saidi@ARM.com panic("Unable to find destination for addr: %llx", addr); 6510621SCurtis.Dunham@arm.com 6610621SCurtis.Dunham@arm.com // we shouldn't be sending this back to where it came from 6710037SARM gem5 Developers assert(dest_id != id); 6810037SARM gem5 Developers 6910037SARM gem5 Developers return interfaces[dest_id]; 7010037SARM gem5 Developers} 717439Sdam.sunwoo@arm.com 727576SAli.Saidi@ARM.com/** Function called by the port when the bus is recieving a Atomic 7310037SARM gem5 Developers * transaction.*/ 7410037SARM gem5 DevelopersTick 7510037SARM gem5 DevelopersBus::recvAtomic(Packet &pkt, int id) 7610717Sandreas.hansson@arm.com{ 7710037SARM gem5 Developers return findPort(pkt.addr, id)->sendAtomic(pkt); 7810037SARM gem5 Developers} 7910037SARM gem5 Developers 8010037SARM gem5 Developers/** Function called by the port when the bus is recieving a Functional 8110037SARM gem5 Developers * transaction.*/ 8210037SARM gem5 Developersvoid 8310037SARM gem5 DevelopersBus::recvFunctional(Packet &pkt, int id) 8410037SARM gem5 Developers{ 8510037SARM gem5 Developers findPort(pkt.addr, id)->sendFunctional(pkt); 8610037SARM gem5 Developers} 8710037SARM gem5 Developers 8810037SARM gem5 Developers/** Function called by the port when the bus is recieving a status change.*/ 897439Sdam.sunwoo@arm.comvoid 907404SAli.Saidi@ARM.comBus::recvStatusChange(Port::Status status, int id) 917404SAli.Saidi@ARM.com{ 927404SAli.Saidi@ARM.com assert(status == Port::RangeChange && 937404SAli.Saidi@ARM.com "The other statuses need to be implemented."); 947404SAli.Saidi@ARM.com 957404SAli.Saidi@ARM.com assert(id < interfaces.size() && id >= 0); 9610717Sandreas.hansson@arm.com Port *port = interfaces[id]; 9710717Sandreas.hansson@arm.com AddrRangeList ranges; 9810717Sandreas.hansson@arm.com AddrRangeList snoops; 9910717Sandreas.hansson@arm.com 10010717Sandreas.hansson@arm.com port->getPeerAddressRanges(ranges, snoops); 10110717Sandreas.hansson@arm.com 10210717Sandreas.hansson@arm.com // not dealing with snooping yet either 10310717Sandreas.hansson@arm.com assert(snoops.size() == 0); 10410717Sandreas.hansson@arm.com // or multiple ranges 10510717Sandreas.hansson@arm.com assert(ranges.size() == 1); 10610717Sandreas.hansson@arm.com 10710717Sandreas.hansson@arm.com DevMap dm; 10810717Sandreas.hansson@arm.com dm.portId = id; 10910717Sandreas.hansson@arm.com dm.range = ranges.front(); 11010717Sandreas.hansson@arm.com 11110717Sandreas.hansson@arm.com DPRINTF(MMU, "Adding range %llx - %llx for id %d\n", dm.range.start, 11210717Sandreas.hansson@arm.com dm.range.end, id); 11310717Sandreas.hansson@arm.com portList.push_back(dm); 11410717Sandreas.hansson@arm.com DPRINTF(MMU, "port list has %d entries\n", portList.size()); 11510717Sandreas.hansson@arm.com} 11610717Sandreas.hansson@arm.com 11710717Sandreas.hansson@arm.comvoid 11810717Sandreas.hansson@arm.comBus::BusPort::addressRanges(AddrRangeList &resp, AddrRangeList &snoop) 11910717Sandreas.hansson@arm.com{ 12010717Sandreas.hansson@arm.com panic("I'm not implemented.\n"); 12110717Sandreas.hansson@arm.com} 12210717Sandreas.hansson@arm.com 12310717Sandreas.hansson@arm.comBEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus) 12410717Sandreas.hansson@arm.com 12510537Sandreas.hansson@arm.com Param<int> bus_id; 12610537Sandreas.hansson@arm.com 12710537Sandreas.hansson@arm.comEND_DECLARE_SIM_OBJECT_PARAMS(Bus) 12810537Sandreas.hansson@arm.com 12910537Sandreas.hansson@arm.comBEGIN_INIT_SIM_OBJECT_PARAMS(Bus) 13010537Sandreas.hansson@arm.com INIT_PARAM(bus_id, "junk bus id") 13110537Sandreas.hansson@arm.comEND_INIT_SIM_OBJECT_PARAMS(PhysicalMemory) 13210537Sandreas.hansson@arm.com 13310537Sandreas.hansson@arm.comCREATE_SIM_OBJECT(Bus) 13410037SARM gem5 Developers{ 13510037SARM gem5 Developers return new Bus(getInstanceName()); 13610037SARM gem5 Developers} 1379152Satgutier@umich.edu 1389152Satgutier@umich.eduREGISTER_SIM_OBJECT("Bus", Bus) 1399152Satgutier@umich.edu