write_queue_entry.hh revision 13861
12810SN/A/* 212728Snikos.nikoleris@arm.com * Copyright (c) 2012-2013, 2015-2016 ARM Limited 39347SAndreas.Sandberg@arm.com * All rights reserved. 49347SAndreas.Sandberg@arm.com * 59347SAndreas.Sandberg@arm.com * The license below extends only to copyright in the software and shall 69347SAndreas.Sandberg@arm.com * not be construed as granting a license to any other intellectual 79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating 89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software 99347SAndreas.Sandberg@arm.com * licensed hereunder. You may use the software subject to the license 109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated 119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form. 139347SAndreas.Sandberg@arm.com * 142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 412810SN/A * Andreas Hansson 422810SN/A */ 432810SN/A 442810SN/A/** 452810SN/A * @file 462810SN/A * Write queue entry 472810SN/A */ 482810SN/A 4912492Sodanrc@yahoo.com.br#ifndef __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__ 5012492Sodanrc@yahoo.com.br#define __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__ 512810SN/A 5212727Snikos.nikoleris@arm.com#include <cassert> 5312728Snikos.nikoleris@arm.com#include <iosfwd> 542810SN/A#include <list> 558229Snate@binkert.org#include <string> 568229Snate@binkert.org 5712727Snikos.nikoleris@arm.com#include "base/printable.hh" 582810SN/A#include "base/types.hh" 5912727Snikos.nikoleris@arm.com#include "mem/cache/queue_entry.hh" 6010815Sdavid.guillen@arm.com#include "mem/packet.hh" 6112727Snikos.nikoleris@arm.com#include "sim/core.hh" 629796Sprakash.ramrakhyani@arm.com 639796Sprakash.ramrakhyani@arm.comclass BaseCache; 642810SN/A 652810SN/A/** 662810SN/A * Write queue entry 672810SN/A */ 682810SN/Aclass WriteQueueEntry : public QueueEntry, public Printable 692810SN/A{ 709796Sprakash.ramrakhyani@arm.com 712810SN/A /** 722810SN/A * Consider the queues friends to avoid making everything public. 739796Sprakash.ramrakhyani@arm.com */ 749796Sprakash.ramrakhyani@arm.com template<typename Entry> 7511893Snikos.nikoleris@arm.com friend class Queue; 7611893Snikos.nikoleris@arm.com friend class WriteQueue; 779796Sprakash.ramrakhyani@arm.com 789796Sprakash.ramrakhyani@arm.com public: 7911722Ssophiane.senni@gmail.com class TargetList : public std::list<Target> { 8011722Ssophiane.senni@gmail.com 8111722Ssophiane.senni@gmail.com public: 8211722Ssophiane.senni@gmail.com 8311722Ssophiane.senni@gmail.com TargetList() {} 8411722Ssophiane.senni@gmail.com void add(PacketPtr pkt, Tick readyTime, Counter order); 8511722Ssophiane.senni@gmail.com bool trySatisfyFunctional(PacketPtr pkt); 8610693SMarco.Balboni@ARM.com void print(std::ostream &os, int verbosity, 872810SN/A const std::string &prefix) const; 882810SN/A }; 892810SN/A 902810SN/A /** A list of write queue entriess. */ 912810SN/A typedef std::list<WriteQueueEntry *> List; 922810SN/A /** WriteQueueEntry list iterator. */ 932810SN/A typedef List::iterator Iterator; 9412513Sodanrc@yahoo.com.br 952810SN/A bool sendPacket(BaseCache &cache); 962810SN/A 972810SN/A private: 986978SLisa.Hsu@amd.com 9912553Snikos.nikoleris@arm.com /** 1006978SLisa.Hsu@amd.com * Pointer to this entry on the ready list. 10112629Sodanrc@yahoo.com.br * @sa MissQueue, WriteQueue::readyList 10212629Sodanrc@yahoo.com.br */ 10312629Sodanrc@yahoo.com.br Iterator readyIter; 1042810SN/A 1052810SN/A /** 10612513Sodanrc@yahoo.com.br * Pointer to this entry on the allocated list. 1072810SN/A * @sa MissQueue, WriteQueue::allocatedList 1082810SN/A */ 1092810SN/A Iterator allocIter; 1102810SN/A 1112810SN/A /** List of all requests that match the address */ 1125999Snate@binkert.org TargetList targets; 1132810SN/A 1142810SN/A public: 1155999Snate@binkert.org 1162810SN/A /** A simple constructor. */ 1172810SN/A WriteQueueEntry() {} 1182810SN/A 1192810SN/A /** 1202810SN/A * Allocate a miss to this entry. 1212810SN/A * @param blk_addr The address of the block. 1225999Snate@binkert.org * @param blk_size The number of bytes to request. 1232810SN/A * @param pkt The original write. 1242810SN/A * @param when_ready When should the write be sent out. 1252810SN/A * @param _order The logical order of this write. 1262810SN/A */ 1272810SN/A void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, 1282810SN/A Tick when_ready, Counter _order); 1292810SN/A 13012513Sodanrc@yahoo.com.br 1315999Snate@binkert.org /** 1326978SLisa.Hsu@amd.com * Mark this entry as free. 1338833Sdam.sunwoo@arm.com */ 1346978SLisa.Hsu@amd.com void deallocate(); 1356978SLisa.Hsu@amd.com 1368833Sdam.sunwoo@arm.com /** 1376978SLisa.Hsu@amd.com * Returns the current number of allocated targets. 1386978SLisa.Hsu@amd.com * @return The current number of allocated targets. 13910024Sdam.sunwoo@arm.com */ 14010024Sdam.sunwoo@arm.com int getNumTargets() const 14110024Sdam.sunwoo@arm.com { return targets.size(); } 14210024Sdam.sunwoo@arm.com 14310024Sdam.sunwoo@arm.com /** 14410024Sdam.sunwoo@arm.com * Returns true if there are targets left. 14510024Sdam.sunwoo@arm.com * @return true if there are targets 14610024Sdam.sunwoo@arm.com */ 14710024Sdam.sunwoo@arm.com bool hasTargets() const { return !targets.empty(); } 14810025Stimothy.jones@arm.com 14910025Stimothy.jones@arm.com /** 15010025Stimothy.jones@arm.com * Returns a reference to the first target. 15110025Stimothy.jones@arm.com * @return A pointer to the first target. 15210025Stimothy.jones@arm.com */ 1532810SN/A Target *getTarget() override 1542810SN/A { 1552810SN/A assert(hasTargets()); 1562810SN/A return &targets.front(); 1572810SN/A } 1589796Sprakash.ramrakhyani@arm.com 1599796Sprakash.ramrakhyani@arm.com /** 1602810SN/A * Pop first target. 1612810SN/A */ 1622810SN/A void popTarget() 1632810SN/A { 1642810SN/A targets.pop_front(); 1652810SN/A } 1662810SN/A 1679796Sprakash.ramrakhyani@arm.com bool trySatisfyFunctional(PacketPtr pkt); 1682810SN/A 1692810SN/A /** 1702810SN/A * Prints the contents of this MSHR for debugging. 1712810SN/A */ 1722810SN/A void print(std::ostream &os, 1739796Sprakash.ramrakhyani@arm.com int verbosity = 0, 1742810SN/A const std::string &prefix = "") const; 1759796Sprakash.ramrakhyani@arm.com /** 1762810SN/A * A no-args wrapper of print(std::ostream...) meant to be 1772810SN/A * invoked from DPRINTFs avoiding string overheads in fast mode 1782810SN/A * 1792810SN/A * @return string with mshr fields 1802810SN/A */ 18112728Snikos.nikoleris@arm.com std::string print() const; 1827612SGene.Wu@arm.com 1837612SGene.Wu@arm.com bool matchBlockAddr(const Addr addr, const bool is_secure) const override; 18410024Sdam.sunwoo@arm.com bool matchBlockAddr(const PacketPtr pkt) const override; 18510024Sdam.sunwoo@arm.com bool conflictAddr(const QueueEntry* entry) const override; 18612728Snikos.nikoleris@arm.com}; 18710024Sdam.sunwoo@arm.com 18810024Sdam.sunwoo@arm.com#endif // __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__ 1899663Suri.wiener@arm.com