write_queue_entry.hh revision 12724
111375Sandreas.hansson@arm.com/* 211375Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015-2016 ARM Limited 311375Sandreas.hansson@arm.com * All rights reserved. 411375Sandreas.hansson@arm.com * 511375Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611375Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711375Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811375Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911375Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011375Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111375Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211375Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311375Sandreas.hansson@arm.com * 1411375Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511375Sandreas.hansson@arm.com * All rights reserved. 1611375Sandreas.hansson@arm.com * 1711375Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 1811375Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 1911375Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 2011375Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 2111375Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 2211375Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 2311375Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 2411375Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 2511375Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 2611375Sandreas.hansson@arm.com * this software without specific prior written permission. 2711375Sandreas.hansson@arm.com * 2811375Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911375Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3011375Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111375Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211375Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311375Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411375Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3511375Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3611375Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3711375Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811375Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3911375Sandreas.hansson@arm.com * 4011375Sandreas.hansson@arm.com * Authors: Erik Hallnor 4111375Sandreas.hansson@arm.com * Andreas Hansson 4211375Sandreas.hansson@arm.com */ 4311375Sandreas.hansson@arm.com 4411375Sandreas.hansson@arm.com/** 4511375Sandreas.hansson@arm.com * @file 4611375Sandreas.hansson@arm.com * Write queue entry 4711375Sandreas.hansson@arm.com */ 4811375Sandreas.hansson@arm.com 4911375Sandreas.hansson@arm.com#ifndef __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__ 5011375Sandreas.hansson@arm.com#define __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__ 5111375Sandreas.hansson@arm.com 5211375Sandreas.hansson@arm.com#include <list> 5311375Sandreas.hansson@arm.com 5411375Sandreas.hansson@arm.com#include "base/printable.hh" 5511375Sandreas.hansson@arm.com#include "mem/cache/queue_entry.hh" 5611375Sandreas.hansson@arm.com 5712724Snikos.nikoleris@arm.comclass BaseCache; 5811375Sandreas.hansson@arm.com 5911375Sandreas.hansson@arm.com/** 6011375Sandreas.hansson@arm.com * Write queue entry 6111375Sandreas.hansson@arm.com */ 6211375Sandreas.hansson@arm.comclass WriteQueueEntry : public QueueEntry, public Printable 6311375Sandreas.hansson@arm.com{ 6411375Sandreas.hansson@arm.com 6511375Sandreas.hansson@arm.com /** 6611375Sandreas.hansson@arm.com * Consider the queues friends to avoid making everything public. 6711375Sandreas.hansson@arm.com */ 6811375Sandreas.hansson@arm.com template<typename Entry> 6911375Sandreas.hansson@arm.com friend class Queue; 7011375Sandreas.hansson@arm.com friend class WriteQueue; 7111375Sandreas.hansson@arm.com 7211375Sandreas.hansson@arm.com public: 7311375Sandreas.hansson@arm.com 7411375Sandreas.hansson@arm.com class Target { 7511375Sandreas.hansson@arm.com public: 7611375Sandreas.hansson@arm.com 7711375Sandreas.hansson@arm.com const Tick recvTime; //!< Time when request was received (for stats) 7811375Sandreas.hansson@arm.com const Tick readyTime; //!< Time when request is ready to be serviced 7911375Sandreas.hansson@arm.com const Counter order; //!< Global order (for memory consistency mgmt) 8011375Sandreas.hansson@arm.com const PacketPtr pkt; //!< Pending request packet. 8111375Sandreas.hansson@arm.com 8211375Sandreas.hansson@arm.com Target(PacketPtr _pkt, Tick _readyTime, Counter _order) 8311375Sandreas.hansson@arm.com : recvTime(curTick()), readyTime(_readyTime), order(_order), 8411375Sandreas.hansson@arm.com pkt(_pkt) 8511375Sandreas.hansson@arm.com {} 8611375Sandreas.hansson@arm.com }; 8711375Sandreas.hansson@arm.com 8811375Sandreas.hansson@arm.com class TargetList : public std::list<Target> { 8911375Sandreas.hansson@arm.com 9011375Sandreas.hansson@arm.com public: 9111375Sandreas.hansson@arm.com 9211375Sandreas.hansson@arm.com TargetList() {} 9311375Sandreas.hansson@arm.com void add(PacketPtr pkt, Tick readyTime, Counter order); 9411375Sandreas.hansson@arm.com bool checkFunctional(PacketPtr pkt); 9511375Sandreas.hansson@arm.com void print(std::ostream &os, int verbosity, 9611375Sandreas.hansson@arm.com const std::string &prefix) const; 9711375Sandreas.hansson@arm.com }; 9811375Sandreas.hansson@arm.com 9911375Sandreas.hansson@arm.com /** A list of write queue entriess. */ 10011375Sandreas.hansson@arm.com typedef std::list<WriteQueueEntry *> List; 10111375Sandreas.hansson@arm.com /** WriteQueueEntry list iterator. */ 10211375Sandreas.hansson@arm.com typedef List::iterator Iterator; 10311375Sandreas.hansson@arm.com 10412724Snikos.nikoleris@arm.com bool sendPacket(BaseCache &cache); 10511375Sandreas.hansson@arm.com 10611375Sandreas.hansson@arm.com private: 10711375Sandreas.hansson@arm.com 10811375Sandreas.hansson@arm.com /** 10911375Sandreas.hansson@arm.com * Pointer to this entry on the ready list. 11011375Sandreas.hansson@arm.com * @sa MissQueue, WriteQueue::readyList 11111375Sandreas.hansson@arm.com */ 11211375Sandreas.hansson@arm.com Iterator readyIter; 11311375Sandreas.hansson@arm.com 11411375Sandreas.hansson@arm.com /** 11511375Sandreas.hansson@arm.com * Pointer to this entry on the allocated list. 11611375Sandreas.hansson@arm.com * @sa MissQueue, WriteQueue::allocatedList 11711375Sandreas.hansson@arm.com */ 11811375Sandreas.hansson@arm.com Iterator allocIter; 11911375Sandreas.hansson@arm.com 12011375Sandreas.hansson@arm.com /** List of all requests that match the address */ 12111375Sandreas.hansson@arm.com TargetList targets; 12211375Sandreas.hansson@arm.com 12311375Sandreas.hansson@arm.com public: 12411375Sandreas.hansson@arm.com 12511375Sandreas.hansson@arm.com /** A simple constructor. */ 12611375Sandreas.hansson@arm.com WriteQueueEntry() {} 12711375Sandreas.hansson@arm.com 12811375Sandreas.hansson@arm.com /** 12911375Sandreas.hansson@arm.com * Allocate a miss to this entry. 13011375Sandreas.hansson@arm.com * @param blk_addr The address of the block. 13111375Sandreas.hansson@arm.com * @param blk_size The number of bytes to request. 13211375Sandreas.hansson@arm.com * @param pkt The original write. 13311375Sandreas.hansson@arm.com * @param when_ready When should the write be sent out. 13411375Sandreas.hansson@arm.com * @param _order The logical order of this write. 13511375Sandreas.hansson@arm.com */ 13611375Sandreas.hansson@arm.com void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, 13711375Sandreas.hansson@arm.com Tick when_ready, Counter _order); 13811375Sandreas.hansson@arm.com 13911375Sandreas.hansson@arm.com 14011375Sandreas.hansson@arm.com /** 14111375Sandreas.hansson@arm.com * Mark this entry as free. 14211375Sandreas.hansson@arm.com */ 14311375Sandreas.hansson@arm.com void deallocate(); 14411375Sandreas.hansson@arm.com 14511375Sandreas.hansson@arm.com /** 14611375Sandreas.hansson@arm.com * Returns the current number of allocated targets. 14711375Sandreas.hansson@arm.com * @return The current number of allocated targets. 14811375Sandreas.hansson@arm.com */ 14911375Sandreas.hansson@arm.com int getNumTargets() const 15011375Sandreas.hansson@arm.com { return targets.size(); } 15111375Sandreas.hansson@arm.com 15211375Sandreas.hansson@arm.com /** 15311375Sandreas.hansson@arm.com * Returns true if there are targets left. 15411375Sandreas.hansson@arm.com * @return true if there are targets 15511375Sandreas.hansson@arm.com */ 15611375Sandreas.hansson@arm.com bool hasTargets() const { return !targets.empty(); } 15711375Sandreas.hansson@arm.com 15811375Sandreas.hansson@arm.com /** 15911375Sandreas.hansson@arm.com * Returns a reference to the first target. 16011375Sandreas.hansson@arm.com * @return A pointer to the first target. 16111375Sandreas.hansson@arm.com */ 16211375Sandreas.hansson@arm.com Target *getTarget() 16311375Sandreas.hansson@arm.com { 16411375Sandreas.hansson@arm.com assert(hasTargets()); 16511375Sandreas.hansson@arm.com return &targets.front(); 16611375Sandreas.hansson@arm.com } 16711375Sandreas.hansson@arm.com 16811375Sandreas.hansson@arm.com /** 16911375Sandreas.hansson@arm.com * Pop first target. 17011375Sandreas.hansson@arm.com */ 17111375Sandreas.hansson@arm.com void popTarget() 17211375Sandreas.hansson@arm.com { 17311375Sandreas.hansson@arm.com targets.pop_front(); 17411375Sandreas.hansson@arm.com } 17511375Sandreas.hansson@arm.com 17611375Sandreas.hansson@arm.com bool checkFunctional(PacketPtr pkt); 17711375Sandreas.hansson@arm.com 17811375Sandreas.hansson@arm.com /** 17911375Sandreas.hansson@arm.com * Prints the contents of this MSHR for debugging. 18011375Sandreas.hansson@arm.com */ 18111375Sandreas.hansson@arm.com void print(std::ostream &os, 18211375Sandreas.hansson@arm.com int verbosity = 0, 18311375Sandreas.hansson@arm.com const std::string &prefix = "") const; 18411375Sandreas.hansson@arm.com /** 18511375Sandreas.hansson@arm.com * A no-args wrapper of print(std::ostream...) meant to be 18611375Sandreas.hansson@arm.com * invoked from DPRINTFs avoiding string overheads in fast mode 18711375Sandreas.hansson@arm.com * 18811375Sandreas.hansson@arm.com * @return string with mshr fields 18911375Sandreas.hansson@arm.com */ 19011375Sandreas.hansson@arm.com std::string print() const; 19111375Sandreas.hansson@arm.com}; 19211375Sandreas.hansson@arm.com 19311375Sandreas.hansson@arm.com#endif // __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__ 194