base_set_assoc.hh revision 11484:08b33c52a16d
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
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8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
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26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASESETASSOC_HH__
49#define __MEM_CACHE_TAGS_BASESETASSOC_HH__
50
51#include <cassert>
52#include <cstring>
53#include <list>
54
55#include "mem/cache/tags/base.hh"
56#include "mem/cache/tags/cacheset.hh"
57#include "mem/cache/base.hh"
58#include "mem/cache/blk.hh"
59#include "mem/packet.hh"
60#include "params/BaseSetAssoc.hh"
61
62/**
63 * A BaseSetAssoc cache tag store.
64 * @sa  \ref gem5MemorySystem "gem5 Memory System"
65 *
66 * The BaseSetAssoc tags provide a base, as well as the functionality
67 * common to any set associative tags. Any derived class must implement
68 * the methods related to the specifics of the actual replacment policy.
69 * These are:
70 *
71 * BlkType* accessBlock();
72 * BlkType* findVictim();
73 * void insertBlock();
74 * void invalidate();
75 */
76class BaseSetAssoc : public BaseTags
77{
78  public:
79    /** Typedef the block type used in this tag store. */
80    typedef CacheBlk BlkType;
81    /** Typedef for a list of pointers to the local block class. */
82    typedef std::list<BlkType*> BlkList;
83    /** Typedef the set type used in this tag store. */
84    typedef CacheSet<CacheBlk> SetType;
85
86
87  protected:
88    /** The associativity of the cache. */
89    const unsigned assoc;
90    /** The allocatable associativity of the cache (alloc mask). */
91    unsigned allocAssoc;
92    /** The number of sets in the cache. */
93    const unsigned numSets;
94    /** Whether tags and data are accessed sequentially. */
95    const bool sequentialAccess;
96
97    /** The cache sets. */
98    SetType *sets;
99
100    /** The cache blocks. */
101    BlkType *blks;
102    /** The data blocks, 1 per cache block. */
103    uint8_t *dataBlks;
104
105    /** The amount to shift the address to get the set. */
106    int setShift;
107    /** The amount to shift the address to get the tag. */
108    int tagShift;
109    /** Mask out all bits that aren't part of the set index. */
110    unsigned setMask;
111    /** Mask out all bits that aren't part of the block offset. */
112    unsigned blkMask;
113
114public:
115
116    /** Convenience typedef. */
117     typedef BaseSetAssocParams Params;
118
119    /**
120     * Construct and initialize this tag store.
121     */
122    BaseSetAssoc(const Params *p);
123
124    /**
125     * Destructor
126     */
127    virtual ~BaseSetAssoc();
128
129    /**
130     * Return the block size.
131     * @return the block size.
132     */
133    unsigned
134    getBlockSize() const
135    {
136        return blkSize;
137    }
138
139    /**
140     * Return the subblock size. In the case of BaseSetAssoc it is always
141     * the block size.
142     * @return The block size.
143     */
144    unsigned
145    getSubBlockSize() const
146    {
147        return blkSize;
148    }
149
150    /**
151     * Return the number of sets this cache has
152     * @return The number of sets.
153     */
154    unsigned
155    getNumSets() const override
156    {
157        return numSets;
158    }
159
160    /**
161     * Return the number of ways this cache has
162     * @return The number of ways.
163     */
164    unsigned
165    getNumWays() const override
166    {
167        return assoc;
168    }
169
170    /**
171     * Find the cache block given set and way
172     * @param set The set of the block.
173     * @param way The way of the block.
174     * @return The cache block.
175     */
176    CacheBlk *findBlockBySetAndWay(int set, int way) const override;
177
178    /**
179     * Invalidate the given block.
180     * @param blk The block to invalidate.
181     */
182    void invalidate(CacheBlk *blk) override
183    {
184        assert(blk);
185        assert(blk->isValid());
186        tagsInUse--;
187        assert(blk->srcMasterId < cache->system->maxMasters());
188        occupancies[blk->srcMasterId]--;
189        blk->srcMasterId = Request::invldMasterId;
190        blk->task_id = ContextSwitchTaskId::Unknown;
191        blk->tickInserted = curTick();
192    }
193
194    /**
195     * Access block and update replacement data. May not succeed, in which case
196     * nullptr is returned. This has all the implications of a cache
197     * access and should only be used as such. Returns the access latency as a
198     * side effect.
199     * @param addr The address to find.
200     * @param is_secure True if the target memory space is secure.
201     * @param asid The address space ID.
202     * @param lat The access latency.
203     * @return Pointer to the cache block if found.
204     */
205    CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
206                          int context_src) override
207    {
208        Addr tag = extractTag(addr);
209        int set = extractSet(addr);
210        BlkType *blk = sets[set].findBlk(tag, is_secure);
211        lat = accessLatency;;
212
213        // Access all tags in parallel, hence one in each way.  The data side
214        // either accesses all blocks in parallel, or one block sequentially on
215        // a hit.  Sequential access with a miss doesn't access data.
216        tagAccesses += allocAssoc;
217        if (sequentialAccess) {
218            if (blk != nullptr) {
219                dataAccesses += 1;
220            }
221        } else {
222            dataAccesses += allocAssoc;
223        }
224
225        if (blk != nullptr) {
226            if (blk->whenReady > curTick()
227                && cache->ticksToCycles(blk->whenReady - curTick())
228                > accessLatency) {
229                lat = cache->ticksToCycles(blk->whenReady - curTick());
230            }
231            blk->refCount += 1;
232        }
233
234        return blk;
235    }
236
237    /**
238     * Finds the given address in the cache, do not update replacement data.
239     * i.e. This is a no-side-effect find of a block.
240     * @param addr The address to find.
241     * @param is_secure True if the target memory space is secure.
242     * @param asid The address space ID.
243     * @return Pointer to the cache block if found.
244     */
245    CacheBlk* findBlock(Addr addr, bool is_secure) const override;
246
247    /**
248     * Find an invalid block to evict for the address provided.
249     * If there are no invalid blocks, this will return the block
250     * in the least-recently-used position.
251     * @param addr The addr to a find a replacement candidate for.
252     * @return The candidate block.
253     */
254    CacheBlk* findVictim(Addr addr) override
255    {
256        BlkType *blk = nullptr;
257        int set = extractSet(addr);
258
259        // prefer to evict an invalid block
260        for (int i = 0; i < allocAssoc; ++i) {
261            blk = sets[set].blks[i];
262            if (!blk->isValid())
263                break;
264        }
265
266        return blk;
267    }
268
269    /**
270     * Insert the new block into the cache.
271     * @param pkt Packet holding the address to update
272     * @param blk The block to update.
273     */
274     void insertBlock(PacketPtr pkt, CacheBlk *blk) override
275     {
276         Addr addr = pkt->getAddr();
277         MasterID master_id = pkt->req->masterId();
278         uint32_t task_id = pkt->req->taskId();
279
280         if (!blk->isTouched) {
281             tagsInUse++;
282             blk->isTouched = true;
283             if (!warmedUp && tagsInUse.value() >= warmupBound) {
284                 warmedUp = true;
285                 warmupCycle = curTick();
286             }
287         }
288
289         // If we're replacing a block that was previously valid update
290         // stats for it. This can't be done in findBlock() because a
291         // found block might not actually be replaced there if the
292         // coherence protocol says it can't be.
293         if (blk->isValid()) {
294             replacements[0]++;
295             totalRefs += blk->refCount;
296             ++sampledRefs;
297             blk->refCount = 0;
298
299             // deal with evicted block
300             assert(blk->srcMasterId < cache->system->maxMasters());
301             occupancies[blk->srcMasterId]--;
302
303             blk->invalidate();
304         }
305
306         blk->isTouched = true;
307
308         // Set tag for new block.  Caller is responsible for setting status.
309         blk->tag = extractTag(addr);
310
311         // deal with what we are bringing in
312         assert(master_id < cache->system->maxMasters());
313         occupancies[master_id]++;
314         blk->srcMasterId = master_id;
315         blk->task_id = task_id;
316         blk->tickInserted = curTick();
317
318         // We only need to write into one tag and one data block.
319         tagAccesses += 1;
320         dataAccesses += 1;
321     }
322
323    /**
324     * Limit the allocation for the cache ways.
325     * @param ways The maximum number of ways available for replacement.
326     */
327    virtual void setWayAllocationMax(int ways) override
328    {
329        fatal_if(ways < 1, "Allocation limit must be greater than zero");
330        allocAssoc = ways;
331    }
332
333    /**
334     * Get the way allocation mask limit.
335     * @return The maximum number of ways available for replacement.
336     */
337    virtual int getWayAllocationMax() const override
338    {
339        return allocAssoc;
340    }
341
342    /**
343     * Generate the tag from the given address.
344     * @param addr The address to get the tag from.
345     * @return The tag of the address.
346     */
347    Addr extractTag(Addr addr) const override
348    {
349        return (addr >> tagShift);
350    }
351
352    /**
353     * Calculate the set index from the address.
354     * @param addr The address to get the set from.
355     * @return The set index of the address.
356     */
357    int extractSet(Addr addr) const override
358    {
359        return ((addr >> setShift) & setMask);
360    }
361
362    /**
363     * Align an address to the block size.
364     * @param addr the address to align.
365     * @return The block address.
366     */
367    Addr blkAlign(Addr addr) const
368    {
369        return (addr & ~(Addr)blkMask);
370    }
371
372    /**
373     * Regenerate the block address from the tag.
374     * @param tag The tag of the block.
375     * @param set The set of the block.
376     * @return The block address.
377     */
378    Addr regenerateBlkAddr(Addr tag, unsigned set) const override
379    {
380        return ((tag << tagShift) | ((Addr)set << setShift));
381    }
382
383    /**
384     * Called at end of simulation to complete average block reference stats.
385     */
386    void cleanupRefs() override;
387
388    /**
389     * Print all tags used
390     */
391    std::string print() const override;
392
393    /**
394     * Called prior to dumping stats to compute task occupancy
395     */
396    void computeStats() override;
397
398    /**
399     * Visit each block in the tag store and apply a visitor to the
400     * block.
401     *
402     * The visitor should be a function (or object that behaves like a
403     * function) that takes a cache block reference as its parameter
404     * and returns a bool. A visitor can request the traversal to be
405     * stopped by returning false, returning true causes it to be
406     * called for the next block in the tag store.
407     *
408     * \param visitor Visitor to call on each block.
409     */
410    void forEachBlk(CacheBlkVisitor &visitor) override {
411        for (unsigned i = 0; i < numSets * assoc; ++i) {
412            if (!visitor(blks[i]))
413                return;
414        }
415    }
416};
417
418#endif // __MEM_CACHE_TAGS_BASESETASSOC_HH__
419