stride.cc revision 9288
1/* 2 * Copyright (c) 2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ron Dreslinski 29 * Steve Reinhardt 30 */ 31 32/** 33 * @file 34 * Stride Prefetcher template instantiations. 35 */ 36 37#include "base/trace.hh" 38#include "debug/HWPrefetch.hh" 39#include "mem/cache/prefetch/stride.hh" 40 41void 42StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, 43 std::list<Cycles> &delays) 44{ 45 if (!pkt->req->hasPC()) { 46 DPRINTF(HWPrefetch, "ignoring request with no PC"); 47 return; 48 } 49 50 Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1); 51 MasterID master_id = useMasterId ? pkt->req->masterId() : 0; 52 Addr pc = pkt->req->getPC(); 53 assert(master_id < Max_Contexts); 54 std::list<StrideEntry*> &tab = table[master_id]; 55 56 /* Scan Table for instAddr Match */ 57 std::list<StrideEntry*>::iterator iter; 58 for (iter = tab.begin(); iter != tab.end(); iter++) { 59 if ((*iter)->instAddr == pc) 60 break; 61 } 62 63 if (iter != tab.end()) { 64 // Hit in table 65 66 int new_stride = blk_addr - (*iter)->missAddr; 67 bool stride_match = (new_stride == (*iter)->stride); 68 69 if (stride_match && new_stride != 0) { 70 if ((*iter)->confidence < Max_Conf) 71 (*iter)->confidence++; 72 } else { 73 (*iter)->stride = new_stride; 74 if ((*iter)->confidence > Min_Conf) 75 (*iter)->confidence = 0; 76 } 77 78 DPRINTF(HWPrefetch, "hit: PC %x blk_addr %x stride %d (%s), conf %d\n", 79 pc, blk_addr, new_stride, stride_match ? "match" : "change", 80 (*iter)->confidence); 81 82 (*iter)->missAddr = blk_addr; 83 84 if ((*iter)->confidence <= 0) 85 return; 86 87 for (int d = 1; d <= degree; d++) { 88 Addr new_addr = blk_addr + d * new_stride; 89 if (pageStop && !samePage(blk_addr, new_addr)) { 90 // Spanned the page, so now stop 91 pfSpanPage += degree - d + 1; 92 return; 93 } else { 94 DPRINTF(HWPrefetch, " queuing prefetch to %x @ %d\n", 95 new_addr, latency); 96 addresses.push_back(new_addr); 97 delays.push_back(latency); 98 } 99 } 100 } else { 101 // Miss in table 102 // Find lowest confidence and replace 103 104 DPRINTF(HWPrefetch, "miss: PC %x blk_addr %x\n", pc, blk_addr); 105 106 if (tab.size() >= 256) { //set default table size is 256 107 std::list<StrideEntry*>::iterator min_pos = tab.begin(); 108 int min_conf = (*min_pos)->confidence; 109 for (iter = min_pos, ++iter; iter != tab.end(); ++iter) { 110 if ((*iter)->confidence < min_conf){ 111 min_pos = iter; 112 min_conf = (*iter)->confidence; 113 } 114 } 115 DPRINTF(HWPrefetch, " replacing PC %x\n", (*min_pos)->instAddr); 116 117 // free entry and delete it 118 delete *min_pos; 119 tab.erase(min_pos); 120 } 121 122 StrideEntry *new_entry = new StrideEntry; 123 new_entry->instAddr = pc; 124 new_entry->missAddr = blk_addr; 125 new_entry->stride = 0; 126 new_entry->confidence = 0; 127 tab.push_back(new_entry); 128 } 129} 130 131 132StridePrefetcher* 133StridePrefetcherParams::create() 134{ 135 return new StridePrefetcher(this); 136} 137