stride.cc revision 10623 
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Steve Reinhardt
42 */
43
44/**
45 * @file
46 * Stride Prefetcher template instantiations.
47 */
48
49#include "debug/HWPrefetch.hh"
50#include "mem/cache/prefetch/stride.hh"
51
52StridePrefetcher::StridePrefetcher(const StridePrefetcherParams *p)
53    : QueuedPrefetcher(p),
54      maxConf(p->max_conf),
55      threshConf(p->thresh_conf),
56      minConf(p->min_conf),
57      startConf(p->start_conf),
58      pcTableAssoc(p->table_assoc),
59      pcTableSets(p->table_sets),
60      useMasterId(p->use_master_id),
61      degree(p->degree)
62{
63    // Don't consult stride prefetcher on instruction accesses
64    onInst = false;
65
66    assert(isPowerOf2(pcTableSets));
67
68    for (int c = 0; c < maxContexts; c++) {
69        pcTable[c] = new StrideEntry*[pcTableSets];
70        for (int s = 0; s < pcTableSets; s++) {
71            pcTable[c][s] = new StrideEntry[pcTableAssoc];
72        }
73    }
74}
75
76StridePrefetcher::~StridePrefetcher()
77{
78    for (int c = 0; c < maxContexts; c++) {
79        for (int s = 0; s < pcTableSets; s++) {
80            delete[] pcTable[c][s];
81        }
82    }
83}
84
85void
86StridePrefetcher::calculatePrefetch(const PacketPtr &pkt,
87                                    std::vector<Addr> &addresses)
88{
89    if (!pkt->req->hasPC()) {
90        DPRINTF(HWPrefetch, "Ignoring request with no PC.\n");
91        return;
92    }
93
94    // Get required packet info
95    Addr pkt_addr = pkt->getAddr();
96    Addr pc = pkt->req->getPC();
97    bool is_secure = pkt->isSecure();
98    MasterID master_id = useMasterId ? pkt->req->masterId() : 0;
99
100    assert(master_id < maxContexts);
101
102    // Lookup pc-based information
103    StrideEntry *entry;
104
105    if(pcTableHit(pc, is_secure, master_id, entry)) {
106        // Hit in table
107        int new_stride = pkt_addr - entry->lastAddr;
108        bool stride_match = (new_stride == entry->stride);
109
110        // Adjust confidence for stride entry
111        if (stride_match && new_stride != 0) {
112            if (entry->confidence < maxConf)
113                entry->confidence++;
114        } else {
115            if (entry->confidence > minConf)
116                entry->confidence--;
117            // If confidence has dropped below the threshold, train new stride
118            if (entry->confidence < threshConf)
119                entry->stride = new_stride;
120        }
121
122        DPRINTF(HWPrefetch, "Hit: PC %x pkt_addr %x (%s) stride %d (%s), "
123                "conf %d\n", pc, pkt_addr, is_secure ? "s" : "ns", new_stride,
124                stride_match ? "match" : "change",
125                entry->confidence);
126
127        entry->lastAddr = pkt_addr;
128
129        // Abort prefetch generation if below confidence threshold
130        if (entry->confidence < threshConf)
131            return;
132
133        // Generate up to degree prefetches
134        for (int d = 1; d <= degree; d++) {
135            // Round strides up to atleast 1 cacheline
136            int prefetch_stride = new_stride;
137            if (abs(new_stride) < blkSize) {
138                prefetch_stride = (new_stride < 0) ? -blkSize : blkSize;
139            }
140
141            Addr new_addr = pkt_addr + d * prefetch_stride;
142            if (samePage(pkt_addr, new_addr)) {
143                DPRINTF(HWPrefetch, "Queuing prefetch to %#x.\n", new_addr);
144                addresses.push_back(new_addr);
145            } else {
146                // Record the number of page crossing prefetches generated
147                pfSpanPage += degree - d + 1;
148                DPRINTF(HWPrefetch, "Ignoring page crossing prefetch.\n");
149                return;
150            }
151        }
152    } else {
153        // Miss in table
154        DPRINTF(HWPrefetch, "Miss: PC %x pkt_addr %x (%s)\n", pc, pkt_addr,
155                is_secure ? "s" : "ns");
156
157        StrideEntry* entry = pcTableVictim(pc, master_id);
158        entry->instAddr = pc;
159        entry->lastAddr = pkt_addr;
160        entry->isSecure= is_secure;
161        entry->stride = 0;
162        entry->confidence = startConf;
163    }
164}
165
166inline Addr
167StridePrefetcher::pcHash(Addr pc) const
168{
169    Addr hash1 = pc >> 1;
170    Addr hash2 = hash1 >> floorLog2(pcTableSets);
171    return (hash1 ^ hash2) & (Addr)(pcTableSets - 1);
172}
173
174inline StridePrefetcher::StrideEntry*
175StridePrefetcher::pcTableVictim(Addr pc, int master_id)
176{
177    // Rand replacement for now
178    int set = pcHash(pc);
179    int way = rand() % pcTableAssoc;
180
181    DPRINTF(HWPrefetch, "Victimizing lookup table[%d][%d].\n", set, way);
182    return &pcTable[master_id][set][way];
183}
184
185inline bool
186StridePrefetcher::pcTableHit(Addr pc, bool is_secure, int master_id,
187                             StrideEntry* &entry)
188{
189    int set = pcHash(pc);
190    StrideEntry* set_entries = pcTable[master_id][set];
191    for (int way = 0; way < pcTableAssoc; way++) {
192        // Search ways for match
193        if (set_entries[way].instAddr == pc &&
194            set_entries[way].isSecure == is_secure) {
195            DPRINTF(HWPrefetch, "Lookup hit table[%d][%d].\n", set, way);
196            entry = &set_entries[way];
197            return true;
198        }
199    }
200    return false;
201}
202
203StridePrefetcher*
204StridePrefetcherParams::create()
205{
206    return new StridePrefetcher(this);
207}
208