stride.cc revision 5338
12810SN/A/*
22810SN/A * Copyright (c) 2005 The Regents of The University of Michigan
32810SN/A * All rights reserved.
42810SN/A *
52810SN/A * Redistribution and use in source and binary forms, with or without
62810SN/A * modification, are permitted provided that the following conditions are
72810SN/A * met: redistributions of source code must retain the above copyright
82810SN/A * notice, this list of conditions and the following disclaimer;
92810SN/A * redistributions in binary form must reproduce the above copyright
102810SN/A * notice, this list of conditions and the following disclaimer in the
112810SN/A * documentation and/or other materials provided with the distribution;
122810SN/A * neither the name of the copyright holders nor the names of its
132810SN/A * contributors may be used to endorse or promote products derived from
142810SN/A * this software without specific prior written permission.
152810SN/A *
162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272810SN/A *
282810SN/A * Authors: Ron Dreslinski
292810SN/A *          Steve Reinhardt
302810SN/A */
312810SN/A
322810SN/A/**
332810SN/A * @file
342810SN/A * Stride Prefetcher template instantiations.
352810SN/A */
362810SN/A
375338Sstever@gmail.com#include "mem/cache/prefetch/stride.hh"
382810SN/A
393861SN/Avoid
403861SN/AStridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
413861SN/A                                    std::list<Tick> &delays)
423861SN/A{
433861SN/A//	Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1);
443861SN/A    int cpuID = pkt->req->getCpuNum();
453861SN/A    if (!useCPUId) cpuID = 0;
462810SN/A
473861SN/A    /* Scan Table for IAddr Match */
483861SN/A/*	std::list<strideEntry*>::iterator iter;
493861SN/A  for (iter=table[cpuID].begin();
503861SN/A  iter !=table[cpuID].end();
513861SN/A  iter++) {
523861SN/A  if ((*iter)->IAddr == pkt->pc) break;
533861SN/A  }
542810SN/A
553861SN/A  if (iter != table[cpuID].end()) {
563861SN/A  //Hit in table
573861SN/A
583861SN/A  int newStride = blkAddr - (*iter)->MAddr;
593861SN/A  if (newStride == (*iter)->stride) {
603861SN/A  (*iter)->confidence++;
613861SN/A  }
623861SN/A  else {
633861SN/A  (*iter)->stride = newStride;
643861SN/A  (*iter)->confidence--;
653861SN/A  }
663861SN/A
673861SN/A  (*iter)->MAddr = blkAddr;
683861SN/A
693861SN/A  for (int d=1; d <= degree; d++) {
703861SN/A  Addr newAddr = blkAddr + d * newStride;
713861SN/A  if (this->pageStop &&
723861SN/A  (blkAddr & ~(TheISA::VMPageSize - 1)) !=
733861SN/A  (newAddr & ~(TheISA::VMPageSize - 1)))
743861SN/A  {
753861SN/A  //Spanned the page, so now stop
763861SN/A  this->pfSpanPage += degree - d + 1;
773861SN/A  return;
783861SN/A  }
793861SN/A  else
803861SN/A  {
813861SN/A  addresses.push_back(newAddr);
823861SN/A  delays.push_back(latency);
833861SN/A  }
843861SN/A  }
853861SN/A  }
863861SN/A  else {
873861SN/A  //Miss in table
883861SN/A  //Find lowest confidence and replace
893861SN/A
903861SN/A  }
913861SN/A*/
923861SN/A}
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