base.hh revision 13667
18541Sgblack@eecs.umich.edu/* 28541Sgblack@eecs.umich.edu * Copyright (c) 2013-2014 ARM Limited 38541Sgblack@eecs.umich.edu * All rights reserved. 48541Sgblack@eecs.umich.edu * 58541Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 68541Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 78541Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 88541Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 98541Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 108541Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 118541Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 128541Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 138541Sgblack@eecs.umich.edu * 148541Sgblack@eecs.umich.edu * Copyright (c) 2005 The Regents of The University of Michigan 158541Sgblack@eecs.umich.edu * All rights reserved. 168541Sgblack@eecs.umich.edu * 178541Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 188541Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 198541Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 208541Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 218541Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 228541Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 238541Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 248541Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 258541Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 268541Sgblack@eecs.umich.edu * this software without specific prior written permission. 278541Sgblack@eecs.umich.edu * 288541Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 298541Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 308541Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 318541Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 328541Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 338541Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 348541Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 358541Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 368541Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 378541Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389024Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 398541Sgblack@eecs.umich.edu * 409022Sgblack@eecs.umich.edu * Authors: Ron Dreslinski 419022Sgblack@eecs.umich.edu * Mitch Hayenga 429022Sgblack@eecs.umich.edu */ 439022Sgblack@eecs.umich.edu 448541Sgblack@eecs.umich.edu/** 459024Sgblack@eecs.umich.edu * @file 468541Sgblack@eecs.umich.edu * Miss and writeback queue declarations. 478541Sgblack@eecs.umich.edu */ 489024Sgblack@eecs.umich.edu 499024Sgblack@eecs.umich.edu#ifndef __MEM_CACHE_PREFETCH_BASE_HH__ 509024Sgblack@eecs.umich.edu#define __MEM_CACHE_PREFETCH_BASE_HH__ 519024Sgblack@eecs.umich.edu 529024Sgblack@eecs.umich.edu#include <cstdint> 539024Sgblack@eecs.umich.edu 549024Sgblack@eecs.umich.edu#include "base/statistics.hh" 559024Sgblack@eecs.umich.edu#include "base/types.hh" 569024Sgblack@eecs.umich.edu#include "mem/packet.hh" 579024Sgblack@eecs.umich.edu#include "mem/request.hh" 589024Sgblack@eecs.umich.edu#include "sim/clocked_object.hh" 598541Sgblack@eecs.umich.edu#include "sim/probe/probe.hh" 609024Sgblack@eecs.umich.edu 619024Sgblack@eecs.umich.educlass BaseCache; 629024Sgblack@eecs.umich.edustruct BasePrefetcherParams; 639024Sgblack@eecs.umich.edu 649024Sgblack@eecs.umich.educlass BasePrefetcher : public ClockedObject 659024Sgblack@eecs.umich.edu{ 668541Sgblack@eecs.umich.edu class PrefetchListener : public ProbeListenerArgBase<PacketPtr> 679024Sgblack@eecs.umich.edu { 689024Sgblack@eecs.umich.edu public: 699024Sgblack@eecs.umich.edu PrefetchListener(BasePrefetcher &_parent, ProbeManager *pm, 709024Sgblack@eecs.umich.edu const std::string &name) 718541Sgblack@eecs.umich.edu : ProbeListenerArgBase(pm, name), 729024Sgblack@eecs.umich.edu parent(_parent) {} 739024Sgblack@eecs.umich.edu void notify(const PacketPtr &pkt) override; 749024Sgblack@eecs.umich.edu protected: 758541Sgblack@eecs.umich.edu BasePrefetcher &parent; 769024Sgblack@eecs.umich.edu }; 779024Sgblack@eecs.umich.edu 789024Sgblack@eecs.umich.edu std::vector<PrefetchListener *> listeners; 799024Sgblack@eecs.umich.edu 809024Sgblack@eecs.umich.edu public: 819024Sgblack@eecs.umich.edu 829024Sgblack@eecs.umich.edu /** 839024Sgblack@eecs.umich.edu * Class containing the information needed by the prefetch to train and 849021Sgblack@eecs.umich.edu * generate new prefetch requests. 859024Sgblack@eecs.umich.edu */ 869024Sgblack@eecs.umich.edu class PrefetchInfo { 879024Sgblack@eecs.umich.edu /** The address. */ 889024Sgblack@eecs.umich.edu Addr address; 899024Sgblack@eecs.umich.edu /** The program counter that generated this address. */ 909024Sgblack@eecs.umich.edu Addr pc; 919024Sgblack@eecs.umich.edu /** The requestor ID that generated this address. */ 929024Sgblack@eecs.umich.edu MasterID masterId; 939024Sgblack@eecs.umich.edu /** Validity bit for the PC of this address. */ 949024Sgblack@eecs.umich.edu bool validPC; 959024Sgblack@eecs.umich.edu /** Whether this address targets the secure memory space. */ 968541Sgblack@eecs.umich.edu bool secure; 979024Sgblack@eecs.umich.edu 989024Sgblack@eecs.umich.edu public: 999024Sgblack@eecs.umich.edu /** 1009024Sgblack@eecs.umich.edu * Obtains the address value of this Prefetcher address. 1019024Sgblack@eecs.umich.edu * @return the addres value. 1029024Sgblack@eecs.umich.edu */ 1039024Sgblack@eecs.umich.edu Addr getAddr() const 1049024Sgblack@eecs.umich.edu { 1059024Sgblack@eecs.umich.edu return address; 1069024Sgblack@eecs.umich.edu } 1079024Sgblack@eecs.umich.edu 1089024Sgblack@eecs.umich.edu /** 1099024Sgblack@eecs.umich.edu * Returns true if the address targets the secure memory space. 1109024Sgblack@eecs.umich.edu * @return true if the address targets the secure memory space. 1118541Sgblack@eecs.umich.edu */ 1128541Sgblack@eecs.umich.edu bool isSecure() const 1139024Sgblack@eecs.umich.edu { 1149024Sgblack@eecs.umich.edu return secure; 1159024Sgblack@eecs.umich.edu } 1169024Sgblack@eecs.umich.edu 1179024Sgblack@eecs.umich.edu /** 1189024Sgblack@eecs.umich.edu * Returns the program counter that generated this request. 1199024Sgblack@eecs.umich.edu * @return the pc value 1209024Sgblack@eecs.umich.edu */ 1219024Sgblack@eecs.umich.edu Addr getPC() const 1229024Sgblack@eecs.umich.edu { 1239024Sgblack@eecs.umich.edu assert(hasPC()); 1249024Sgblack@eecs.umich.edu return pc; 1258541Sgblack@eecs.umich.edu } 1268541Sgblack@eecs.umich.edu 1279024Sgblack@eecs.umich.edu /** 1289024Sgblack@eecs.umich.edu * Returns true if the associated program counter is valid 1298541Sgblack@eecs.umich.edu * @return true if the program counter has a valid value 130 */ 131 bool hasPC() const 132 { 133 return validPC; 134 } 135 136 /** 137 * Gets the requestor ID that generated this address 138 * @return the requestor ID that generated this address 139 */ 140 MasterID getMasterId() const 141 { 142 return masterId; 143 } 144 145 /** 146 * Check for equality 147 * @param pfi PrefetchInfo to compare against 148 * @return True if this object and the provided one are equal 149 */ 150 bool sameAddr(PrefetchInfo const &pfi) const 151 { 152 return this->getAddr() == pfi.getAddr() && 153 this->isSecure() == pfi.isSecure(); 154 } 155 156 /** 157 * Constructs a PrefetchInfo using a PacketPtr. 158 * @param pkt PacketPtr used to generate the PrefetchInfo 159 * @param addr the address value of the new object 160 */ 161 PrefetchInfo(PacketPtr pkt, Addr addr); 162 163 /** 164 * Constructs a PrefetchInfo using a new address value and 165 * another PrefetchInfo as a reference. 166 * @param pfi PrefetchInfo used to generate this new object 167 * @param addr the address value of the new object 168 */ 169 PrefetchInfo(PrefetchInfo const &pfi, Addr addr); 170 }; 171 172 protected: 173 174 // PARAMETERS 175 176 /** Pointr to the parent cache. */ 177 BaseCache* cache; 178 179 /** The block size of the parent cache. */ 180 unsigned blkSize; 181 182 /** log_2(block size of the parent cache). */ 183 unsigned lBlkSize; 184 185 /** Only consult prefetcher on cache misses? */ 186 const bool onMiss; 187 188 /** Consult prefetcher on reads? */ 189 const bool onRead; 190 191 /** Consult prefetcher on reads? */ 192 const bool onWrite; 193 194 /** Consult prefetcher on data accesses? */ 195 const bool onData; 196 197 /** Consult prefetcher on instruction accesses? */ 198 const bool onInst; 199 200 /** Request id for prefetches */ 201 const MasterID masterId; 202 203 const Addr pageBytes; 204 205 /** Prefetch on every access, not just misses */ 206 const bool prefetchOnAccess; 207 208 /** Use Virtual Addresses for prefetching */ 209 const bool useVirtualAddresses; 210 211 /** Determine if this access should be observed */ 212 bool observeAccess(const PacketPtr &pkt) const; 213 214 /** Determine if address is in cache */ 215 bool inCache(Addr addr, bool is_secure) const; 216 217 /** Determine if address is in cache miss queue */ 218 bool inMissQueue(Addr addr, bool is_secure) const; 219 220 bool hasBeenPrefetched(Addr addr, bool is_secure) const; 221 222 /** Determine if addresses are on the same page */ 223 bool samePage(Addr a, Addr b) const; 224 /** Determine the address of the block in which a lays */ 225 Addr blockAddress(Addr a) const; 226 /** Determine the address of a at block granularity */ 227 Addr blockIndex(Addr a) const; 228 /** Determine the address of the page in which a lays */ 229 Addr pageAddress(Addr a) const; 230 /** Determine the page-offset of a */ 231 Addr pageOffset(Addr a) const; 232 /** Build the address of the i-th block inside the page */ 233 Addr pageIthBlockAddress(Addr page, uint32_t i) const; 234 235 Stats::Scalar pfIssued; 236 237 /** Total prefetches issued */ 238 uint64_t issuedPrefetches; 239 /** Total prefetches that has been useful */ 240 uint64_t usefulPrefetches; 241 242 public: 243 244 BasePrefetcher(const BasePrefetcherParams *p); 245 246 virtual ~BasePrefetcher() {} 247 248 void setCache(BaseCache *_cache); 249 250 /** 251 * Notify prefetcher of cache access (may be any access or just 252 * misses, depending on cache parameters.) 253 */ 254 virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) = 0; 255 256 virtual PacketPtr getPacket() = 0; 257 258 virtual Tick nextPrefetchReadyTime() const = 0; 259 260 /** 261 * Register local statistics. 262 */ 263 void regStats() override; 264 265 /** 266 * Register probe points for this object. 267 */ 268 void regProbeListeners() override; 269 270 /** 271 * Process a notification event from the ProbeListener. 272 * @param pkt The memory request causing the event 273 */ 274 void probeNotify(const PacketPtr &pkt); 275 276 /** 277 * Add a SimObject and a probe name to listen events from 278 * @param obj The SimObject pointer to listen from 279 * @param name The probe name 280 */ 281 void addEventProbe(SimObject *obj, const char *name); 282}; 283#endif //__MEM_CACHE_PREFETCH_BASE_HH__ 284