base.hh revision 13667
1/* 2 * Copyright (c) 2013-2014 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ron Dreslinski 41 * Mitch Hayenga 42 */ 43 44/** 45 * @file 46 * Miss and writeback queue declarations. 47 */ 48 49#ifndef __MEM_CACHE_PREFETCH_BASE_HH__ 50#define __MEM_CACHE_PREFETCH_BASE_HH__ 51 52#include <cstdint> 53 54#include "base/statistics.hh" 55#include "base/types.hh" 56#include "mem/packet.hh" 57#include "mem/request.hh" 58#include "sim/clocked_object.hh" 59#include "sim/probe/probe.hh" 60 61class BaseCache; 62struct BasePrefetcherParams; 63 64class BasePrefetcher : public ClockedObject 65{ 66 class PrefetchListener : public ProbeListenerArgBase<PacketPtr> 67 { 68 public: 69 PrefetchListener(BasePrefetcher &_parent, ProbeManager *pm, 70 const std::string &name) 71 : ProbeListenerArgBase(pm, name), 72 parent(_parent) {} 73 void notify(const PacketPtr &pkt) override; 74 protected: 75 BasePrefetcher &parent; 76 }; 77 78 std::vector<PrefetchListener *> listeners; 79 80 public: 81 82 /** 83 * Class containing the information needed by the prefetch to train and 84 * generate new prefetch requests. 85 */ 86 class PrefetchInfo { 87 /** The address. */ 88 Addr address; 89 /** The program counter that generated this address. */ 90 Addr pc; 91 /** The requestor ID that generated this address. */ 92 MasterID masterId; 93 /** Validity bit for the PC of this address. */ 94 bool validPC; 95 /** Whether this address targets the secure memory space. */ 96 bool secure; 97 98 public: 99 /** 100 * Obtains the address value of this Prefetcher address. 101 * @return the addres value. 102 */ 103 Addr getAddr() const 104 { 105 return address; 106 } 107 108 /** 109 * Returns true if the address targets the secure memory space. 110 * @return true if the address targets the secure memory space. 111 */ 112 bool isSecure() const 113 { 114 return secure; 115 } 116 117 /** 118 * Returns the program counter that generated this request. 119 * @return the pc value 120 */ 121 Addr getPC() const 122 { 123 assert(hasPC()); 124 return pc; 125 } 126 127 /** 128 * Returns true if the associated program counter is valid 129 * @return true if the program counter has a valid value 130 */ 131 bool hasPC() const 132 { 133 return validPC; 134 } 135 136 /** 137 * Gets the requestor ID that generated this address 138 * @return the requestor ID that generated this address 139 */ 140 MasterID getMasterId() const 141 { 142 return masterId; 143 } 144 145 /** 146 * Check for equality 147 * @param pfi PrefetchInfo to compare against 148 * @return True if this object and the provided one are equal 149 */ 150 bool sameAddr(PrefetchInfo const &pfi) const 151 { 152 return this->getAddr() == pfi.getAddr() && 153 this->isSecure() == pfi.isSecure(); 154 } 155 156 /** 157 * Constructs a PrefetchInfo using a PacketPtr. 158 * @param pkt PacketPtr used to generate the PrefetchInfo 159 * @param addr the address value of the new object 160 */ 161 PrefetchInfo(PacketPtr pkt, Addr addr); 162 163 /** 164 * Constructs a PrefetchInfo using a new address value and 165 * another PrefetchInfo as a reference. 166 * @param pfi PrefetchInfo used to generate this new object 167 * @param addr the address value of the new object 168 */ 169 PrefetchInfo(PrefetchInfo const &pfi, Addr addr); 170 }; 171 172 protected: 173 174 // PARAMETERS 175 176 /** Pointr to the parent cache. */ 177 BaseCache* cache; 178 179 /** The block size of the parent cache. */ 180 unsigned blkSize; 181 182 /** log_2(block size of the parent cache). */ 183 unsigned lBlkSize; 184 185 /** Only consult prefetcher on cache misses? */ 186 const bool onMiss; 187 188 /** Consult prefetcher on reads? */ 189 const bool onRead; 190 191 /** Consult prefetcher on reads? */ 192 const bool onWrite; 193 194 /** Consult prefetcher on data accesses? */ 195 const bool onData; 196 197 /** Consult prefetcher on instruction accesses? */ 198 const bool onInst; 199 200 /** Request id for prefetches */ 201 const MasterID masterId; 202 203 const Addr pageBytes; 204 205 /** Prefetch on every access, not just misses */ 206 const bool prefetchOnAccess; 207 208 /** Use Virtual Addresses for prefetching */ 209 const bool useVirtualAddresses; 210 211 /** Determine if this access should be observed */ 212 bool observeAccess(const PacketPtr &pkt) const; 213 214 /** Determine if address is in cache */ 215 bool inCache(Addr addr, bool is_secure) const; 216 217 /** Determine if address is in cache miss queue */ 218 bool inMissQueue(Addr addr, bool is_secure) const; 219 220 bool hasBeenPrefetched(Addr addr, bool is_secure) const; 221 222 /** Determine if addresses are on the same page */ 223 bool samePage(Addr a, Addr b) const; 224 /** Determine the address of the block in which a lays */ 225 Addr blockAddress(Addr a) const; 226 /** Determine the address of a at block granularity */ 227 Addr blockIndex(Addr a) const; 228 /** Determine the address of the page in which a lays */ 229 Addr pageAddress(Addr a) const; 230 /** Determine the page-offset of a */ 231 Addr pageOffset(Addr a) const; 232 /** Build the address of the i-th block inside the page */ 233 Addr pageIthBlockAddress(Addr page, uint32_t i) const; 234 235 Stats::Scalar pfIssued; 236 237 /** Total prefetches issued */ 238 uint64_t issuedPrefetches; 239 /** Total prefetches that has been useful */ 240 uint64_t usefulPrefetches; 241 242 public: 243 244 BasePrefetcher(const BasePrefetcherParams *p); 245 246 virtual ~BasePrefetcher() {} 247 248 void setCache(BaseCache *_cache); 249 250 /** 251 * Notify prefetcher of cache access (may be any access or just 252 * misses, depending on cache parameters.) 253 */ 254 virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) = 0; 255 256 virtual PacketPtr getPacket() = 0; 257 258 virtual Tick nextPrefetchReadyTime() const = 0; 259 260 /** 261 * Register local statistics. 262 */ 263 void regStats() override; 264 265 /** 266 * Register probe points for this object. 267 */ 268 void regProbeListeners() override; 269 270 /** 271 * Process a notification event from the ProbeListener. 272 * @param pkt The memory request causing the event 273 */ 274 void probeNotify(const PacketPtr &pkt); 275 276 /** 277 * Add a SimObject and a probe name to listen events from 278 * @param obj The SimObject pointer to listen from 279 * @param name The probe name 280 */ 281 void addEventProbe(SimObject *obj, const char *name); 282}; 283#endif //__MEM_CACHE_PREFETCH_BASE_HH__ 284