Prefetcher.py revision 13735:52ab3bab4f28
113168Smatt.horsnell@arm.com# Copyright (c) 2012, 2014 ARM Limited 213168Smatt.horsnell@arm.com# All rights reserved. 313168Smatt.horsnell@arm.com# 413168Smatt.horsnell@arm.com# The license below extends only to copyright in the software and shall 513168Smatt.horsnell@arm.com# not be construed as granting a license to any other intellectual 613168Smatt.horsnell@arm.com# property including but not limited to intellectual property relating 713168Smatt.horsnell@arm.com# to a hardware implementation of the functionality of the software 813168Smatt.horsnell@arm.com# licensed hereunder. You may use the software subject to the license 913168Smatt.horsnell@arm.com# terms below provided that you ensure that this notice is replicated 1013168Smatt.horsnell@arm.com# unmodified and in its entirety in all distributions of the software, 1113168Smatt.horsnell@arm.com# modified or unmodified, in source code or in binary form. 1213168Smatt.horsnell@arm.com# 1313168Smatt.horsnell@arm.com# Copyright (c) 2005 The Regents of The University of Michigan 1413168Smatt.horsnell@arm.com# All rights reserved. 1513168Smatt.horsnell@arm.com# 1613168Smatt.horsnell@arm.com# Redistribution and use in source and binary forms, with or without 1713168Smatt.horsnell@arm.com# modification, are permitted provided that the following conditions are 1813168Smatt.horsnell@arm.com# met: redistributions of source code must retain the above copyright 1913168Smatt.horsnell@arm.com# notice, this list of conditions and the following disclaimer; 2013168Smatt.horsnell@arm.com# redistributions in binary form must reproduce the above copyright 2113168Smatt.horsnell@arm.com# notice, this list of conditions and the following disclaimer in the 2213168Smatt.horsnell@arm.com# documentation and/or other materials provided with the distribution; 2313168Smatt.horsnell@arm.com# neither the name of the copyright holders nor the names of its 2413168Smatt.horsnell@arm.com# contributors may be used to endorse or promote products derived from 2513168Smatt.horsnell@arm.com# this software without specific prior written permission. 2613168Smatt.horsnell@arm.com# 2713168Smatt.horsnell@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2813168Smatt.horsnell@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2913168Smatt.horsnell@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3013168Smatt.horsnell@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3113168Smatt.horsnell@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3213168Smatt.horsnell@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3313168Smatt.horsnell@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3413168Smatt.horsnell@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3513168Smatt.horsnell@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3613168Smatt.horsnell@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3713168Smatt.horsnell@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3813168Smatt.horsnell@arm.com# 3913168Smatt.horsnell@arm.com# Authors: Ron Dreslinski 4013168Smatt.horsnell@arm.com# Mitch Hayenga 4113168Smatt.horsnell@arm.com 4213168Smatt.horsnell@arm.comfrom m5.SimObject import * 4313168Smatt.horsnell@arm.comfrom m5.params import * 4413168Smatt.horsnell@arm.comfrom m5.proxy import * 4513168Smatt.horsnell@arm.com 4613168Smatt.horsnell@arm.comfrom m5.objects.ClockedObject import ClockedObject 4713168Smatt.horsnell@arm.comfrom m5.objects.IndexingPolicies import * 4813168Smatt.horsnell@arm.comfrom m5.objects.ReplacementPolicies import * 4913169Smatt.horsnell@arm.com 5013169Smatt.horsnell@arm.comclass HWPProbeEvent(object): 5113169Smatt.horsnell@arm.com def __init__(self, prefetcher, obj, *listOfNames): 5213169Smatt.horsnell@arm.com self.obj = obj 5313169Smatt.horsnell@arm.com self.prefetcher = prefetcher 5413169Smatt.horsnell@arm.com self.names = listOfNames 5513169Smatt.horsnell@arm.com 5613169Smatt.horsnell@arm.com def register(self): 5713169Smatt.horsnell@arm.com if self.obj: 5813169Smatt.horsnell@arm.com for name in self.names: 5913169Smatt.horsnell@arm.com self.prefetcher.getCCObject().addEventProbe( 6013169Smatt.horsnell@arm.com self.obj.getCCObject(), name) 6113169Smatt.horsnell@arm.com 6213169Smatt.horsnell@arm.comclass BasePrefetcher(ClockedObject): 6313169Smatt.horsnell@arm.com type = 'BasePrefetcher' 6413169Smatt.horsnell@arm.com abstract = True 6513169Smatt.horsnell@arm.com cxx_header = "mem/cache/prefetch/base.hh" 6613169Smatt.horsnell@arm.com cxx_exports = [ 6713169Smatt.horsnell@arm.com PyBindMethod("addEventProbe"), 6813169Smatt.horsnell@arm.com ] 6913169Smatt.horsnell@arm.com sys = Param.System(Parent.any, "System this prefetcher belongs to") 7013169Smatt.horsnell@arm.com 7113169Smatt.horsnell@arm.com # Get the block size from the parent (system) 7213169Smatt.horsnell@arm.com block_size = Param.Int(Parent.cache_line_size, "Block size in bytes") 7313169Smatt.horsnell@arm.com 7413169Smatt.horsnell@arm.com on_miss = Param.Bool(False, "Only notify prefetcher on misses") 7513169Smatt.horsnell@arm.com on_read = Param.Bool(True, "Notify prefetcher on reads") 7613169Smatt.horsnell@arm.com on_write = Param.Bool(True, "Notify prefetcher on writes") 7713169Smatt.horsnell@arm.com on_data = Param.Bool(True, "Notify prefetcher on data accesses") 7813169Smatt.horsnell@arm.com on_inst = Param.Bool(True, "Notify prefetcher on instruction accesses") 7913169Smatt.horsnell@arm.com prefetch_on_access = Param.Bool(Parent.prefetch_on_access, 8013169Smatt.horsnell@arm.com "Notify the hardware prefetcher on every access (not just misses)") 8113169Smatt.horsnell@arm.com use_virtual_addresses = Param.Bool(False, 8213169Smatt.horsnell@arm.com "Use virtual addresses for prefetching") 8313169Smatt.horsnell@arm.com 8413169Smatt.horsnell@arm.com _events = [] 8513169Smatt.horsnell@arm.com def addEvent(self, newObject): 8613169Smatt.horsnell@arm.com self._events.append(newObject) 8713169Smatt.horsnell@arm.com 8813169Smatt.horsnell@arm.com # Override the normal SimObject::regProbeListeners method and 8913169Smatt.horsnell@arm.com # register deferred event handlers. 9013169Smatt.horsnell@arm.com def regProbeListeners(self): 9113169Smatt.horsnell@arm.com for event in self._events: 9213169Smatt.horsnell@arm.com event.register() 9313169Smatt.horsnell@arm.com self.getCCObject().regProbeListeners() 9413169Smatt.horsnell@arm.com 9513169Smatt.horsnell@arm.com def listenFromProbe(self, simObj, *probeNames): 9613169Smatt.horsnell@arm.com if not isinstance(simObj, SimObject): 9713169Smatt.horsnell@arm.com raise TypeError("argument must be of SimObject type") 9813169Smatt.horsnell@arm.com if len(probeNames) <= 0: 9913169Smatt.horsnell@arm.com raise TypeError("probeNames must have at least one element") 10013169Smatt.horsnell@arm.com self.addEvent(HWPProbeEvent(self, simObj, *probeNames)) 10113169Smatt.horsnell@arm.com 10213169Smatt.horsnell@arm.comclass QueuedPrefetcher(BasePrefetcher): 10313169Smatt.horsnell@arm.com type = "QueuedPrefetcher" 10413169Smatt.horsnell@arm.com abstract = True 10513169Smatt.horsnell@arm.com cxx_class = "QueuedPrefetcher" 10613169Smatt.horsnell@arm.com cxx_header = "mem/cache/prefetch/queued.hh" 10713169Smatt.horsnell@arm.com latency = Param.Int(1, "Latency for generated prefetches") 10813169Smatt.horsnell@arm.com queue_size = Param.Int(32, "Maximum number of queued prefetches") 10913169Smatt.horsnell@arm.com queue_squash = Param.Bool(True, "Squash queued prefetch on demand access") 11013169Smatt.horsnell@arm.com queue_filter = Param.Bool(True, "Don't queue redundant prefetches") 11113169Smatt.horsnell@arm.com cache_snoop = Param.Bool(False, "Snoop cache to eliminate redundant request") 11213169Smatt.horsnell@arm.com 11313169Smatt.horsnell@arm.com tag_prefetch = Param.Bool(True, "Tag prefetch with PC of generating access") 11413169Smatt.horsnell@arm.com 11513169Smatt.horsnell@arm.comclass StridePrefetcher(QueuedPrefetcher): 11613169Smatt.horsnell@arm.com type = 'StridePrefetcher' 11713169Smatt.horsnell@arm.com cxx_class = 'StridePrefetcher' 11813169Smatt.horsnell@arm.com cxx_header = "mem/cache/prefetch/stride.hh" 11913169Smatt.horsnell@arm.com 12013169Smatt.horsnell@arm.com # Do not consult stride prefetcher on instruction accesses 12113169Smatt.horsnell@arm.com on_inst = False 12213169Smatt.horsnell@arm.com 12313169Smatt.horsnell@arm.com max_conf = Param.Int(7, "Maximum confidence level") 12413169Smatt.horsnell@arm.com thresh_conf = Param.Int(4, "Threshold confidence level") 12513169Smatt.horsnell@arm.com min_conf = Param.Int(0, "Minimum confidence level") 12613169Smatt.horsnell@arm.com start_conf = Param.Int(4, "Starting confidence for new entries") 12713169Smatt.horsnell@arm.com 12813169Smatt.horsnell@arm.com table_sets = Param.Int(16, "Number of sets in PC lookup table") 12913169Smatt.horsnell@arm.com table_assoc = Param.Int(4, "Associativity of PC lookup table") 13013169Smatt.horsnell@arm.com use_master_id = Param.Bool(True, "Use master id based history") 13113169Smatt.horsnell@arm.com 13213169Smatt.horsnell@arm.com degree = Param.Int(4, "Number of prefetches to generate") 13313169Smatt.horsnell@arm.com 13413169Smatt.horsnell@arm.com # Get replacement policy 13513169Smatt.horsnell@arm.com replacement_policy = Param.BaseReplacementPolicy(RandomRP(), 13613169Smatt.horsnell@arm.com "Replacement policy") 13713169Smatt.horsnell@arm.com 13813169Smatt.horsnell@arm.comclass TaggedPrefetcher(QueuedPrefetcher): 13913169Smatt.horsnell@arm.com type = 'TaggedPrefetcher' 14013169Smatt.horsnell@arm.com cxx_class = 'TaggedPrefetcher' 14113169Smatt.horsnell@arm.com cxx_header = "mem/cache/prefetch/tagged.hh" 14213169Smatt.horsnell@arm.com 14313169Smatt.horsnell@arm.com degree = Param.Int(2, "Number of prefetches to generate") 14413169Smatt.horsnell@arm.com 14513169Smatt.horsnell@arm.comclass SignaturePathPrefetcher(QueuedPrefetcher): 14613169Smatt.horsnell@arm.com type = 'SignaturePathPrefetcher' 14713169Smatt.horsnell@arm.com cxx_class = 'SignaturePathPrefetcher' 14813169Smatt.horsnell@arm.com cxx_header = "mem/cache/prefetch/signature_path.hh" 14913169Smatt.horsnell@arm.com 15013169Smatt.horsnell@arm.com signature_shift = Param.UInt8(3, 15113169Smatt.horsnell@arm.com "Number of bits to shift when calculating a new signature"); 15213169Smatt.horsnell@arm.com signature_bits = Param.UInt16(12, 15313169Smatt.horsnell@arm.com "Size of the signature, in bits"); 15413169Smatt.horsnell@arm.com signature_table_entries = Param.MemorySize("1024", 15513169Smatt.horsnell@arm.com "Number of entries of the signature table") 15613169Smatt.horsnell@arm.com signature_table_assoc = Param.Unsigned(2, 15713169Smatt.horsnell@arm.com "Associativity of the signature table") 15813169Smatt.horsnell@arm.com signature_table_indexing_policy = Param.BaseIndexingPolicy( 15913169Smatt.horsnell@arm.com SetAssociative(entry_size = 1, assoc = Parent.signature_table_assoc, 16013169Smatt.horsnell@arm.com size = Parent.signature_table_entries), 16113169Smatt.horsnell@arm.com "Indexing policy of the signature table") 16213169Smatt.horsnell@arm.com signature_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(), 16313169Smatt.horsnell@arm.com "Replacement policy of the signature table") 16413169Smatt.horsnell@arm.com 16513169Smatt.horsnell@arm.com max_counter_value = Param.UInt8(7, "Maximum pattern counter value") 16613169Smatt.horsnell@arm.com pattern_table_entries = Param.MemorySize("4096", 16713169Smatt.horsnell@arm.com "Number of entries of the pattern table") 16813169Smatt.horsnell@arm.com pattern_table_assoc = Param.Unsigned(1, 16913169Smatt.horsnell@arm.com "Associativity of the pattern table") 17013169Smatt.horsnell@arm.com strides_per_pattern_entry = Param.Unsigned(4, 17113169Smatt.horsnell@arm.com "Number of strides stored in each pattern entry") 17213169Smatt.horsnell@arm.com pattern_table_indexing_policy = Param.BaseIndexingPolicy( 17313169Smatt.horsnell@arm.com SetAssociative(entry_size = 1, assoc = Parent.pattern_table_assoc, 17413169Smatt.horsnell@arm.com size = Parent.pattern_table_entries), 17513169Smatt.horsnell@arm.com "Indexing policy of the pattern table") 17613169Smatt.horsnell@arm.com pattern_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(), 17713169Smatt.horsnell@arm.com "Replacement policy of the pattern table") 17813169Smatt.horsnell@arm.com 17913169Smatt.horsnell@arm.com prefetch_confidence_threshold = Param.Float(0.5, 18013169Smatt.horsnell@arm.com "Minimum confidence to issue prefetches") 18113169Smatt.horsnell@arm.com lookahead_confidence_threshold = Param.Float(0.75, 18213169Smatt.horsnell@arm.com "Minimum confidence to continue exploring lookahead entries") 18313169Smatt.horsnell@arm.com 18413169Smatt.horsnell@arm.comclass SignaturePathPrefetcherV2(SignaturePathPrefetcher): 18513169Smatt.horsnell@arm.com type = 'SignaturePathPrefetcherV2' 18613169Smatt.horsnell@arm.com cxx_class = 'SignaturePathPrefetcherV2' 18713169Smatt.horsnell@arm.com cxx_header = "mem/cache/prefetch/signature_path_v2.hh" 18813169Smatt.horsnell@arm.com 18913169Smatt.horsnell@arm.com signature_table_entries = "256" 19013169Smatt.horsnell@arm.com signature_table_assoc = 1 19113169Smatt.horsnell@arm.com pattern_table_entries = "512" 19213169Smatt.horsnell@arm.com pattern_table_assoc = 1 19313169Smatt.horsnell@arm.com max_counter_value = 15 19413169Smatt.horsnell@arm.com prefetch_confidence_threshold = 0.25 19513169Smatt.horsnell@arm.com lookahead_confidence_threshold = 0.25 19613169Smatt.horsnell@arm.com 19713169Smatt.horsnell@arm.com global_history_register_entries = Param.MemorySize("8", 19813169Smatt.horsnell@arm.com "Number of entries of global history register") 19913169Smatt.horsnell@arm.com global_history_register_indexing_policy = Param.BaseIndexingPolicy( 20013169Smatt.horsnell@arm.com SetAssociative(entry_size = 1, 20113169Smatt.horsnell@arm.com assoc = Parent.global_history_register_entries, 20213169Smatt.horsnell@arm.com size = Parent.global_history_register_entries), 20313169Smatt.horsnell@arm.com "Indexing policy of the global history register") 20413169Smatt.horsnell@arm.com global_history_register_replacement_policy = Param.BaseReplacementPolicy( 20513169Smatt.horsnell@arm.com LRURP(), "Replacement policy of the global history register") 20613169Smatt.horsnell@arm.com 20713169Smatt.horsnell@arm.comclass AccessMapPatternMatching(ClockedObject): 20813169Smatt.horsnell@arm.com type = 'AccessMapPatternMatching' 20913169Smatt.horsnell@arm.com cxx_class = 'AccessMapPatternMatching' 21013169Smatt.horsnell@arm.com cxx_header = "mem/cache/prefetch/access_map_pattern_matching.hh" 21113169Smatt.horsnell@arm.com 21213169Smatt.horsnell@arm.com block_size = Param.Unsigned(Parent.block_size, 21313169Smatt.horsnell@arm.com "Cacheline size used by the prefetcher using this object") 21413169Smatt.horsnell@arm.com 21513169Smatt.horsnell@arm.com limit_stride = Param.Unsigned(0, 21613169Smatt.horsnell@arm.com "Limit the strides checked up to -X/X, if 0, disable the limit") 21713169Smatt.horsnell@arm.com start_degree = Param.Unsigned(4, 21813169Smatt.horsnell@arm.com "Initial degree (Maximum number of prefetches generated") 21913169Smatt.horsnell@arm.com hot_zone_size = Param.MemorySize("2kB", "Memory covered by a hot zone") 22013169Smatt.horsnell@arm.com access_map_table_entries = Param.MemorySize("256", 22113169Smatt.horsnell@arm.com "Number of entries in the access map table") 22213169Smatt.horsnell@arm.com access_map_table_assoc = Param.Unsigned(8, 22313169Smatt.horsnell@arm.com "Associativity of the access map table") 22413169Smatt.horsnell@arm.com access_map_table_indexing_policy = Param.BaseIndexingPolicy( 22513169Smatt.horsnell@arm.com SetAssociative(entry_size = 1, assoc = Parent.access_map_table_assoc, 22613169Smatt.horsnell@arm.com size = Parent.access_map_table_entries), 22713169Smatt.horsnell@arm.com "Indexing policy of the access map table") 22813169Smatt.horsnell@arm.com access_map_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(), 22913169Smatt.horsnell@arm.com "Replacement policy of the access map table") 23013169Smatt.horsnell@arm.com high_coverage_threshold = Param.Float(0.25, 23113169Smatt.horsnell@arm.com "A prefetch coverage factor bigger than this is considered high") 23213169Smatt.horsnell@arm.com low_coverage_threshold = Param.Float(0.125, 23313169Smatt.horsnell@arm.com "A prefetch coverage factor smaller than this is considered low") 23413169Smatt.horsnell@arm.com high_accuracy_threshold = Param.Float(0.5, 23513169Smatt.horsnell@arm.com "A prefetch accuracy factor bigger than this is considered high") 23613169Smatt.horsnell@arm.com low_accuracy_threshold = Param.Float(0.25, 23713169Smatt.horsnell@arm.com "A prefetch accuracy factor smaller than this is considered low") 23813169Smatt.horsnell@arm.com high_cache_hit_threshold = Param.Float(0.875, 23913169Smatt.horsnell@arm.com "A cache hit ratio bigger than this is considered high") 24013169Smatt.horsnell@arm.com low_cache_hit_threshold = Param.Float(0.75, 24113169Smatt.horsnell@arm.com "A cache hit ratio smaller than this is considered low") 24213169Smatt.horsnell@arm.com epoch_cycles = Param.Cycles(256000, "Cycles in an epoch period") 24313169Smatt.horsnell@arm.com offchip_memory_latency = Param.Latency("30ns", 24413169Smatt.horsnell@arm.com "Memory latency used to compute the required memory bandwidth") 24513169Smatt.horsnell@arm.com 24613169Smatt.horsnell@arm.comclass AMPMPrefetcher(QueuedPrefetcher): 24713169Smatt.horsnell@arm.com type = 'AMPMPrefetcher' 24813169Smatt.horsnell@arm.com cxx_class = 'AMPMPrefetcher' 24913169Smatt.horsnell@arm.com cxx_header = "mem/cache/prefetch/access_map_pattern_matching.hh" 25013169Smatt.horsnell@arm.com ampm = Param.AccessMapPatternMatching( AccessMapPatternMatching(), 25113169Smatt.horsnell@arm.com "Access Map Pattern Matching object") 25213169Smatt.horsnell@arm.com 25313169Smatt.horsnell@arm.comclass DeltaCorrelatingPredictionTables(SimObject): 25413169Smatt.horsnell@arm.com type = 'DeltaCorrelatingPredictionTables' 25513169Smatt.horsnell@arm.com cxx_class = 'DeltaCorrelatingPredictionTables' 25613169Smatt.horsnell@arm.com cxx_header = "mem/cache/prefetch/delta_correlating_prediction_tables.hh" 25713169Smatt.horsnell@arm.com deltas_per_entry = Param.Unsigned(20, 25813169Smatt.horsnell@arm.com "Number of deltas stored in each table entry") 25913169Smatt.horsnell@arm.com delta_bits = Param.Unsigned(12, "Bits per delta") 26013169Smatt.horsnell@arm.com delta_mask_bits = Param.Unsigned(8, 26113169Smatt.horsnell@arm.com "Lower bits to mask when comparing deltas") 26213169Smatt.horsnell@arm.com table_entries = Param.MemorySize("128", 26313169Smatt.horsnell@arm.com "Number of entries in the table") 26413169Smatt.horsnell@arm.com table_assoc = Param.Unsigned(128, 26513169Smatt.horsnell@arm.com "Associativity of the table") 26613169Smatt.horsnell@arm.com table_indexing_policy = Param.BaseIndexingPolicy( 26713169Smatt.horsnell@arm.com SetAssociative(entry_size = 1, assoc = Parent.table_assoc, 26813169Smatt.horsnell@arm.com size = Parent.table_entries), 26913169Smatt.horsnell@arm.com "Indexing policy of the table") 27013169Smatt.horsnell@arm.com table_replacement_policy = Param.BaseReplacementPolicy(LRURP(), 27113169Smatt.horsnell@arm.com "Replacement policy of the table") 27213169Smatt.horsnell@arm.com 27313169Smatt.horsnell@arm.comclass DCPTPrefetcher(QueuedPrefetcher): 27413169Smatt.horsnell@arm.com type = 'DCPTPrefetcher' 27513169Smatt.horsnell@arm.com cxx_class = 'DCPTPrefetcher' 27613169Smatt.horsnell@arm.com cxx_header = "mem/cache/prefetch/delta_correlating_prediction_tables.hh" 27713168Smatt.horsnell@arm.com dcpt = Param.DeltaCorrelatingPredictionTables( 27813168Smatt.horsnell@arm.com DeltaCorrelatingPredictionTables(), 27913168Smatt.horsnell@arm.com "Delta Correlating Prediction Tables object") 28013168Smatt.horsnell@arm.com 28113168Smatt.horsnell@arm.comclass IrregularStreamBufferPrefetcher(QueuedPrefetcher): 28213168Smatt.horsnell@arm.com type = "IrregularStreamBufferPrefetcher" 28313168Smatt.horsnell@arm.com cxx_class = "IrregularStreamBufferPrefetcher" 28413168Smatt.horsnell@arm.com cxx_header = "mem/cache/prefetch/irregular_stream_buffer.hh" 28513168Smatt.horsnell@arm.com 28613168Smatt.horsnell@arm.com max_counter_value = Param.Unsigned(3, 28713168Smatt.horsnell@arm.com "Maximum value of the confidence counter") 28813168Smatt.horsnell@arm.com chunk_size = Param.Unsigned(256, 28913168Smatt.horsnell@arm.com "Maximum number of addresses in a temporal stream") 29013168Smatt.horsnell@arm.com degree = Param.Unsigned(4, "Number of prefetches to generate") 29113168Smatt.horsnell@arm.com training_unit_assoc = Param.Unsigned(128, 29213168Smatt.horsnell@arm.com "Associativity of the training unit") 29313168Smatt.horsnell@arm.com training_unit_entries = Param.MemorySize("128", 29413168Smatt.horsnell@arm.com "Number of entries of the training unit") 29513168Smatt.horsnell@arm.com training_unit_indexing_policy = Param.BaseIndexingPolicy( 29613168Smatt.horsnell@arm.com SetAssociative(entry_size = 1, assoc = Parent.training_unit_assoc, 29713168Smatt.horsnell@arm.com size = Parent.training_unit_entries), 29813168Smatt.horsnell@arm.com "Indexing policy of the training unit") 29913168Smatt.horsnell@arm.com training_unit_replacement_policy = Param.BaseReplacementPolicy(LRURP(), 30013168Smatt.horsnell@arm.com "Replacement policy of the training unit") 30113168Smatt.horsnell@arm.com 30213168Smatt.horsnell@arm.com prefetch_candidates_per_entry = Param.Unsigned(16, 30313168Smatt.horsnell@arm.com "Number of prefetch candidates stored in a SP-AMC entry") 30413168Smatt.horsnell@arm.com address_map_cache_assoc = Param.Unsigned(128, 30513168Smatt.horsnell@arm.com "Associativity of the PS/SP AMCs") 30613168Smatt.horsnell@arm.com address_map_cache_entries = Param.MemorySize("128", 30713168Smatt.horsnell@arm.com "Number of entries of the PS/SP AMCs") 30813168Smatt.horsnell@arm.com ps_address_map_cache_indexing_policy = Param.BaseIndexingPolicy( 30913168Smatt.horsnell@arm.com SetAssociative(entry_size = 1, 31013168Smatt.horsnell@arm.com assoc = Parent.address_map_cache_assoc, 31113168Smatt.horsnell@arm.com size = Parent.address_map_cache_entries), 31213168Smatt.horsnell@arm.com "Indexing policy of the Physical-to-Structural Address Map Cache") 31313168Smatt.horsnell@arm.com ps_address_map_cache_replacement_policy = Param.BaseReplacementPolicy( 31413168Smatt.horsnell@arm.com LRURP(), 31513168Smatt.horsnell@arm.com "Replacement policy of the Physical-to-Structural Address Map Cache") 31613168Smatt.horsnell@arm.com sp_address_map_cache_indexing_policy = Param.BaseIndexingPolicy( 31713168Smatt.horsnell@arm.com SetAssociative(entry_size = 1, 31813168Smatt.horsnell@arm.com assoc = Parent.address_map_cache_assoc, 31913168Smatt.horsnell@arm.com size = Parent.address_map_cache_entries), 32013168Smatt.horsnell@arm.com "Indexing policy of the Structural-to-Physical Address Mao Cache") 32113168Smatt.horsnell@arm.com sp_address_map_cache_replacement_policy = Param.BaseReplacementPolicy( 32213168Smatt.horsnell@arm.com LRURP(), 32313168Smatt.horsnell@arm.com "Replacement policy of the Structural-to-Physical Address Map Cache") 32413168Smatt.horsnell@arm.com 32513168Smatt.horsnell@arm.comclass SlimAccessMapPatternMatching(AccessMapPatternMatching): 32613168Smatt.horsnell@arm.com start_degree = 2 32713168Smatt.horsnell@arm.com limit_stride = 4 32813168Smatt.horsnell@arm.com 32913168Smatt.horsnell@arm.comclass SlimDeltaCorrelatingPredictionTables(DeltaCorrelatingPredictionTables): 33013168Smatt.horsnell@arm.com table_entries = "256" 33113168Smatt.horsnell@arm.com table_assoc = 256 33213168Smatt.horsnell@arm.com deltas_per_entry = 9 33313168Smatt.horsnell@arm.com 33413168Smatt.horsnell@arm.comclass SlimAMPMPrefetcher(QueuedPrefetcher): 33513168Smatt.horsnell@arm.com type = 'SlimAMPMPrefetcher' 33613168Smatt.horsnell@arm.com cxx_class = 'SlimAMPMPrefetcher' 33713168Smatt.horsnell@arm.com cxx_header = "mem/cache/prefetch/slim_ampm.hh" 33813168Smatt.horsnell@arm.com 33913168Smatt.horsnell@arm.com ampm = Param.AccessMapPatternMatching(SlimAccessMapPatternMatching(), 34013168Smatt.horsnell@arm.com "Access Map Pattern Matching object") 34113168Smatt.horsnell@arm.com dcpt = Param.DeltaCorrelatingPredictionTables( 34213168Smatt.horsnell@arm.com SlimDeltaCorrelatingPredictionTables(), 34313168Smatt.horsnell@arm.com "Delta Correlating Prediction Tables object") 34413168Smatt.horsnell@arm.com 34513168Smatt.horsnell@arm.comclass BOPPrefetcher(QueuedPrefetcher): 34613168Smatt.horsnell@arm.com type = "BOPPrefetcher" 34713168Smatt.horsnell@arm.com cxx_class = "BOPPrefetcher" 34813168Smatt.horsnell@arm.com cxx_header = "mem/cache/prefetch/bop.hh" 34913168Smatt.horsnell@arm.com score_max = Param.Unsigned(31, "Max. score to update the best offset") 35013168Smatt.horsnell@arm.com round_max = Param.Unsigned(100, "Max. round to update the best offset") 35113168Smatt.horsnell@arm.com bad_score = Param.Unsigned(10, "Score at which the HWP is disabled") 35213168Smatt.horsnell@arm.com rr_size = Param.Unsigned(64, "Number of entries of each RR bank") 35313168Smatt.horsnell@arm.com tag_bits = Param.Unsigned(12, "Bits used to store the tag") 35413168Smatt.horsnell@arm.com offset_list_size = Param.Unsigned(46, 35513168Smatt.horsnell@arm.com "Number of entries in the offsets list") 35613168Smatt.horsnell@arm.com negative_offsets_enable = Param.Bool(True, 35713168Smatt.horsnell@arm.com "Initialize the offsets list also with negative values \ 35813168Smatt.horsnell@arm.com (i.e. the table will have half of the entries with positive \ 35913168Smatt.horsnell@arm.com offsets and the other half with negative ones)") 36013168Smatt.horsnell@arm.com delay_queue_enable = Param.Bool(True, "Enable the delay queue") 36113168Smatt.horsnell@arm.com delay_queue_size = Param.Unsigned(15, 36213168Smatt.horsnell@arm.com "Number of entries in the delay queue") 36313168Smatt.horsnell@arm.com delay_queue_cycles = Param.Cycles(60, 36413168Smatt.horsnell@arm.com "Cycles to delay a write in the left RR table from the delay \ 36513168Smatt.horsnell@arm.com queue") 36613168Smatt.horsnell@arm.com 36713168Smatt.horsnell@arm.comclass SBOOEPrefetcher(QueuedPrefetcher): 36813168Smatt.horsnell@arm.com type = 'SBOOEPrefetcher' 36913168Smatt.horsnell@arm.com cxx_class = 'SBOOEPrefetcher' 37013168Smatt.horsnell@arm.com cxx_header = "mem/cache/prefetch/sbooe.hh" 37113168Smatt.horsnell@arm.com latency_buffer_size = Param.Int(32, "Entries in the latency buffer") 37213168Smatt.horsnell@arm.com sequential_prefetchers = Param.Int(9, "Number of sequential prefetchers") 37313168Smatt.horsnell@arm.com sandbox_entries = Param.Int(1024, "Size of the address buffer") 37413168Smatt.horsnell@arm.com score_threshold_pct = Param.Percent(25, "Min. threshold to issue a \ 37513168Smatt.horsnell@arm.com prefetch. The value is the percentage of sandbox entries to use") 37613168Smatt.horsnell@arm.com