mshr.hh revision 4903
12SN/A/* 22188SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Erik Hallnor 292665SN/A */ 302665SN/A 312665SN/A/** 322SN/A * @file 332SN/A * Miss Status and Handling Register (MSHR) declaration. 342SN/A */ 352SN/A 362465SN/A#ifndef __MSHR_HH__ 371717SN/A#define __MSHR_HH__ 382683Sktlim@umich.edu 392680SN/A#include <list> 402SN/A 411858SN/A#include "mem/packet.hh" 423565Sgblack@eecs.umich.edu 431917SN/Aclass CacheBlk; 441070SN/Aclass MSHRQueue; 451917SN/A 462188SN/A/** 471917SN/A * Miss Status and handling Register. This class keeps all the information 482290SN/A * needed to handle a cache miss including a list of target requests. 491070SN/A */ 501917SN/Aclass MSHR : public Packet::SenderState 512170SN/A{ 522SN/A 53360SN/A public: 542519SN/A 552420SN/A class Target { 562SN/A public: 572SN/A Tick recvTime; //!< Time when request was received (for stats) 582SN/A Tick readyTime; //!< Time when request is ready to be serviced 592SN/A Counter order; //!< Global order (for memory consistency mgmt) 602SN/A PacketPtr pkt; //!< Pending request packet. 611858SN/A bool cpuSide; //!< Did request come from cpu side or mem side? 622683Sktlim@umich.edu 633453Sgblack@eecs.umich.edu bool isCpuSide() { return cpuSide; } 642683Sktlim@umich.edu 653402Sktlim@umich.edu Target(PacketPtr _pkt, Tick _readyTime, Counter _order, bool _cpuSide) 662683Sktlim@umich.edu : recvTime(curTick), readyTime(_readyTime), order(_order), 672521SN/A pkt(_pkt), cpuSide(_cpuSide) 682SN/A {} 692683Sktlim@umich.edu }; 702190SN/A 712680SN/A class TargetList : public std::list<Target> { 722290SN/A /** Target list iterator. */ 732526SN/A typedef std::list<Target>::iterator Iterator; 741917SN/A 751917SN/A public: 761982SN/A bool needsExclusive; 771917SN/A bool hasUpgrade; 782683Sktlim@umich.edu 792683Sktlim@umich.edu TargetList(); 801917SN/A void resetFlags() { needsExclusive = hasUpgrade = false; } 811917SN/A bool isReset() { return !needsExclusive && !hasUpgrade; } 821917SN/A void add(PacketPtr pkt, Tick readyTime, Counter order, bool cpuSide); 831917SN/A void replaceUpgrades(); 841917SN/A }; 851917SN/A 861917SN/A /** A list of MSHRs. */ 871917SN/A typedef std::list<MSHR *> List; 882521SN/A /** MSHR list iterator. */ 895482Snate@binkert.org typedef List::iterator Iterator; 903548Sgblack@eecs.umich.edu /** MSHR list const_iterator. */ 912SN/A typedef List::const_iterator ConstIterator; 922SN/A 934997Sgblack@eecs.umich.edu /** Pointer to queue containing this MSHR. */ 944997Sgblack@eecs.umich.edu MSHRQueue *queue; 953402Sktlim@umich.edu 964997Sgblack@eecs.umich.edu /** Cycle when ready to issue */ 972SN/A Tick readyTime; 982526SN/A 992683Sktlim@umich.edu /** Order number assigned by the miss queue. */ 1002SN/A Counter order; 1012190SN/A 1022862Sktlim@umich.edu /** Address of the request. */ 1032862Sktlim@umich.edu Addr addr; 1042864Sktlim@umich.edu 1052862Sktlim@umich.edu /** Size of the request. */ 1063402Sktlim@umich.edu int size; 1072862Sktlim@umich.edu 1083402Sktlim@umich.edu /** True if the request has been sent to the bus. */ 1092862Sktlim@umich.edu bool inService; 1102190SN/A 1112683Sktlim@umich.edu /** True if we will be putting the returned block in the cache */ 1122862Sktlim@umich.edu bool isCacheFill; 1132190SN/A 1142190SN/A /** True if we need to get an exclusive copy of the block. */ 1152683Sktlim@umich.edu bool needsExclusive() { return targets->needsExclusive; } 1161070SN/A 1173486Sktlim@umich.edu /** True if the request is uncacheable */ 1183486Sktlim@umich.edu bool _isUncacheable; 1193486Sktlim@umich.edu 1203486Sktlim@umich.edu bool pendingInvalidate; 1212680SN/A bool pendingShared; 1221070SN/A 1231070SN/A /** Thread number of the miss. */ 1241917SN/A short threadNum; 1252683Sktlim@umich.edu /** The number of currently allocated targets. */ 126180SN/A short ntargets; 127180SN/A 1281858SN/A 1292235SN/A /** Data buffer (if needed). Currently used only for pending 130180SN/A * upgrade handling. */ 1312235SN/A uint8_t *data; 132180SN/A 133180SN/A /** 1342862Sktlim@umich.edu * Pointer to this MSHR on the ready list. 1352862Sktlim@umich.edu * @sa MissQueue, MSHRQueue::readyList 1362313SN/A */ 1372313SN/A Iterator readyIter; 1382680SN/A 1392313SN/A /** 1402680SN/A * Pointer to this MSHR on the allocated list. 1412313SN/A * @sa MissQueue, MSHRQueue::allocatedList 1422313SN/A */ 1432680SN/A Iterator allocIter; 1442313SN/A 1452361SN/Aprivate: 1463548Sgblack@eecs.umich.edu /** List of all requests that match the address */ 1472361SN/A TargetList *targets; 1482361SN/A 1492361SN/A TargetList *deferredTargets; 1502235SN/A 151180SN/Apublic: 152180SN/A 153180SN/A bool isUncacheable() { return _isUncacheable; } 1542680SN/A 155180SN/A /** 156180SN/A * Allocate a miss to this MSHR. 1572SN/A * @param cmd The requesting command. 1582864Sktlim@umich.edu * @param addr The address of the miss. 1592864Sktlim@umich.edu * @param asid The address space id of the miss. 1602864Sktlim@umich.edu * @param size The number of bytes to request. 1612864Sktlim@umich.edu * @param pkt The original miss. 1622864Sktlim@umich.edu */ 1632864Sktlim@umich.edu void allocate(Addr addr, int size, PacketPtr pkt, 1642864Sktlim@umich.edu Tick when, Counter _order); 1652864Sktlim@umich.edu 1662864Sktlim@umich.edu /** 1673548Sgblack@eecs.umich.edu * Mark this MSHR as free. 1682864Sktlim@umich.edu */ 1692864Sktlim@umich.edu void deallocate(); 1702864Sktlim@umich.edu 1712864Sktlim@umich.edu /** 1722864Sktlim@umich.edu * Add a request to the list of targets. 1732864Sktlim@umich.edu * @param target The target. 1742864Sktlim@umich.edu */ 1752862Sktlim@umich.edu void allocateTarget(PacketPtr target, Tick when, Counter order); 1762862Sktlim@umich.edu bool handleSnoop(PacketPtr target, Counter order); 1772862Sktlim@umich.edu 1782862Sktlim@umich.edu /** A simple constructor. */ 1792862Sktlim@umich.edu MSHR(); 1802862Sktlim@umich.edu /** A simple destructor. */ 1812862Sktlim@umich.edu ~MSHR(); 1822862Sktlim@umich.edu 1832862Sktlim@umich.edu /** 1842915Sktlim@umich.edu * Returns the current number of allocated targets. 1852862Sktlim@umich.edu * @return The current number of allocated targets. 1862862Sktlim@umich.edu */ 1872862Sktlim@umich.edu int getNumTargets() { return ntargets; } 1882683Sktlim@umich.edu 189217SN/A /** 1902862Sktlim@umich.edu * Returns a pointer to the target list. 191223SN/A * @return a pointer to the target list. 192223SN/A */ 193217SN/A TargetList *getTargetList() { return targets; } 194217SN/A 195217SN/A /** 196217SN/A * Returns true if there are targets left. 1972683Sktlim@umich.edu * @return true if there are targets 198217SN/A */ 1992862Sktlim@umich.edu bool hasTargets() { return !targets->empty(); } 200237SN/A 201223SN/A /** 202217SN/A * Returns a reference to the first target. 203217SN/A * @return A pointer to the first target. 2042683Sktlim@umich.edu */ 2052683Sktlim@umich.edu Target *getTarget() { assert(hasTargets()); return &targets->front(); } 2062683Sktlim@umich.edu 2072683Sktlim@umich.edu /** 2082683Sktlim@umich.edu * Pop first target. 2092683Sktlim@umich.edu */ 2102683Sktlim@umich.edu void popTarget() 2112683Sktlim@umich.edu { 212217SN/A --ntargets; 213217SN/A targets->pop_front(); 2142683Sktlim@umich.edu } 2152SN/A 2162680SN/A bool isSimpleForward() 2172SN/A { 2182SN/A if (getNumTargets() != 1) 2192188SN/A return false; 2202188SN/A Target *tgt = getTarget(); 2214400Srdreslin@umich.edu return tgt->isCpuSide() && !tgt->pkt->needsResponse(); 2224400Srdreslin@umich.edu } 2234400Srdreslin@umich.edu 2244400Srdreslin@umich.edu bool promoteDeferredTargets(); 2252290SN/A 2262680SN/A void handleFill(Packet *pkt, CacheBlk *blk); 2272290SN/A 2282290SN/A /** 2292683Sktlim@umich.edu * Prints the contents of this MSHR to stderr. 230393SN/A */ 231393SN/A void dump(); 232393SN/A}; 2332683Sktlim@umich.edu 234393SN/A#endif //__MSHR_HH__ 2352680SN/A