mshr.hh revision 4903 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 */
30
31/**
32 * @file
33 * Miss Status and Handling Register (MSHR) declaration.
34 */
35
36#ifndef __MSHR_HH__
37#define __MSHR_HH__
38
39#include <list>
40
41#include "mem/packet.hh"
42
43class CacheBlk;
44class MSHRQueue;
45
46/**
47 * Miss Status and handling Register. This class keeps all the information
48 * needed to handle a cache miss including a list of target requests.
49 */
50class MSHR : public Packet::SenderState
51{
52
53  public:
54
55    class Target {
56      public:
57        Tick recvTime;  //!< Time when request was received (for stats)
58        Tick readyTime; //!< Time when request is ready to be serviced
59        Counter order;  //!< Global order (for memory consistency mgmt)
60        PacketPtr pkt;  //!< Pending request packet.
61        bool cpuSide;   //!< Did request come from cpu side or mem side?
62
63        bool isCpuSide() { return cpuSide; }
64
65        Target(PacketPtr _pkt, Tick _readyTime, Counter _order, bool _cpuSide)
66            : recvTime(curTick), readyTime(_readyTime), order(_order),
67              pkt(_pkt), cpuSide(_cpuSide)
68        {}
69    };
70
71    class TargetList : public std::list<Target> {
72        /** Target list iterator. */
73        typedef std::list<Target>::iterator Iterator;
74
75      public:
76        bool needsExclusive;
77        bool hasUpgrade;
78
79        TargetList();
80        void resetFlags() { needsExclusive = hasUpgrade = false; }
81        bool isReset()    { return !needsExclusive && !hasUpgrade; }
82        void add(PacketPtr pkt, Tick readyTime, Counter order, bool cpuSide);
83        void replaceUpgrades();
84    };
85
86    /** A list of MSHRs. */
87    typedef std::list<MSHR *> List;
88    /** MSHR list iterator. */
89    typedef List::iterator Iterator;
90    /** MSHR list const_iterator. */
91    typedef List::const_iterator ConstIterator;
92
93    /** Pointer to queue containing this MSHR. */
94    MSHRQueue *queue;
95
96    /** Cycle when ready to issue */
97    Tick readyTime;
98
99    /** Order number assigned by the miss queue. */
100    Counter order;
101
102    /** Address of the request. */
103    Addr addr;
104
105    /** Size of the request. */
106    int size;
107
108    /** True if the request has been sent to the bus. */
109    bool inService;
110
111    /** True if we will be putting the returned block in the cache */
112    bool isCacheFill;
113
114    /** True if we need to get an exclusive copy of the block. */
115    bool needsExclusive() { return targets->needsExclusive; }
116
117    /** True if the request is uncacheable */
118    bool _isUncacheable;
119
120    bool pendingInvalidate;
121    bool pendingShared;
122
123    /** Thread number of the miss. */
124    short threadNum;
125    /** The number of currently allocated targets. */
126    short ntargets;
127
128
129    /** Data buffer (if needed).  Currently used only for pending
130     * upgrade handling. */
131    uint8_t *data;
132
133    /**
134     * Pointer to this MSHR on the ready list.
135     * @sa MissQueue, MSHRQueue::readyList
136     */
137    Iterator readyIter;
138
139    /**
140     * Pointer to this MSHR on the allocated list.
141     * @sa MissQueue, MSHRQueue::allocatedList
142     */
143    Iterator allocIter;
144
145private:
146    /** List of all requests that match the address */
147    TargetList *targets;
148
149    TargetList *deferredTargets;
150
151public:
152
153    bool isUncacheable() { return _isUncacheable; }
154
155    /**
156     * Allocate a miss to this MSHR.
157     * @param cmd The requesting command.
158     * @param addr The address of the miss.
159     * @param asid The address space id of the miss.
160     * @param size The number of bytes to request.
161     * @param pkt  The original miss.
162     */
163    void allocate(Addr addr, int size, PacketPtr pkt,
164                  Tick when, Counter _order);
165
166    /**
167     * Mark this MSHR as free.
168     */
169    void deallocate();
170
171    /**
172     * Add a request to the list of targets.
173     * @param target The target.
174     */
175    void allocateTarget(PacketPtr target, Tick when, Counter order);
176    bool handleSnoop(PacketPtr target, Counter order);
177
178    /** A simple constructor. */
179    MSHR();
180    /** A simple destructor. */
181    ~MSHR();
182
183    /**
184     * Returns the current number of allocated targets.
185     * @return The current number of allocated targets.
186     */
187    int getNumTargets() { return ntargets; }
188
189    /**
190     * Returns a pointer to the target list.
191     * @return a pointer to the target list.
192     */
193    TargetList *getTargetList() { return targets; }
194
195    /**
196     * Returns true if there are targets left.
197     * @return true if there are targets
198     */
199    bool hasTargets() { return !targets->empty(); }
200
201    /**
202     * Returns a reference to the first target.
203     * @return A pointer to the first target.
204     */
205    Target *getTarget() { assert(hasTargets());  return &targets->front(); }
206
207    /**
208     * Pop first target.
209     */
210    void popTarget()
211    {
212        --ntargets;
213        targets->pop_front();
214    }
215
216    bool isSimpleForward()
217    {
218        if (getNumTargets() != 1)
219            return false;
220        Target *tgt = getTarget();
221        return tgt->isCpuSide() && !tgt->pkt->needsResponse();
222    }
223
224    bool promoteDeferredTargets();
225
226    void handleFill(Packet *pkt, CacheBlk *blk);
227
228    /**
229     * Prints the contents of this MSHR to stderr.
230     */
231    void dump();
232};
233
234#endif //__MSHR_HH__
235