mshr.cc revision 10028:fb8c44de891a
17585SAli.Saidi@arm.com/*
27585SAli.Saidi@arm.com * Copyright (c) 2012-2013 ARM Limited
37585SAli.Saidi@arm.com * All rights reserved.
47585SAli.Saidi@arm.com *
57585SAli.Saidi@arm.com * The license below extends only to copyright in the software and shall
67585SAli.Saidi@arm.com * not be construed as granting a license to any other intellectual
77585SAli.Saidi@arm.com * property including but not limited to intellectual property relating
87585SAli.Saidi@arm.com * to a hardware implementation of the functionality of the software
97585SAli.Saidi@arm.com * licensed hereunder.  You may use the software subject to the license
107585SAli.Saidi@arm.com * terms below provided that you ensure that this notice is replicated
117585SAli.Saidi@arm.com * unmodified and in its entirety in all distributions of the software,
127585SAli.Saidi@arm.com * modified or unmodified, in source code or in binary form.
137585SAli.Saidi@arm.com *
147585SAli.Saidi@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan
157585SAli.Saidi@arm.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
167585SAli.Saidi@arm.com * All rights reserved.
177585SAli.Saidi@arm.com *
187585SAli.Saidi@arm.com * Redistribution and use in source and binary forms, with or without
197585SAli.Saidi@arm.com * modification, are permitted provided that the following conditions are
207585SAli.Saidi@arm.com * met: redistributions of source code must retain the above copyright
217585SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer;
227585SAli.Saidi@arm.com * redistributions in binary form must reproduce the above copyright
237585SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer in the
247585SAli.Saidi@arm.com * documentation and/or other materials provided with the distribution;
257585SAli.Saidi@arm.com * neither the name of the copyright holders nor the names of its
267585SAli.Saidi@arm.com * contributors may be used to endorse or promote products derived from
277585SAli.Saidi@arm.com * this software without specific prior written permission.
287585SAli.Saidi@arm.com *
297585SAli.Saidi@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
307585SAli.Saidi@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
317585SAli.Saidi@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
327585SAli.Saidi@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
337585SAli.Saidi@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
347585SAli.Saidi@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
357585SAli.Saidi@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
367585SAli.Saidi@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
377585SAli.Saidi@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
387585SAli.Saidi@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
397585SAli.Saidi@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
407585SAli.Saidi@arm.com *
417585SAli.Saidi@arm.com * Authors: Erik Hallnor
427585SAli.Saidi@arm.com *          Dave Greene
437585SAli.Saidi@arm.com */
447585SAli.Saidi@arm.com
457585SAli.Saidi@arm.com/**
467723SAli.Saidi@ARM.com * @file
477585SAli.Saidi@arm.com * Miss Status and Handling Register (MSHR) definitions.
487585SAli.Saidi@arm.com */
497723SAli.Saidi@ARM.com
508143SAli.Saidi@ARM.com#include <algorithm>
517585SAli.Saidi@arm.com#include <cassert>
527585SAli.Saidi@arm.com#include <string>
537585SAli.Saidi@arm.com#include <vector>
548143SAli.Saidi@ARM.com
557585SAli.Saidi@arm.com#include "base/misc.hh"
567585SAli.Saidi@arm.com#include "base/types.hh"
577585SAli.Saidi@arm.com#include "debug/Cache.hh"
587585SAli.Saidi@arm.com#include "mem/cache/cache.hh"
597585SAli.Saidi@arm.com#include "mem/cache/mshr.hh"
607585SAli.Saidi@arm.com#include "sim/core.hh"
617585SAli.Saidi@arm.com
627585SAli.Saidi@arm.comusing namespace std;
637585SAli.Saidi@arm.com
647585SAli.Saidi@arm.comMSHR::MSHR() : readyTime(0), _isUncacheable(false), downstreamPending(false),
657585SAli.Saidi@arm.com               pendingDirty(false), postInvalidate(false),
667585SAli.Saidi@arm.com               postDowngrade(false), queue(NULL), order(0), addr(0), size(0),
677585SAli.Saidi@arm.com               isSecure(false), inService(false), isForward(false),
687585SAli.Saidi@arm.com               threadNum(InvalidThreadID), data(NULL)
697585SAli.Saidi@arm.com{
707585SAli.Saidi@arm.com}
717585SAli.Saidi@arm.com
727585SAli.Saidi@arm.com
737585SAli.Saidi@arm.comMSHR::TargetList::TargetList()
747585SAli.Saidi@arm.com    : needsExclusive(false), hasUpgrade(false)
757585SAli.Saidi@arm.com{}
767585SAli.Saidi@arm.com
777585SAli.Saidi@arm.com
787585SAli.Saidi@arm.cominline void
797585SAli.Saidi@arm.comMSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
807585SAli.Saidi@arm.com                      Counter order, Target::Source source, bool markPending)
817585SAli.Saidi@arm.com{
827585SAli.Saidi@arm.com    if (source != Target::FromSnoop) {
837585SAli.Saidi@arm.com        if (pkt->needsExclusive()) {
847585SAli.Saidi@arm.com            needsExclusive = true;
857585SAli.Saidi@arm.com        }
867585SAli.Saidi@arm.com
877585SAli.Saidi@arm.com        // StoreCondReq is effectively an upgrade if it's in an MSHR
887585SAli.Saidi@arm.com        // since it would have been failed already if we didn't have a
897585SAli.Saidi@arm.com        // read-only copy
907585SAli.Saidi@arm.com        if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
917585SAli.Saidi@arm.com            hasUpgrade = true;
927585SAli.Saidi@arm.com        }
937585SAli.Saidi@arm.com    }
947723SAli.Saidi@ARM.com
957585SAli.Saidi@arm.com    if (markPending) {
967585SAli.Saidi@arm.com        // Iterate over the SenderState stack and see if we find
977585SAli.Saidi@arm.com        // an MSHR entry. If we do, set the downstreamPending
987585SAli.Saidi@arm.com        // flag. Otherwise, do nothing.
997585SAli.Saidi@arm.com        MSHR *mshr = pkt->findNextSenderState<MSHR>();
1007585SAli.Saidi@arm.com        if (mshr != NULL) {
1018143SAli.Saidi@ARM.com            assert(!mshr->downstreamPending);
1028143SAli.Saidi@ARM.com            mshr->downstreamPending = true;
1038143SAli.Saidi@ARM.com        }
1048143SAli.Saidi@ARM.com    }
1058143SAli.Saidi@ARM.com
1068143SAli.Saidi@ARM.com    push_back(Target(pkt, readyTime, order, source, markPending));
1078143SAli.Saidi@ARM.com}
1088143SAli.Saidi@ARM.com
1098143SAli.Saidi@ARM.com
1108143SAli.Saidi@ARM.comstatic void
1118143SAli.Saidi@ARM.comreplaceUpgrade(PacketPtr pkt)
1128143SAli.Saidi@ARM.com{
1138143SAli.Saidi@ARM.com    if (pkt->cmd == MemCmd::UpgradeReq) {
1148143SAli.Saidi@ARM.com        pkt->cmd = MemCmd::ReadExReq;
1158143SAli.Saidi@ARM.com        DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
1168143SAli.Saidi@ARM.com    } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
1178143SAli.Saidi@ARM.com        pkt->cmd = MemCmd::SCUpgradeFailReq;
1188143SAli.Saidi@ARM.com        DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
1197585SAli.Saidi@arm.com    } else if (pkt->cmd == MemCmd::StoreCondReq) {
1207585SAli.Saidi@arm.com        pkt->cmd = MemCmd::StoreCondFailReq;
1217585SAli.Saidi@arm.com        DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
1227733SAli.Saidi@ARM.com    }
1237585SAli.Saidi@arm.com}
1247733SAli.Saidi@ARM.com
1257585SAli.Saidi@arm.com
1267585SAli.Saidi@arm.comvoid
1277585SAli.Saidi@arm.comMSHR::TargetList::replaceUpgrades()
1287720Sgblack@eecs.umich.edu{
1297585SAli.Saidi@arm.com    if (!hasUpgrade)
1307585SAli.Saidi@arm.com        return;
1317585SAli.Saidi@arm.com
1327585SAli.Saidi@arm.com    Iterator end_i = end();
1337585SAli.Saidi@arm.com    for (Iterator i = begin(); i != end_i; ++i) {
1347585SAli.Saidi@arm.com        replaceUpgrade(i->pkt);
1357585SAli.Saidi@arm.com    }
1367585SAli.Saidi@arm.com
1377585SAli.Saidi@arm.com    hasUpgrade = false;
1388143SAli.Saidi@ARM.com}
1398143SAli.Saidi@ARM.com
1408143SAli.Saidi@ARM.com
1418143SAli.Saidi@ARM.comvoid
1427585SAli.Saidi@arm.comMSHR::TargetList::clearDownstreamPending()
1437585SAli.Saidi@arm.com{
1447585SAli.Saidi@arm.com    Iterator end_i = end();
1457585SAli.Saidi@arm.com    for (Iterator i = begin(); i != end_i; ++i) {
1467585SAli.Saidi@arm.com        if (i->markedPending) {
1477585SAli.Saidi@arm.com            // Iterate over the SenderState stack and see if we find
1487585SAli.Saidi@arm.com            // an MSHR entry. If we find one, clear the
149            // downstreamPending flag by calling
150            // clearDownstreamPending(). This recursively clears the
151            // downstreamPending flag in all caches this packet has
152            // passed through.
153            MSHR *mshr = i->pkt->findNextSenderState<MSHR>();
154            if (mshr != NULL) {
155                mshr->clearDownstreamPending();
156            }
157        }
158    }
159}
160
161
162bool
163MSHR::TargetList::checkFunctional(PacketPtr pkt)
164{
165    Iterator end_i = end();
166    for (Iterator i = begin(); i != end_i; ++i) {
167        if (pkt->checkFunctional(i->pkt)) {
168            return true;
169        }
170    }
171
172    return false;
173}
174
175
176void
177MSHR::TargetList::
178print(std::ostream &os, int verbosity, const std::string &prefix) const
179{
180    ConstIterator end_i = end();
181    for (ConstIterator i = begin(); i != end_i; ++i) {
182        const char *s;
183        switch (i->source) {
184          case Target::FromCPU:
185            s = "FromCPU";
186            break;
187          case Target::FromSnoop:
188            s = "FromSnoop";
189            break;
190          case Target::FromPrefetcher:
191            s = "FromPrefetcher";
192            break;
193          default:
194            s = "";
195            break;
196        }
197        ccprintf(os, "%s%s: ", prefix, s);
198        i->pkt->print(os, verbosity, "");
199    }
200}
201
202
203void
204MSHR::allocate(Addr _addr, int _size, PacketPtr target, Tick whenReady,
205               Counter _order)
206{
207    addr = _addr;
208    size = _size;
209    isSecure = target->isSecure();
210    readyTime = whenReady;
211    order = _order;
212    assert(target);
213    isForward = false;
214    _isUncacheable = target->req->isUncacheable();
215    inService = false;
216    downstreamPending = false;
217    threadNum = 0;
218    assert(targets.isReset());
219    // Don't know of a case where we would allocate a new MSHR for a
220    // snoop (mem-side request), so set source according to request here
221    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
222        Target::FromPrefetcher : Target::FromCPU;
223    targets.add(target, whenReady, _order, source, true);
224    assert(deferredTargets.isReset());
225    data = NULL;
226}
227
228
229void
230MSHR::clearDownstreamPending()
231{
232    assert(downstreamPending);
233    downstreamPending = false;
234    // recursively clear flag on any MSHRs we will be forwarding
235    // responses to
236    targets.clearDownstreamPending();
237}
238
239bool
240MSHR::markInService(PacketPtr pkt)
241{
242    assert(!inService);
243    if (isForwardNoResponse()) {
244        // we just forwarded the request packet & don't expect a
245        // response, so get rid of it
246        assert(getNumTargets() == 1);
247        popTarget();
248        return true;
249    }
250    inService = true;
251    pendingDirty = (targets.needsExclusive ||
252                    (!pkt->sharedAsserted() && pkt->memInhibitAsserted()));
253    postInvalidate = postDowngrade = false;
254
255    if (!downstreamPending) {
256        // let upstream caches know that the request has made it to a
257        // level where it's going to get a response
258        targets.clearDownstreamPending();
259    }
260    return false;
261}
262
263
264void
265MSHR::deallocate()
266{
267    assert(targets.empty());
268    targets.resetFlags();
269    assert(deferredTargets.isReset());
270    inService = false;
271}
272
273/*
274 * Adds a target to an MSHR
275 */
276void
277MSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order)
278{
279    // if there's a request already in service for this MSHR, we will
280    // have to defer the new target until after the response if any of
281    // the following are true:
282    // - there are other targets already deferred
283    // - there's a pending invalidate to be applied after the response
284    //   comes back (but before this target is processed)
285    // - this target requires an exclusive block and either we're not
286    //   getting an exclusive block back or we have already snooped
287    //   another read request that will downgrade our exclusive block
288    //   to shared
289
290    // assume we'd never issue a prefetch when we've got an
291    // outstanding miss
292    assert(pkt->cmd != MemCmd::HardPFReq);
293
294    if (inService &&
295        (!deferredTargets.empty() || hasPostInvalidate() ||
296         (pkt->needsExclusive() &&
297          (!isPendingDirty() || hasPostDowngrade() || isForward)))) {
298        // need to put on deferred list
299        if (hasPostInvalidate())
300            replaceUpgrade(pkt);
301        deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true);
302    } else {
303        // No request outstanding, or still OK to append to
304        // outstanding request: append to regular target list.  Only
305        // mark pending if current request hasn't been issued yet
306        // (isn't in service).
307        targets.add(pkt, whenReady, _order, Target::FromCPU, !inService);
308    }
309}
310
311bool
312MSHR::handleSnoop(PacketPtr pkt, Counter _order)
313{
314    DPRINTF(Cache, "%s for %s address %x size %d\n", __func__,
315            pkt->cmdString(), pkt->getAddr(), pkt->getSize());
316    if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
317        // Request has not been issued yet, or it's been issued
318        // locally but is buffered unissued at some downstream cache
319        // which is forwarding us this snoop.  Either way, the packet
320        // we're snooping logically precedes this MSHR's request, so
321        // the snoop has no impact on the MSHR, but must be processed
322        // in the standard way by the cache.  The only exception is
323        // that if we're an L2+ cache buffering an UpgradeReq from a
324        // higher-level cache, and the snoop is invalidating, then our
325        // buffered upgrades must be converted to read exclusives,
326        // since the upper-level cache no longer has a valid copy.
327        // That is, even though the upper-level cache got out on its
328        // local bus first, some other invalidating transaction
329        // reached the global bus before the upgrade did.
330        if (pkt->needsExclusive()) {
331            targets.replaceUpgrades();
332            deferredTargets.replaceUpgrades();
333        }
334
335        return false;
336    }
337
338    // From here on down, the request issued by this MSHR logically
339    // precedes the request we're snooping.
340    if (pkt->needsExclusive()) {
341        // snooped request still precedes the re-request we'll have to
342        // issue for deferred targets, if any...
343        deferredTargets.replaceUpgrades();
344    }
345
346    if (hasPostInvalidate()) {
347        // a prior snoop has already appended an invalidation, so
348        // logically we don't have the block anymore; no need for
349        // further snooping.
350        return true;
351    }
352
353    if (isPendingDirty() || pkt->isInvalidate()) {
354        // We need to save and replay the packet in two cases:
355        // 1. We're awaiting an exclusive copy, so ownership is pending,
356        //    and we need to respond after we receive data.
357        // 2. It's an invalidation (e.g., UpgradeReq), and we need
358        //    to forward the snoop up the hierarchy after the current
359        //    transaction completes.
360
361        // Actual target device (typ. a memory) will delete the
362        // packet on reception, so we need to save a copy here.
363        PacketPtr cp_pkt = new Packet(pkt, true);
364        targets.add(cp_pkt, curTick(), _order, Target::FromSnoop,
365                     downstreamPending && targets.needsExclusive);
366
367        if (isPendingDirty()) {
368            pkt->assertMemInhibit();
369            pkt->setSupplyExclusive();
370        }
371
372        if (pkt->needsExclusive()) {
373            // This transaction will take away our pending copy
374            postInvalidate = true;
375        }
376    }
377
378    if (!pkt->needsExclusive()) {
379        // This transaction will get a read-shared copy, downgrading
380        // our copy if we had an exclusive one
381        postDowngrade = true;
382        pkt->assertShared();
383    }
384
385    return true;
386}
387
388
389bool
390MSHR::promoteDeferredTargets()
391{
392    assert(targets.empty());
393    if (deferredTargets.empty()) {
394        return false;
395    }
396
397    // swap targets & deferredTargets lists
398    std::swap(targets, deferredTargets);
399
400    // clear deferredTargets flags
401    deferredTargets.resetFlags();
402
403    order = targets.front().order;
404    readyTime = std::max(curTick(), targets.front().readyTime);
405
406    return true;
407}
408
409
410void
411MSHR::handleFill(Packet *pkt, CacheBlk *blk)
412{
413    if (!pkt->sharedAsserted()
414        && !(hasPostInvalidate() || hasPostDowngrade())
415        && deferredTargets.needsExclusive) {
416        // We got an exclusive response, but we have deferred targets
417        // which are waiting to request an exclusive copy (not because
418        // of a pending invalidate).  This can happen if the original
419        // request was for a read-only (non-exclusive) block, but we
420        // got an exclusive copy anyway because of the E part of the
421        // MOESI/MESI protocol.  Since we got the exclusive copy
422        // there's no need to defer the targets, so move them up to
423        // the regular target list.
424        assert(!targets.needsExclusive);
425        targets.needsExclusive = true;
426        // if any of the deferred targets were upper-level cache
427        // requests marked downstreamPending, need to clear that
428        assert(!downstreamPending);  // not pending here anymore
429        deferredTargets.clearDownstreamPending();
430        // this clears out deferredTargets too
431        targets.splice(targets.end(), deferredTargets);
432        deferredTargets.resetFlags();
433    }
434}
435
436
437bool
438MSHR::checkFunctional(PacketPtr pkt)
439{
440    // For printing, we treat the MSHR as a whole as single entity.
441    // For other requests, we iterate over the individual targets
442    // since that's where the actual data lies.
443    if (pkt->isPrint()) {
444        pkt->checkFunctional(this, addr, isSecure, size, NULL);
445        return false;
446    } else {
447        return (targets.checkFunctional(pkt) ||
448                deferredTargets.checkFunctional(pkt));
449    }
450}
451
452
453void
454MSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
455{
456    ccprintf(os, "%s[%x:%x](%s) %s %s %s state: %s %s %s %s %s\n",
457             prefix, addr, addr+size-1,
458             isSecure ? "s" : "ns",
459             isForward ? "Forward" : "",
460             isForwardNoResponse() ? "ForwNoResp" : "",
461             needsExclusive() ? "Excl" : "",
462             _isUncacheable ? "Unc" : "",
463             inService ? "InSvc" : "",
464             downstreamPending ? "DwnPend" : "",
465             hasPostInvalidate() ? "PostInv" : "",
466             hasPostDowngrade() ? "PostDowngr" : "");
467
468    ccprintf(os, "%s  Targets:\n", prefix);
469    targets.print(os, verbosity, prefix + "    ");
470    if (!deferredTargets.empty()) {
471        ccprintf(os, "%s  Deferred Targets:\n", prefix);
472        deferredTargets.print(os, verbosity, prefix + "      ");
473    }
474}
475
476std::string
477MSHR::print() const
478{
479    ostringstream str;
480    print(str);
481    return str.str();
482}
483