mshr.cc revision 9725
13358Srdreslin@umich.edu/* 21693Sstever@eecs.umich.edu * Copyright (c) 2012 ARM Limited 31693Sstever@eecs.umich.edu * All rights reserved. 41693Sstever@eecs.umich.edu * 51693Sstever@eecs.umich.edu * The license below extends only to copyright in the software and shall 61693Sstever@eecs.umich.edu * not be construed as granting a license to any other intellectual 71693Sstever@eecs.umich.edu * property including but not limited to intellectual property relating 81693Sstever@eecs.umich.edu * to a hardware implementation of the functionality of the software 91693Sstever@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 101693Sstever@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 111693Sstever@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 121693Sstever@eecs.umich.edu * modified or unmodified, in source code or in binary form. 131693Sstever@eecs.umich.edu * 141693Sstever@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 151693Sstever@eecs.umich.edu * Copyright (c) 2010 Advanced Micro Devices, Inc. 161693Sstever@eecs.umich.edu * All rights reserved. 171693Sstever@eecs.umich.edu * 181693Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 191693Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 201693Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 211693Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 221693Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 231693Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 241693Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 251693Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 261693Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 271693Sstever@eecs.umich.edu * this software without specific prior written permission. 281693Sstever@eecs.umich.edu * 293358Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 303358Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311516SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 323358Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 333358Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 343358Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 353358Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361516SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 373358Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 383358Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 393358Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 403358Srdreslin@umich.edu * 413358Srdreslin@umich.edu * Authors: Erik Hallnor 423358Srdreslin@umich.edu * Dave Greene 433358Srdreslin@umich.edu */ 443358Srdreslin@umich.edu 453358Srdreslin@umich.edu/** 463358Srdreslin@umich.edu * @file 473358Srdreslin@umich.edu * Miss Status and Handling Register (MSHR) definitions. 483358Srdreslin@umich.edu */ 493358Srdreslin@umich.edu 503358Srdreslin@umich.edu#include <algorithm> 513358Srdreslin@umich.edu#include <cassert> 523358Srdreslin@umich.edu#include <string> 533358Srdreslin@umich.edu#include <vector> 543358Srdreslin@umich.edu 553358Srdreslin@umich.edu#include "base/misc.hh" 563358Srdreslin@umich.edu#include "base/types.hh" 573358Srdreslin@umich.edu#include "debug/Cache.hh" 583358Srdreslin@umich.edu#include "mem/cache/cache.hh" 593358Srdreslin@umich.edu#include "mem/cache/mshr.hh" 603358Srdreslin@umich.edu#include "sim/core.hh" 613358Srdreslin@umich.edu 623358Srdreslin@umich.eduusing namespace std; 633358Srdreslin@umich.edu 643358Srdreslin@umich.eduMSHR::MSHR() : readyTime(0), _isUncacheable(false), downstreamPending(false), 653358Srdreslin@umich.edu pendingDirty(false), postInvalidate(false), 663358Srdreslin@umich.edu postDowngrade(false), queue(NULL), order(0), addr(0), size(0), 673358Srdreslin@umich.edu inService(false), isForward(false), threadNum(InvalidThreadID), 683358Srdreslin@umich.edu data(NULL) 693358Srdreslin@umich.edu{ 703358Srdreslin@umich.edu} 713358Srdreslin@umich.edu 723358Srdreslin@umich.edu 733358Srdreslin@umich.eduMSHR::TargetList::TargetList() 743358Srdreslin@umich.edu : needsExclusive(false), hasUpgrade(false) 753358Srdreslin@umich.edu{} 763358Srdreslin@umich.edu 773358Srdreslin@umich.edu 783358Srdreslin@umich.eduinline void 793358Srdreslin@umich.eduMSHR::TargetList::add(PacketPtr pkt, Tick readyTime, 803358Srdreslin@umich.edu Counter order, Target::Source source, bool markPending) 813358Srdreslin@umich.edu{ 823358Srdreslin@umich.edu if (source != Target::FromSnoop) { 833358Srdreslin@umich.edu if (pkt->needsExclusive()) { 843358Srdreslin@umich.edu needsExclusive = true; 853358Srdreslin@umich.edu } 863358Srdreslin@umich.edu 873358Srdreslin@umich.edu // StoreCondReq is effectively an upgrade if it's in an MSHR 883358Srdreslin@umich.edu // since it would have been failed already if we didn't have a 893358Srdreslin@umich.edu // read-only copy 903358Srdreslin@umich.edu if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) { 913358Srdreslin@umich.edu hasUpgrade = true; 923358Srdreslin@umich.edu } 933358Srdreslin@umich.edu } 943358Srdreslin@umich.edu 953358Srdreslin@umich.edu if (markPending) { 963358Srdreslin@umich.edu // Iterate over the SenderState stack and see if we find 973358Srdreslin@umich.edu // an MSHR entry. If we do, set the downstreamPending 983358Srdreslin@umich.edu // flag. Otherwise, do nothing. 993358Srdreslin@umich.edu MSHR *mshr = pkt->findNextSenderState<MSHR>(); 1003358Srdreslin@umich.edu if (mshr != NULL) { 1013358Srdreslin@umich.edu assert(!mshr->downstreamPending); 1023358Srdreslin@umich.edu mshr->downstreamPending = true; 1033358Srdreslin@umich.edu } 1043358Srdreslin@umich.edu } 1053358Srdreslin@umich.edu 1063358Srdreslin@umich.edu push_back(Target(pkt, readyTime, order, source, markPending)); 1073358Srdreslin@umich.edu} 1083358Srdreslin@umich.edu 1093358Srdreslin@umich.edu 1103358Srdreslin@umich.edustatic void 1113358Srdreslin@umich.edureplaceUpgrade(PacketPtr pkt) 1123358Srdreslin@umich.edu{ 1133358Srdreslin@umich.edu if (pkt->cmd == MemCmd::UpgradeReq) { 1143358Srdreslin@umich.edu pkt->cmd = MemCmd::ReadExReq; 1153358Srdreslin@umich.edu DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n"); 1163358Srdreslin@umich.edu } else if (pkt->cmd == MemCmd::SCUpgradeReq) { 1173358Srdreslin@umich.edu pkt->cmd = MemCmd::SCUpgradeFailReq; 1183358Srdreslin@umich.edu DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n"); 1193358Srdreslin@umich.edu } else if (pkt->cmd == MemCmd::StoreCondReq) { 1203358Srdreslin@umich.edu pkt->cmd = MemCmd::StoreCondFailReq; 1213358Srdreslin@umich.edu DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n"); 1223358Srdreslin@umich.edu } 1233358Srdreslin@umich.edu} 1243358Srdreslin@umich.edu 1253358Srdreslin@umich.edu 1263358Srdreslin@umich.eduvoid 1273358Srdreslin@umich.eduMSHR::TargetList::replaceUpgrades() 1283358Srdreslin@umich.edu{ 1293358Srdreslin@umich.edu if (!hasUpgrade) 1303358Srdreslin@umich.edu return; 1313358Srdreslin@umich.edu 1323358Srdreslin@umich.edu Iterator end_i = end(); 1333358Srdreslin@umich.edu for (Iterator i = begin(); i != end_i; ++i) { 1343358Srdreslin@umich.edu replaceUpgrade(i->pkt); 1353358Srdreslin@umich.edu } 1363358Srdreslin@umich.edu 1373358Srdreslin@umich.edu hasUpgrade = false; 1383358Srdreslin@umich.edu} 1393358Srdreslin@umich.edu 1403358Srdreslin@umich.edu 1413358Srdreslin@umich.eduvoid 1423358Srdreslin@umich.eduMSHR::TargetList::clearDownstreamPending() 1433358Srdreslin@umich.edu{ 1443358Srdreslin@umich.edu Iterator end_i = end(); 1453358Srdreslin@umich.edu for (Iterator i = begin(); i != end_i; ++i) { 1463358Srdreslin@umich.edu if (i->markedPending) { 1473358Srdreslin@umich.edu // Iterate over the SenderState stack and see if we find 1483358Srdreslin@umich.edu // an MSHR entry. If we find one, clear the 1493358Srdreslin@umich.edu // downstreamPending flag by calling 1503358Srdreslin@umich.edu // clearDownstreamPending(). This recursively clears the 1513358Srdreslin@umich.edu // downstreamPending flag in all caches this packet has 1523358Srdreslin@umich.edu // passed through. 1533358Srdreslin@umich.edu MSHR *mshr = i->pkt->findNextSenderState<MSHR>(); 1543358Srdreslin@umich.edu if (mshr != NULL) { 1553358Srdreslin@umich.edu mshr->clearDownstreamPending(); 1563358Srdreslin@umich.edu } 1573358Srdreslin@umich.edu } 1583358Srdreslin@umich.edu } 1593358Srdreslin@umich.edu} 1603358Srdreslin@umich.edu 1613358Srdreslin@umich.edu 1623358Srdreslin@umich.edubool 1631516SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt) 1643358Srdreslin@umich.edu{ 1653358Srdreslin@umich.edu Iterator end_i = end(); 1663358Srdreslin@umich.edu for (Iterator i = begin(); i != end_i; ++i) { 1671516SN/A if (pkt->checkFunctional(i->pkt)) { 1683358Srdreslin@umich.edu return true; 1693358Srdreslin@umich.edu } 1703358Srdreslin@umich.edu } 1713358Srdreslin@umich.edu 1723358Srdreslin@umich.edu return false; 1731516SN/A} 1743358Srdreslin@umich.edu 1753358Srdreslin@umich.edu 1763358Srdreslin@umich.eduvoid 1773358Srdreslin@umich.eduMSHR::TargetList:: 1783358Srdreslin@umich.eduprint(std::ostream &os, int verbosity, const std::string &prefix) const 1793358Srdreslin@umich.edu{ 1803358Srdreslin@umich.edu ConstIterator end_i = end(); 1813358Srdreslin@umich.edu for (ConstIterator i = begin(); i != end_i; ++i) { 1823358Srdreslin@umich.edu const char *s; 1833358Srdreslin@umich.edu switch (i->source) { 1843358Srdreslin@umich.edu case Target::FromCPU: 1853358Srdreslin@umich.edu s = "FromCPU"; 1863358Srdreslin@umich.edu break; 1873358Srdreslin@umich.edu case Target::FromSnoop: 1883358Srdreslin@umich.edu s = "FromSnoop"; 1893358Srdreslin@umich.edu break; 1903358Srdreslin@umich.edu case Target::FromPrefetcher: 1913358Srdreslin@umich.edu s = "FromPrefetcher"; 1923358Srdreslin@umich.edu break; 1933358Srdreslin@umich.edu default: 1943358Srdreslin@umich.edu s = ""; 1953358Srdreslin@umich.edu break; 1963358Srdreslin@umich.edu } 1973358Srdreslin@umich.edu ccprintf(os, "%s%s: ", prefix, s); 1983358Srdreslin@umich.edu i->pkt->print(os, verbosity, ""); 1993358Srdreslin@umich.edu } 2003358Srdreslin@umich.edu} 2013358Srdreslin@umich.edu 2023358Srdreslin@umich.edu 2033358Srdreslin@umich.eduvoid 2043358Srdreslin@umich.eduMSHR::allocate(Addr _addr, int _size, PacketPtr target, 2053358Srdreslin@umich.edu Tick whenReady, Counter _order) 2063358Srdreslin@umich.edu{ 2073358Srdreslin@umich.edu addr = _addr; 2083358Srdreslin@umich.edu size = _size; 2093358Srdreslin@umich.edu readyTime = whenReady; 2103358Srdreslin@umich.edu order = _order; 2113358Srdreslin@umich.edu assert(target); 2123358Srdreslin@umich.edu isForward = false; 2133358Srdreslin@umich.edu _isUncacheable = target->req->isUncacheable(); 2143358Srdreslin@umich.edu inService = false; 2153358Srdreslin@umich.edu downstreamPending = false; 2163358Srdreslin@umich.edu threadNum = 0; 2173358Srdreslin@umich.edu assert(targets.isReset()); 2183358Srdreslin@umich.edu // Don't know of a case where we would allocate a new MSHR for a 2193358Srdreslin@umich.edu // snoop (mem-side request), so set source according to request here 2203358Srdreslin@umich.edu Target::Source source = (target->cmd == MemCmd::HardPFReq) ? 2213358Srdreslin@umich.edu Target::FromPrefetcher : Target::FromCPU; 2223358Srdreslin@umich.edu targets.add(target, whenReady, _order, source, true); 2233358Srdreslin@umich.edu assert(deferredTargets.isReset()); 2243358Srdreslin@umich.edu data = NULL; 2253358Srdreslin@umich.edu} 2263358Srdreslin@umich.edu 2273358Srdreslin@umich.edu 2283358Srdreslin@umich.eduvoid 2291516SN/AMSHR::clearDownstreamPending() 2303358Srdreslin@umich.edu{ 2311516SN/A assert(downstreamPending); 2321516SN/A downstreamPending = false; 2331516SN/A // recursively clear flag on any MSHRs we will be forwarding 2343358Srdreslin@umich.edu // responses to 2353358Srdreslin@umich.edu targets.clearDownstreamPending(); 2363358Srdreslin@umich.edu} 2373358Srdreslin@umich.edu 2383358Srdreslin@umich.edubool 2393358Srdreslin@umich.eduMSHR::markInService(PacketPtr pkt) 2403358Srdreslin@umich.edu{ 2413358Srdreslin@umich.edu assert(!inService); 2423358Srdreslin@umich.edu if (isForwardNoResponse()) { 2433358Srdreslin@umich.edu // we just forwarded the request packet & don't expect a 2443358Srdreslin@umich.edu // response, so get rid of it 2453358Srdreslin@umich.edu assert(getNumTargets() == 1); 2463358Srdreslin@umich.edu popTarget(); 2473358Srdreslin@umich.edu return true; 2483358Srdreslin@umich.edu } 2493358Srdreslin@umich.edu inService = true; 2503358Srdreslin@umich.edu pendingDirty = (targets.needsExclusive || 2513358Srdreslin@umich.edu (!pkt->sharedAsserted() && pkt->memInhibitAsserted())); 2523358Srdreslin@umich.edu postInvalidate = postDowngrade = false; 2533358Srdreslin@umich.edu 2543358Srdreslin@umich.edu if (!downstreamPending) { 2553358Srdreslin@umich.edu // let upstream caches know that the request has made it to a 2563358Srdreslin@umich.edu // level where it's going to get a response 2573358Srdreslin@umich.edu targets.clearDownstreamPending(); 2583358Srdreslin@umich.edu } 2593358Srdreslin@umich.edu return false; 260} 261 262 263void 264MSHR::deallocate() 265{ 266 assert(targets.empty()); 267 targets.resetFlags(); 268 assert(deferredTargets.isReset()); 269 inService = false; 270} 271 272/* 273 * Adds a target to an MSHR 274 */ 275void 276MSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order) 277{ 278 // if there's a request already in service for this MSHR, we will 279 // have to defer the new target until after the response if any of 280 // the following are true: 281 // - there are other targets already deferred 282 // - there's a pending invalidate to be applied after the response 283 // comes back (but before this target is processed) 284 // - this target requires an exclusive block and either we're not 285 // getting an exclusive block back or we have already snooped 286 // another read request that will downgrade our exclusive block 287 // to shared 288 289 // assume we'd never issue a prefetch when we've got an 290 // outstanding miss 291 assert(pkt->cmd != MemCmd::HardPFReq); 292 293 if (inService && 294 (!deferredTargets.empty() || hasPostInvalidate() || 295 (pkt->needsExclusive() && 296 (!isPendingDirty() || hasPostDowngrade() || isForward)))) { 297 // need to put on deferred list 298 if (hasPostInvalidate()) 299 replaceUpgrade(pkt); 300 deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true); 301 } else { 302 // No request outstanding, or still OK to append to 303 // outstanding request: append to regular target list. Only 304 // mark pending if current request hasn't been issued yet 305 // (isn't in service). 306 targets.add(pkt, whenReady, _order, Target::FromCPU, !inService); 307 } 308} 309 310bool 311MSHR::handleSnoop(PacketPtr pkt, Counter _order) 312{ 313 DPRINTF(Cache, "%s for %s address %x size %d\n", __func__, 314 pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 315 if (!inService || (pkt->isExpressSnoop() && downstreamPending)) { 316 // Request has not been issued yet, or it's been issued 317 // locally but is buffered unissued at some downstream cache 318 // which is forwarding us this snoop. Either way, the packet 319 // we're snooping logically precedes this MSHR's request, so 320 // the snoop has no impact on the MSHR, but must be processed 321 // in the standard way by the cache. The only exception is 322 // that if we're an L2+ cache buffering an UpgradeReq from a 323 // higher-level cache, and the snoop is invalidating, then our 324 // buffered upgrades must be converted to read exclusives, 325 // since the upper-level cache no longer has a valid copy. 326 // That is, even though the upper-level cache got out on its 327 // local bus first, some other invalidating transaction 328 // reached the global bus before the upgrade did. 329 if (pkt->needsExclusive()) { 330 targets.replaceUpgrades(); 331 deferredTargets.replaceUpgrades(); 332 } 333 334 return false; 335 } 336 337 // From here on down, the request issued by this MSHR logically 338 // precedes the request we're snooping. 339 if (pkt->needsExclusive()) { 340 // snooped request still precedes the re-request we'll have to 341 // issue for deferred targets, if any... 342 deferredTargets.replaceUpgrades(); 343 } 344 345 if (hasPostInvalidate()) { 346 // a prior snoop has already appended an invalidation, so 347 // logically we don't have the block anymore; no need for 348 // further snooping. 349 return true; 350 } 351 352 if (isPendingDirty() || pkt->isInvalidate()) { 353 // We need to save and replay the packet in two cases: 354 // 1. We're awaiting an exclusive copy, so ownership is pending, 355 // and we need to respond after we receive data. 356 // 2. It's an invalidation (e.g., UpgradeReq), and we need 357 // to forward the snoop up the hierarchy after the current 358 // transaction completes. 359 360 // Actual target device (typ. a memory) will delete the 361 // packet on reception, so we need to save a copy here. 362 PacketPtr cp_pkt = new Packet(pkt, true); 363 targets.add(cp_pkt, curTick(), _order, Target::FromSnoop, 364 downstreamPending && targets.needsExclusive); 365 366 if (isPendingDirty()) { 367 pkt->assertMemInhibit(); 368 pkt->setSupplyExclusive(); 369 } 370 371 if (pkt->needsExclusive()) { 372 // This transaction will take away our pending copy 373 postInvalidate = true; 374 } 375 } 376 377 if (!pkt->needsExclusive()) { 378 // This transaction will get a read-shared copy, downgrading 379 // our copy if we had an exclusive one 380 postDowngrade = true; 381 pkt->assertShared(); 382 } 383 384 return true; 385} 386 387 388bool 389MSHR::promoteDeferredTargets() 390{ 391 assert(targets.empty()); 392 if (deferredTargets.empty()) { 393 return false; 394 } 395 396 // swap targets & deferredTargets lists 397 std::swap(targets, deferredTargets); 398 399 // clear deferredTargets flags 400 deferredTargets.resetFlags(); 401 402 order = targets.front().order; 403 readyTime = std::max(curTick(), targets.front().readyTime); 404 405 return true; 406} 407 408 409void 410MSHR::handleFill(Packet *pkt, CacheBlk *blk) 411{ 412 if (!pkt->sharedAsserted() 413 && !(hasPostInvalidate() || hasPostDowngrade()) 414 && deferredTargets.needsExclusive) { 415 // We got an exclusive response, but we have deferred targets 416 // which are waiting to request an exclusive copy (not because 417 // of a pending invalidate). This can happen if the original 418 // request was for a read-only (non-exclusive) block, but we 419 // got an exclusive copy anyway because of the E part of the 420 // MOESI/MESI protocol. Since we got the exclusive copy 421 // there's no need to defer the targets, so move them up to 422 // the regular target list. 423 assert(!targets.needsExclusive); 424 targets.needsExclusive = true; 425 // if any of the deferred targets were upper-level cache 426 // requests marked downstreamPending, need to clear that 427 assert(!downstreamPending); // not pending here anymore 428 deferredTargets.clearDownstreamPending(); 429 // this clears out deferredTargets too 430 targets.splice(targets.end(), deferredTargets); 431 deferredTargets.resetFlags(); 432 } 433} 434 435 436bool 437MSHR::checkFunctional(PacketPtr pkt) 438{ 439 // For printing, we treat the MSHR as a whole as single entity. 440 // For other requests, we iterate over the individual targets 441 // since that's where the actual data lies. 442 if (pkt->isPrint()) { 443 pkt->checkFunctional(this, addr, size, NULL); 444 return false; 445 } else { 446 return (targets.checkFunctional(pkt) || 447 deferredTargets.checkFunctional(pkt)); 448 } 449} 450 451 452void 453MSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const 454{ 455 ccprintf(os, "%s[%x:%x] %s %s %s state: %s %s %s %s %s\n", 456 prefix, addr, addr+size-1, 457 isForward ? "Forward" : "", 458 isForwardNoResponse() ? "ForwNoResp" : "", 459 needsExclusive() ? "Excl" : "", 460 _isUncacheable ? "Unc" : "", 461 inService ? "InSvc" : "", 462 downstreamPending ? "DwnPend" : "", 463 hasPostInvalidate() ? "PostInv" : "", 464 hasPostDowngrade() ? "PostDowngr" : ""); 465 466 ccprintf(os, "%s Targets:\n", prefix); 467 targets.print(os, verbosity, prefix + " "); 468 if (!deferredTargets.empty()) { 469 ccprintf(os, "%s Deferred Targets:\n", prefix); 470 deferredTargets.print(os, verbosity, prefix + " "); 471 } 472} 473 474std::string 475MSHR::print() const 476{ 477 ostringstream str; 478 print(str); 479 return str.str(); 480} 481