mshr.cc revision 9543
12810SN/A/* 22810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 37636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc. 42810SN/A * All rights reserved. 52810SN/A * 62810SN/A * Redistribution and use in source and binary forms, with or without 72810SN/A * modification, are permitted provided that the following conditions are 82810SN/A * met: redistributions of source code must retain the above copyright 92810SN/A * notice, this list of conditions and the following disclaimer; 102810SN/A * redistributions in binary form must reproduce the above copyright 112810SN/A * notice, this list of conditions and the following disclaimer in the 122810SN/A * documentation and/or other materials provided with the distribution; 132810SN/A * neither the name of the copyright holders nor the names of its 142810SN/A * contributors may be used to endorse or promote products derived from 152810SN/A * this software without specific prior written permission. 162810SN/A * 172810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282810SN/A * 292810SN/A * Authors: Erik Hallnor 302810SN/A * Dave Greene 312810SN/A */ 322810SN/A 332810SN/A/** 342810SN/A * @file 352810SN/A * Miss Status and Handling Register (MSHR) definitions. 362810SN/A */ 372810SN/A 386216Snate@binkert.org#include <algorithm> 396216Snate@binkert.org#include <cassert> 402810SN/A#include <string> 412810SN/A#include <vector> 422810SN/A 436216Snate@binkert.org#include "base/misc.hh" 446216Snate@binkert.org#include "base/types.hh" 458232Snate@binkert.org#include "debug/Cache.hh" 466216Snate@binkert.org#include "mem/cache/cache.hh" 475338Sstever@gmail.com#include "mem/cache/mshr.hh" 486216Snate@binkert.org#include "sim/core.hh" 492810SN/A 502810SN/Ausing namespace std; 512810SN/A 522810SN/AMSHR::MSHR() 532810SN/A{ 542810SN/A inService = false; 552810SN/A ntargets = 0; 566221Snate@binkert.org threadNum = InvalidThreadID; 574903SN/A targets = new TargetList(); 584903SN/A deferredTargets = new TargetList(); 592810SN/A} 602810SN/A 614903SN/A 624903SN/AMSHR::TargetList::TargetList() 634903SN/A : needsExclusive(false), hasUpgrade(false) 644903SN/A{} 654903SN/A 664903SN/A 674903SN/Ainline void 684908SN/AMSHR::TargetList::add(PacketPtr pkt, Tick readyTime, 695875Ssteve.reinhardt@amd.com Counter order, Target::Source source, bool markPending) 704903SN/A{ 715875Ssteve.reinhardt@amd.com if (source != Target::FromSnoop) { 724903SN/A if (pkt->needsExclusive()) { 734903SN/A needsExclusive = true; 744903SN/A } 754903SN/A 767669Ssteve.reinhardt@amd.com // StoreCondReq is effectively an upgrade if it's in an MSHR 777669Ssteve.reinhardt@amd.com // since it would have been failed already if we didn't have a 787669Ssteve.reinhardt@amd.com // read-only copy 797669Ssteve.reinhardt@amd.com if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) { 804903SN/A hasUpgrade = true; 814903SN/A } 825318SN/A } 834908SN/A 845318SN/A if (markPending) { 859543Ssascha.bischoff@arm.com // Iterate over the SenderState stack and see if we find 869543Ssascha.bischoff@arm.com // an MSHR entry. If we do, set the downstreamPending 879543Ssascha.bischoff@arm.com // flag. Otherwise, do nothing. 889543Ssascha.bischoff@arm.com MSHR *mshr = pkt->findNextSenderState<MSHR>(); 894908SN/A if (mshr != NULL) { 904908SN/A assert(!mshr->downstreamPending); 914908SN/A mshr->downstreamPending = true; 924908SN/A } 934903SN/A } 944903SN/A 955875Ssteve.reinhardt@amd.com push_back(Target(pkt, readyTime, order, source, markPending)); 964903SN/A} 974903SN/A 984903SN/A 997667Ssteve.reinhardt@amd.comstatic void 1007667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt) 1017667Ssteve.reinhardt@amd.com{ 1027667Ssteve.reinhardt@amd.com if (pkt->cmd == MemCmd::UpgradeReq) { 1037667Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::ReadExReq; 1047667Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n"); 1057667Ssteve.reinhardt@amd.com } else if (pkt->cmd == MemCmd::SCUpgradeReq) { 1067667Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::SCUpgradeFailReq; 1077667Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n"); 1087669Ssteve.reinhardt@amd.com } else if (pkt->cmd == MemCmd::StoreCondReq) { 1097669Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::StoreCondFailReq; 1107669Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n"); 1117667Ssteve.reinhardt@amd.com } 1127667Ssteve.reinhardt@amd.com} 1137667Ssteve.reinhardt@amd.com 1147667Ssteve.reinhardt@amd.com 1154903SN/Avoid 1164903SN/AMSHR::TargetList::replaceUpgrades() 1174903SN/A{ 1184903SN/A if (!hasUpgrade) 1194903SN/A return; 1204903SN/A 1214903SN/A Iterator end_i = end(); 1224903SN/A for (Iterator i = begin(); i != end_i; ++i) { 1237667Ssteve.reinhardt@amd.com replaceUpgrade(i->pkt); 1244903SN/A } 1254903SN/A 1264903SN/A hasUpgrade = false; 1274903SN/A} 1284903SN/A 1294903SN/A 1302810SN/Avoid 1314908SN/AMSHR::TargetList::clearDownstreamPending() 1324908SN/A{ 1334908SN/A Iterator end_i = end(); 1344908SN/A for (Iterator i = begin(); i != end_i; ++i) { 1355318SN/A if (i->markedPending) { 1369543Ssascha.bischoff@arm.com // Iterate over the SenderState stack and see if we find 1379543Ssascha.bischoff@arm.com // an MSHR entry. If we find one, clear the 1389543Ssascha.bischoff@arm.com // downstreamPending flag by calling 1399543Ssascha.bischoff@arm.com // clearDownstreamPending(). This recursively clears the 1409543Ssascha.bischoff@arm.com // downstreamPending flag in all caches this packet has 1419543Ssascha.bischoff@arm.com // passed through. 1429543Ssascha.bischoff@arm.com MSHR *mshr = i->pkt->findNextSenderState<MSHR>(); 1435318SN/A if (mshr != NULL) { 1445318SN/A mshr->clearDownstreamPending(); 1455318SN/A } 1464908SN/A } 1474908SN/A } 1484908SN/A} 1494908SN/A 1504908SN/A 1514920SN/Abool 1524920SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt) 1534920SN/A{ 1544920SN/A Iterator end_i = end(); 1554920SN/A for (Iterator i = begin(); i != end_i; ++i) { 1564920SN/A if (pkt->checkFunctional(i->pkt)) { 1574920SN/A return true; 1584920SN/A } 1594920SN/A } 1604920SN/A 1614920SN/A return false; 1624920SN/A} 1634920SN/A 1644920SN/A 1654908SN/Avoid 1665314SN/AMSHR::TargetList:: 1675314SN/Aprint(std::ostream &os, int verbosity, const std::string &prefix) const 1685314SN/A{ 1695314SN/A ConstIterator end_i = end(); 1705314SN/A for (ConstIterator i = begin(); i != end_i; ++i) { 1715875Ssteve.reinhardt@amd.com const char *s; 1725875Ssteve.reinhardt@amd.com switch (i->source) { 1738988SAli.Saidi@ARM.com case Target::FromCPU: 1748988SAli.Saidi@ARM.com s = "FromCPU"; 1758988SAli.Saidi@ARM.com break; 1768988SAli.Saidi@ARM.com case Target::FromSnoop: 1778988SAli.Saidi@ARM.com s = "FromSnoop"; 1788988SAli.Saidi@ARM.com break; 1798988SAli.Saidi@ARM.com case Target::FromPrefetcher: 1808988SAli.Saidi@ARM.com s = "FromPrefetcher"; 1818988SAli.Saidi@ARM.com break; 1828988SAli.Saidi@ARM.com default: 1838988SAli.Saidi@ARM.com s = ""; 1848988SAli.Saidi@ARM.com break; 1855875Ssteve.reinhardt@amd.com } 1865875Ssteve.reinhardt@amd.com ccprintf(os, "%s%s: ", prefix, s); 1875314SN/A i->pkt->print(os, verbosity, ""); 1885314SN/A } 1895314SN/A} 1905314SN/A 1915314SN/A 1925314SN/Avoid 1934666SN/AMSHR::allocate(Addr _addr, int _size, PacketPtr target, 1944871SN/A Tick whenReady, Counter _order) 1952810SN/A{ 1962885SN/A addr = _addr; 1974626SN/A size = _size; 1984871SN/A readyTime = whenReady; 1994666SN/A order = _order; 2004626SN/A assert(target); 2015730SSteve.Reinhardt@amd.com isForward = false; 2024626SN/A _isUncacheable = target->req->isUncacheable(); 2034626SN/A inService = false; 2044908SN/A downstreamPending = false; 2054626SN/A threadNum = 0; 2064626SN/A ntargets = 1; 2075875Ssteve.reinhardt@amd.com assert(targets->isReset()); 2084626SN/A // Don't know of a case where we would allocate a new MSHR for a 2095875Ssteve.reinhardt@amd.com // snoop (mem-side request), so set source according to request here 2105875Ssteve.reinhardt@amd.com Target::Source source = (target->cmd == MemCmd::HardPFReq) ? 2115875Ssteve.reinhardt@amd.com Target::FromPrefetcher : Target::FromCPU; 2125875Ssteve.reinhardt@amd.com targets->add(target, whenReady, _order, source, true); 2134903SN/A assert(deferredTargets->isReset()); 2144668SN/A data = NULL; 2152810SN/A} 2162810SN/A 2174908SN/A 2185318SN/Avoid 2195318SN/AMSHR::clearDownstreamPending() 2205318SN/A{ 2215318SN/A assert(downstreamPending); 2225318SN/A downstreamPending = false; 2235318SN/A // recursively clear flag on any MSHRs we will be forwarding 2245318SN/A // responses to 2255318SN/A targets->clearDownstreamPending(); 2265318SN/A} 2275318SN/A 2284908SN/Abool 2297667Ssteve.reinhardt@amd.comMSHR::markInService(PacketPtr pkt) 2304908SN/A{ 2314908SN/A assert(!inService); 2325730SSteve.Reinhardt@amd.com if (isForwardNoResponse()) { 2334908SN/A // we just forwarded the request packet & don't expect a 2344908SN/A // response, so get rid of it 2354908SN/A assert(getNumTargets() == 1); 2364908SN/A popTarget(); 2374908SN/A return true; 2384908SN/A } 2394908SN/A inService = true; 2407667Ssteve.reinhardt@amd.com pendingDirty = (targets->needsExclusive || 2417667Ssteve.reinhardt@amd.com (!pkt->sharedAsserted() && pkt->memInhibitAsserted())); 2427667Ssteve.reinhardt@amd.com postInvalidate = postDowngrade = false; 2437667Ssteve.reinhardt@amd.com 2444908SN/A if (!downstreamPending) { 2454908SN/A // let upstream caches know that the request has made it to a 2464908SN/A // level where it's going to get a response 2474908SN/A targets->clearDownstreamPending(); 2484908SN/A } 2494908SN/A return false; 2504908SN/A} 2514908SN/A 2524908SN/A 2532810SN/Avoid 2542810SN/AMSHR::deallocate() 2552810SN/A{ 2564903SN/A assert(targets->empty()); 2574903SN/A targets->resetFlags(); 2584903SN/A assert(deferredTargets->isReset()); 2592810SN/A assert(ntargets == 0); 2602810SN/A inService = false; 2612810SN/A} 2622810SN/A 2632810SN/A/* 2642810SN/A * Adds a target to an MSHR 2652810SN/A */ 2662810SN/Avoid 2674903SN/AMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order) 2682810SN/A{ 2694903SN/A // if there's a request already in service for this MSHR, we will 2704903SN/A // have to defer the new target until after the response if any of 2714903SN/A // the following are true: 2724903SN/A // - there are other targets already deferred 2734903SN/A // - there's a pending invalidate to be applied after the response 2744903SN/A // comes back (but before this target is processed) 2757667Ssteve.reinhardt@amd.com // - this target requires an exclusive block and either we're not 2767667Ssteve.reinhardt@amd.com // getting an exclusive block back or we have already snooped 2777667Ssteve.reinhardt@amd.com // another read request that will downgrade our exclusive block 2787667Ssteve.reinhardt@amd.com // to shared 2795875Ssteve.reinhardt@amd.com 2805875Ssteve.reinhardt@amd.com // assume we'd never issue a prefetch when we've got an 2815875Ssteve.reinhardt@amd.com // outstanding miss 2825875Ssteve.reinhardt@amd.com assert(pkt->cmd != MemCmd::HardPFReq); 2835875Ssteve.reinhardt@amd.com 2844903SN/A if (inService && 2857667Ssteve.reinhardt@amd.com (!deferredTargets->empty() || hasPostInvalidate() || 2867667Ssteve.reinhardt@amd.com (pkt->needsExclusive() && 2877667Ssteve.reinhardt@amd.com (!isPendingDirty() || hasPostDowngrade() || isForward)))) { 2884903SN/A // need to put on deferred list 2897667Ssteve.reinhardt@amd.com if (hasPostInvalidate()) 2907667Ssteve.reinhardt@amd.com replaceUpgrade(pkt); 2915875Ssteve.reinhardt@amd.com deferredTargets->add(pkt, whenReady, _order, Target::FromCPU, true); 2924665SN/A } else { 2935318SN/A // No request outstanding, or still OK to append to 2945318SN/A // outstanding request: append to regular target list. Only 2955318SN/A // mark pending if current request hasn't been issued yet 2965318SN/A // (isn't in service). 2975875Ssteve.reinhardt@amd.com targets->add(pkt, whenReady, _order, Target::FromCPU, !inService); 2982810SN/A } 2992810SN/A 3002810SN/A ++ntargets; 3014665SN/A} 3024665SN/A 3034902SN/Abool 3044902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order) 3054665SN/A{ 3064910SN/A if (!inService || (pkt->isExpressSnoop() && downstreamPending)) { 3074903SN/A // Request has not been issued yet, or it's been issued 3084903SN/A // locally but is buffered unissued at some downstream cache 3094903SN/A // which is forwarding us this snoop. Either way, the packet 3104903SN/A // we're snooping logically precedes this MSHR's request, so 3114903SN/A // the snoop has no impact on the MSHR, but must be processed 3124903SN/A // in the standard way by the cache. The only exception is 3134903SN/A // that if we're an L2+ cache buffering an UpgradeReq from a 3144903SN/A // higher-level cache, and the snoop is invalidating, then our 3154903SN/A // buffered upgrades must be converted to read exclusives, 3164903SN/A // since the upper-level cache no longer has a valid copy. 3174903SN/A // That is, even though the upper-level cache got out on its 3184903SN/A // local bus first, some other invalidating transaction 3194903SN/A // reached the global bus before the upgrade did. 3204903SN/A if (pkt->needsExclusive()) { 3214903SN/A targets->replaceUpgrades(); 3224903SN/A deferredTargets->replaceUpgrades(); 3234903SN/A } 3244903SN/A 3254902SN/A return false; 3264902SN/A } 3274665SN/A 3284903SN/A // From here on down, the request issued by this MSHR logically 3294903SN/A // precedes the request we're snooping. 3304903SN/A if (pkt->needsExclusive()) { 3314903SN/A // snooped request still precedes the re-request we'll have to 3324903SN/A // issue for deferred targets, if any... 3334903SN/A deferredTargets->replaceUpgrades(); 3344903SN/A } 3354903SN/A 3367667Ssteve.reinhardt@amd.com if (hasPostInvalidate()) { 3374665SN/A // a prior snoop has already appended an invalidation, so 3384903SN/A // logically we don't have the block anymore; no need for 3394903SN/A // further snooping. 3404902SN/A return true; 3414665SN/A } 3424665SN/A 3437667Ssteve.reinhardt@amd.com if (isPendingDirty() || pkt->isInvalidate()) { 3447667Ssteve.reinhardt@amd.com // We need to save and replay the packet in two cases: 3457667Ssteve.reinhardt@amd.com // 1. We're awaiting an exclusive copy, so ownership is pending, 3467667Ssteve.reinhardt@amd.com // and we need to respond after we receive data. 3477667Ssteve.reinhardt@amd.com // 2. It's an invalidation (e.g., UpgradeReq), and we need 3487667Ssteve.reinhardt@amd.com // to forward the snoop up the hierarchy after the current 3497667Ssteve.reinhardt@amd.com // transaction completes. 3507667Ssteve.reinhardt@amd.com 3518931Sandreas.hansson@arm.com // Actual target device (typ. a memory) will delete the 3527667Ssteve.reinhardt@amd.com // packet on reception, so we need to save a copy here. 3534970SN/A PacketPtr cp_pkt = new Packet(pkt, true); 3547823Ssteve.reinhardt@amd.com targets->add(cp_pkt, curTick(), _order, Target::FromSnoop, 3555318SN/A downstreamPending && targets->needsExclusive); 3564670SN/A ++ntargets; 3574670SN/A 3587667Ssteve.reinhardt@amd.com if (isPendingDirty()) { 3594670SN/A pkt->assertMemInhibit(); 3604916SN/A pkt->setSupplyExclusive(); 3614670SN/A } 3624670SN/A 3634670SN/A if (pkt->needsExclusive()) { 3644670SN/A // This transaction will take away our pending copy 3657667Ssteve.reinhardt@amd.com postInvalidate = true; 3664670SN/A } 3677667Ssteve.reinhardt@amd.com } 3687667Ssteve.reinhardt@amd.com 3697667Ssteve.reinhardt@amd.com if (!pkt->needsExclusive()) { 3707667Ssteve.reinhardt@amd.com // This transaction will get a read-shared copy, downgrading 3717667Ssteve.reinhardt@amd.com // our copy if we had an exclusive one 3727667Ssteve.reinhardt@amd.com postDowngrade = true; 3734670SN/A pkt->assertShared(); 3744667SN/A } 3754902SN/A 3764902SN/A return true; 3774665SN/A} 3784665SN/A 3794665SN/A 3804665SN/Abool 3814665SN/AMSHR::promoteDeferredTargets() 3824665SN/A{ 3834903SN/A assert(targets->empty()); 3844903SN/A if (deferredTargets->empty()) { 3854665SN/A return false; 3864665SN/A } 3874665SN/A 3884903SN/A // swap targets & deferredTargets lists 3894903SN/A TargetList *tmp = targets; 3904665SN/A targets = deferredTargets; 3914903SN/A deferredTargets = tmp; 3922810SN/A 3934903SN/A assert(targets->size() == ntargets); 3944903SN/A 3954903SN/A // clear deferredTargets flags 3964903SN/A deferredTargets->resetFlags(); 3974903SN/A 3984903SN/A order = targets->front().order; 3997823Ssteve.reinhardt@amd.com readyTime = std::max(curTick(), targets->front().readyTime); 4004665SN/A 4014665SN/A return true; 4022810SN/A} 4032810SN/A 4042810SN/A 4052810SN/Avoid 4064670SN/AMSHR::handleFill(Packet *pkt, CacheBlk *blk) 4074668SN/A{ 4087667Ssteve.reinhardt@amd.com if (!pkt->sharedAsserted() 4097667Ssteve.reinhardt@amd.com && !(hasPostInvalidate() || hasPostDowngrade()) 4105270SN/A && deferredTargets->needsExclusive) { 4115270SN/A // We got an exclusive response, but we have deferred targets 4125270SN/A // which are waiting to request an exclusive copy (not because 4135270SN/A // of a pending invalidate). This can happen if the original 4145270SN/A // request was for a read-only (non-exclusive) block, but we 4155270SN/A // got an exclusive copy anyway because of the E part of the 4165270SN/A // MOESI/MESI protocol. Since we got the exclusive copy 4175270SN/A // there's no need to defer the targets, so move them up to 4185270SN/A // the regular target list. 4195270SN/A assert(!targets->needsExclusive); 4205270SN/A targets->needsExclusive = true; 4215318SN/A // if any of the deferred targets were upper-level cache 4225318SN/A // requests marked downstreamPending, need to clear that 4235318SN/A assert(!downstreamPending); // not pending here anymore 4245318SN/A deferredTargets->clearDownstreamPending(); 4255270SN/A // this clears out deferredTargets too 4265270SN/A targets->splice(targets->end(), *deferredTargets); 4275270SN/A deferredTargets->resetFlags(); 4285270SN/A } 4294668SN/A} 4304668SN/A 4314668SN/A 4325314SN/Abool 4335314SN/AMSHR::checkFunctional(PacketPtr pkt) 4345314SN/A{ 4355314SN/A // For printing, we treat the MSHR as a whole as single entity. 4365314SN/A // For other requests, we iterate over the individual targets 4375314SN/A // since that's where the actual data lies. 4385314SN/A if (pkt->isPrint()) { 4395314SN/A pkt->checkFunctional(this, addr, size, NULL); 4405314SN/A return false; 4415314SN/A } else { 4425314SN/A return (targets->checkFunctional(pkt) || 4435314SN/A deferredTargets->checkFunctional(pkt)); 4445314SN/A } 4455314SN/A} 4465314SN/A 4475314SN/A 4484668SN/Avoid 4495314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const 4502810SN/A{ 4515314SN/A ccprintf(os, "%s[%x:%x] %s %s %s state: %s %s %s %s\n", 4525314SN/A prefix, addr, addr+size-1, 4535730SSteve.Reinhardt@amd.com isForward ? "Forward" : "", 4545730SSteve.Reinhardt@amd.com isForwardNoResponse() ? "ForwNoResp" : "", 4555314SN/A needsExclusive() ? "Excl" : "", 4565314SN/A _isUncacheable ? "Unc" : "", 4575314SN/A inService ? "InSvc" : "", 4585314SN/A downstreamPending ? "DwnPend" : "", 4597667Ssteve.reinhardt@amd.com hasPostInvalidate() ? "PostInv" : "", 4607667Ssteve.reinhardt@amd.com hasPostDowngrade() ? "PostDowngr" : ""); 4612810SN/A 4625314SN/A ccprintf(os, "%s Targets:\n", prefix); 4635314SN/A targets->print(os, verbosity, prefix + " "); 4645314SN/A if (!deferredTargets->empty()) { 4655314SN/A ccprintf(os, "%s Deferred Targets:\n", prefix); 4665314SN/A deferredTargets->print(os, verbosity, prefix + " "); 4672810SN/A } 4682810SN/A} 4692810SN/A 4702810SN/AMSHR::~MSHR() 4712810SN/A{ 4729086Sandreas.hansson@arm.com delete[] targets; 4739086Sandreas.hansson@arm.com delete[] deferredTargets; 4742810SN/A} 475