mshr.cc revision 9086
12810SN/A/*
22810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
37636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
42810SN/A * All rights reserved.
52810SN/A *
62810SN/A * Redistribution and use in source and binary forms, with or without
72810SN/A * modification, are permitted provided that the following conditions are
82810SN/A * met: redistributions of source code must retain the above copyright
92810SN/A * notice, this list of conditions and the following disclaimer;
102810SN/A * redistributions in binary form must reproduce the above copyright
112810SN/A * notice, this list of conditions and the following disclaimer in the
122810SN/A * documentation and/or other materials provided with the distribution;
132810SN/A * neither the name of the copyright holders nor the names of its
142810SN/A * contributors may be used to endorse or promote products derived from
152810SN/A * this software without specific prior written permission.
162810SN/A *
172810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
222810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
232810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
242810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
252810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
262810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282810SN/A *
292810SN/A * Authors: Erik Hallnor
302810SN/A *          Dave Greene
312810SN/A */
322810SN/A
332810SN/A/**
342810SN/A * @file
352810SN/A * Miss Status and Handling Register (MSHR) definitions.
362810SN/A */
372810SN/A
386216Snate@binkert.org#include <algorithm>
396216Snate@binkert.org#include <cassert>
402810SN/A#include <string>
412810SN/A#include <vector>
422810SN/A
436216Snate@binkert.org#include "base/misc.hh"
446216Snate@binkert.org#include "base/types.hh"
458232Snate@binkert.org#include "debug/Cache.hh"
466216Snate@binkert.org#include "mem/cache/cache.hh"
475338Sstever@gmail.com#include "mem/cache/mshr.hh"
486216Snate@binkert.org#include "sim/core.hh"
492810SN/A
502810SN/Ausing namespace std;
512810SN/A
522810SN/AMSHR::MSHR()
532810SN/A{
542810SN/A    inService = false;
552810SN/A    ntargets = 0;
566221Snate@binkert.org    threadNum = InvalidThreadID;
574903SN/A    targets = new TargetList();
584903SN/A    deferredTargets = new TargetList();
592810SN/A}
602810SN/A
614903SN/A
624903SN/AMSHR::TargetList::TargetList()
634903SN/A    : needsExclusive(false), hasUpgrade(false)
644903SN/A{}
654903SN/A
664903SN/A
674903SN/Ainline void
684908SN/AMSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
695875Ssteve.reinhardt@amd.com                      Counter order, Target::Source source, bool markPending)
704903SN/A{
715875Ssteve.reinhardt@amd.com    if (source != Target::FromSnoop) {
724903SN/A        if (pkt->needsExclusive()) {
734903SN/A            needsExclusive = true;
744903SN/A        }
754903SN/A
767669Ssteve.reinhardt@amd.com        // StoreCondReq is effectively an upgrade if it's in an MSHR
777669Ssteve.reinhardt@amd.com        // since it would have been failed already if we didn't have a
787669Ssteve.reinhardt@amd.com        // read-only copy
797669Ssteve.reinhardt@amd.com        if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
804903SN/A            hasUpgrade = true;
814903SN/A        }
825318SN/A    }
834908SN/A
845318SN/A    if (markPending) {
854908SN/A        MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
864908SN/A        if (mshr != NULL) {
874908SN/A            assert(!mshr->downstreamPending);
884908SN/A            mshr->downstreamPending = true;
894908SN/A        }
904903SN/A    }
914903SN/A
925875Ssteve.reinhardt@amd.com    push_back(Target(pkt, readyTime, order, source, markPending));
934903SN/A}
944903SN/A
954903SN/A
967667Ssteve.reinhardt@amd.comstatic void
977667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt)
987667Ssteve.reinhardt@amd.com{
997667Ssteve.reinhardt@amd.com    if (pkt->cmd == MemCmd::UpgradeReq) {
1007667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::ReadExReq;
1017667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
1027667Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
1037667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::SCUpgradeFailReq;
1047667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
1057669Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::StoreCondReq) {
1067669Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::StoreCondFailReq;
1077669Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
1087667Ssteve.reinhardt@amd.com    }
1097667Ssteve.reinhardt@amd.com}
1107667Ssteve.reinhardt@amd.com
1117667Ssteve.reinhardt@amd.com
1124903SN/Avoid
1134903SN/AMSHR::TargetList::replaceUpgrades()
1144903SN/A{
1154903SN/A    if (!hasUpgrade)
1164903SN/A        return;
1174903SN/A
1184903SN/A    Iterator end_i = end();
1194903SN/A    for (Iterator i = begin(); i != end_i; ++i) {
1207667Ssteve.reinhardt@amd.com        replaceUpgrade(i->pkt);
1214903SN/A    }
1224903SN/A
1234903SN/A    hasUpgrade = false;
1244903SN/A}
1254903SN/A
1264903SN/A
1272810SN/Avoid
1284908SN/AMSHR::TargetList::clearDownstreamPending()
1294908SN/A{
1304908SN/A    Iterator end_i = end();
1314908SN/A    for (Iterator i = begin(); i != end_i; ++i) {
1325318SN/A        if (i->markedPending) {
1335318SN/A            MSHR *mshr = dynamic_cast<MSHR*>(i->pkt->senderState);
1345318SN/A            if (mshr != NULL) {
1355318SN/A                mshr->clearDownstreamPending();
1365318SN/A            }
1374908SN/A        }
1384908SN/A    }
1394908SN/A}
1404908SN/A
1414908SN/A
1424920SN/Abool
1434920SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt)
1444920SN/A{
1454920SN/A    Iterator end_i = end();
1464920SN/A    for (Iterator i = begin(); i != end_i; ++i) {
1474920SN/A        if (pkt->checkFunctional(i->pkt)) {
1484920SN/A            return true;
1494920SN/A        }
1504920SN/A    }
1514920SN/A
1524920SN/A    return false;
1534920SN/A}
1544920SN/A
1554920SN/A
1564908SN/Avoid
1575314SN/AMSHR::TargetList::
1585314SN/Aprint(std::ostream &os, int verbosity, const std::string &prefix) const
1595314SN/A{
1605314SN/A    ConstIterator end_i = end();
1615314SN/A    for (ConstIterator i = begin(); i != end_i; ++i) {
1625875Ssteve.reinhardt@amd.com        const char *s;
1635875Ssteve.reinhardt@amd.com        switch (i->source) {
1648988SAli.Saidi@ARM.com          case Target::FromCPU:
1658988SAli.Saidi@ARM.com            s = "FromCPU";
1668988SAli.Saidi@ARM.com            break;
1678988SAli.Saidi@ARM.com          case Target::FromSnoop:
1688988SAli.Saidi@ARM.com            s = "FromSnoop";
1698988SAli.Saidi@ARM.com            break;
1708988SAli.Saidi@ARM.com          case Target::FromPrefetcher:
1718988SAli.Saidi@ARM.com            s = "FromPrefetcher";
1728988SAli.Saidi@ARM.com            break;
1738988SAli.Saidi@ARM.com          default:
1748988SAli.Saidi@ARM.com            s = "";
1758988SAli.Saidi@ARM.com            break;
1765875Ssteve.reinhardt@amd.com        }
1775875Ssteve.reinhardt@amd.com        ccprintf(os, "%s%s: ", prefix, s);
1785314SN/A        i->pkt->print(os, verbosity, "");
1795314SN/A    }
1805314SN/A}
1815314SN/A
1825314SN/A
1835314SN/Avoid
1844666SN/AMSHR::allocate(Addr _addr, int _size, PacketPtr target,
1854871SN/A               Tick whenReady, Counter _order)
1862810SN/A{
1872885SN/A    addr = _addr;
1884626SN/A    size = _size;
1894871SN/A    readyTime = whenReady;
1904666SN/A    order = _order;
1914626SN/A    assert(target);
1925730SSteve.Reinhardt@amd.com    isForward = false;
1934626SN/A    _isUncacheable = target->req->isUncacheable();
1944626SN/A    inService = false;
1954908SN/A    downstreamPending = false;
1964626SN/A    threadNum = 0;
1974626SN/A    ntargets = 1;
1985875Ssteve.reinhardt@amd.com    assert(targets->isReset());
1994626SN/A    // Don't know of a case where we would allocate a new MSHR for a
2005875Ssteve.reinhardt@amd.com    // snoop (mem-side request), so set source according to request here
2015875Ssteve.reinhardt@amd.com    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
2025875Ssteve.reinhardt@amd.com        Target::FromPrefetcher : Target::FromCPU;
2035875Ssteve.reinhardt@amd.com    targets->add(target, whenReady, _order, source, true);
2044903SN/A    assert(deferredTargets->isReset());
2054668SN/A    data = NULL;
2062810SN/A}
2072810SN/A
2084908SN/A
2095318SN/Avoid
2105318SN/AMSHR::clearDownstreamPending()
2115318SN/A{
2125318SN/A    assert(downstreamPending);
2135318SN/A    downstreamPending = false;
2145318SN/A    // recursively clear flag on any MSHRs we will be forwarding
2155318SN/A    // responses to
2165318SN/A    targets->clearDownstreamPending();
2175318SN/A}
2185318SN/A
2194908SN/Abool
2207667Ssteve.reinhardt@amd.comMSHR::markInService(PacketPtr pkt)
2214908SN/A{
2224908SN/A    assert(!inService);
2235730SSteve.Reinhardt@amd.com    if (isForwardNoResponse()) {
2244908SN/A        // we just forwarded the request packet & don't expect a
2254908SN/A        // response, so get rid of it
2264908SN/A        assert(getNumTargets() == 1);
2274908SN/A        popTarget();
2284908SN/A        return true;
2294908SN/A    }
2304908SN/A    inService = true;
2317667Ssteve.reinhardt@amd.com    pendingDirty = (targets->needsExclusive ||
2327667Ssteve.reinhardt@amd.com                    (!pkt->sharedAsserted() && pkt->memInhibitAsserted()));
2337667Ssteve.reinhardt@amd.com    postInvalidate = postDowngrade = false;
2347667Ssteve.reinhardt@amd.com
2354908SN/A    if (!downstreamPending) {
2364908SN/A        // let upstream caches know that the request has made it to a
2374908SN/A        // level where it's going to get a response
2384908SN/A        targets->clearDownstreamPending();
2394908SN/A    }
2404908SN/A    return false;
2414908SN/A}
2424908SN/A
2434908SN/A
2442810SN/Avoid
2452810SN/AMSHR::deallocate()
2462810SN/A{
2474903SN/A    assert(targets->empty());
2484903SN/A    targets->resetFlags();
2494903SN/A    assert(deferredTargets->isReset());
2502810SN/A    assert(ntargets == 0);
2512810SN/A    inService = false;
2522810SN/A}
2532810SN/A
2542810SN/A/*
2552810SN/A * Adds a target to an MSHR
2562810SN/A */
2572810SN/Avoid
2584903SN/AMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order)
2592810SN/A{
2604903SN/A    // if there's a request already in service for this MSHR, we will
2614903SN/A    // have to defer the new target until after the response if any of
2624903SN/A    // the following are true:
2634903SN/A    // - there are other targets already deferred
2644903SN/A    // - there's a pending invalidate to be applied after the response
2654903SN/A    //   comes back (but before this target is processed)
2667667Ssteve.reinhardt@amd.com    // - this target requires an exclusive block and either we're not
2677667Ssteve.reinhardt@amd.com    //   getting an exclusive block back or we have already snooped
2687667Ssteve.reinhardt@amd.com    //   another read request that will downgrade our exclusive block
2697667Ssteve.reinhardt@amd.com    //   to shared
2705875Ssteve.reinhardt@amd.com
2715875Ssteve.reinhardt@amd.com    // assume we'd never issue a prefetch when we've got an
2725875Ssteve.reinhardt@amd.com    // outstanding miss
2735875Ssteve.reinhardt@amd.com    assert(pkt->cmd != MemCmd::HardPFReq);
2745875Ssteve.reinhardt@amd.com
2754903SN/A    if (inService &&
2767667Ssteve.reinhardt@amd.com        (!deferredTargets->empty() || hasPostInvalidate() ||
2777667Ssteve.reinhardt@amd.com         (pkt->needsExclusive() &&
2787667Ssteve.reinhardt@amd.com          (!isPendingDirty() || hasPostDowngrade() || isForward)))) {
2794903SN/A        // need to put on deferred list
2807667Ssteve.reinhardt@amd.com        if (hasPostInvalidate())
2817667Ssteve.reinhardt@amd.com            replaceUpgrade(pkt);
2825875Ssteve.reinhardt@amd.com        deferredTargets->add(pkt, whenReady, _order, Target::FromCPU, true);
2834665SN/A    } else {
2845318SN/A        // No request outstanding, or still OK to append to
2855318SN/A        // outstanding request: append to regular target list.  Only
2865318SN/A        // mark pending if current request hasn't been issued yet
2875318SN/A        // (isn't in service).
2885875Ssteve.reinhardt@amd.com        targets->add(pkt, whenReady, _order, Target::FromCPU, !inService);
2892810SN/A    }
2902810SN/A
2912810SN/A    ++ntargets;
2924665SN/A}
2934665SN/A
2944902SN/Abool
2954902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order)
2964665SN/A{
2974910SN/A    if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
2984903SN/A        // Request has not been issued yet, or it's been issued
2994903SN/A        // locally but is buffered unissued at some downstream cache
3004903SN/A        // which is forwarding us this snoop.  Either way, the packet
3014903SN/A        // we're snooping logically precedes this MSHR's request, so
3024903SN/A        // the snoop has no impact on the MSHR, but must be processed
3034903SN/A        // in the standard way by the cache.  The only exception is
3044903SN/A        // that if we're an L2+ cache buffering an UpgradeReq from a
3054903SN/A        // higher-level cache, and the snoop is invalidating, then our
3064903SN/A        // buffered upgrades must be converted to read exclusives,
3074903SN/A        // since the upper-level cache no longer has a valid copy.
3084903SN/A        // That is, even though the upper-level cache got out on its
3094903SN/A        // local bus first, some other invalidating transaction
3104903SN/A        // reached the global bus before the upgrade did.
3114903SN/A        if (pkt->needsExclusive()) {
3124903SN/A            targets->replaceUpgrades();
3134903SN/A            deferredTargets->replaceUpgrades();
3144903SN/A        }
3154903SN/A
3164902SN/A        return false;
3174902SN/A    }
3184665SN/A
3194903SN/A    // From here on down, the request issued by this MSHR logically
3204903SN/A    // precedes the request we're snooping.
3214903SN/A    if (pkt->needsExclusive()) {
3224903SN/A        // snooped request still precedes the re-request we'll have to
3234903SN/A        // issue for deferred targets, if any...
3244903SN/A        deferredTargets->replaceUpgrades();
3254903SN/A    }
3264903SN/A
3277667Ssteve.reinhardt@amd.com    if (hasPostInvalidate()) {
3284665SN/A        // a prior snoop has already appended an invalidation, so
3294903SN/A        // logically we don't have the block anymore; no need for
3304903SN/A        // further snooping.
3314902SN/A        return true;
3324665SN/A    }
3334665SN/A
3347667Ssteve.reinhardt@amd.com    if (isPendingDirty() || pkt->isInvalidate()) {
3357667Ssteve.reinhardt@amd.com        // We need to save and replay the packet in two cases:
3367667Ssteve.reinhardt@amd.com        // 1. We're awaiting an exclusive copy, so ownership is pending,
3377667Ssteve.reinhardt@amd.com        //    and we need to respond after we receive data.
3387667Ssteve.reinhardt@amd.com        // 2. It's an invalidation (e.g., UpgradeReq), and we need
3397667Ssteve.reinhardt@amd.com        //    to forward the snoop up the hierarchy after the current
3407667Ssteve.reinhardt@amd.com        //    transaction completes.
3417667Ssteve.reinhardt@amd.com
3428931Sandreas.hansson@arm.com        // Actual target device (typ. a memory) will delete the
3437667Ssteve.reinhardt@amd.com        // packet on reception, so we need to save a copy here.
3444970SN/A        PacketPtr cp_pkt = new Packet(pkt, true);
3457823Ssteve.reinhardt@amd.com        targets->add(cp_pkt, curTick(), _order, Target::FromSnoop,
3465318SN/A                     downstreamPending && targets->needsExclusive);
3474670SN/A        ++ntargets;
3484670SN/A
3497667Ssteve.reinhardt@amd.com        if (isPendingDirty()) {
3504670SN/A            pkt->assertMemInhibit();
3514916SN/A            pkt->setSupplyExclusive();
3524670SN/A        }
3534670SN/A
3544670SN/A        if (pkt->needsExclusive()) {
3554670SN/A            // This transaction will take away our pending copy
3567667Ssteve.reinhardt@amd.com            postInvalidate = true;
3574670SN/A        }
3587667Ssteve.reinhardt@amd.com    }
3597667Ssteve.reinhardt@amd.com
3607667Ssteve.reinhardt@amd.com    if (!pkt->needsExclusive()) {
3617667Ssteve.reinhardt@amd.com        // This transaction will get a read-shared copy, downgrading
3627667Ssteve.reinhardt@amd.com        // our copy if we had an exclusive one
3637667Ssteve.reinhardt@amd.com        postDowngrade = true;
3644670SN/A        pkt->assertShared();
3654667SN/A    }
3664902SN/A
3674902SN/A    return true;
3684665SN/A}
3694665SN/A
3704665SN/A
3714665SN/Abool
3724665SN/AMSHR::promoteDeferredTargets()
3734665SN/A{
3744903SN/A    assert(targets->empty());
3754903SN/A    if (deferredTargets->empty()) {
3764665SN/A        return false;
3774665SN/A    }
3784665SN/A
3794903SN/A    // swap targets & deferredTargets lists
3804903SN/A    TargetList *tmp = targets;
3814665SN/A    targets = deferredTargets;
3824903SN/A    deferredTargets = tmp;
3832810SN/A
3844903SN/A    assert(targets->size() == ntargets);
3854903SN/A
3864903SN/A    // clear deferredTargets flags
3874903SN/A    deferredTargets->resetFlags();
3884903SN/A
3894903SN/A    order = targets->front().order;
3907823Ssteve.reinhardt@amd.com    readyTime = std::max(curTick(), targets->front().readyTime);
3914665SN/A
3924665SN/A    return true;
3932810SN/A}
3942810SN/A
3952810SN/A
3962810SN/Avoid
3974670SN/AMSHR::handleFill(Packet *pkt, CacheBlk *blk)
3984668SN/A{
3997667Ssteve.reinhardt@amd.com    if (!pkt->sharedAsserted()
4007667Ssteve.reinhardt@amd.com        && !(hasPostInvalidate() || hasPostDowngrade())
4015270SN/A        && deferredTargets->needsExclusive) {
4025270SN/A        // We got an exclusive response, but we have deferred targets
4035270SN/A        // which are waiting to request an exclusive copy (not because
4045270SN/A        // of a pending invalidate).  This can happen if the original
4055270SN/A        // request was for a read-only (non-exclusive) block, but we
4065270SN/A        // got an exclusive copy anyway because of the E part of the
4075270SN/A        // MOESI/MESI protocol.  Since we got the exclusive copy
4085270SN/A        // there's no need to defer the targets, so move them up to
4095270SN/A        // the regular target list.
4105270SN/A        assert(!targets->needsExclusive);
4115270SN/A        targets->needsExclusive = true;
4125318SN/A        // if any of the deferred targets were upper-level cache
4135318SN/A        // requests marked downstreamPending, need to clear that
4145318SN/A        assert(!downstreamPending);  // not pending here anymore
4155318SN/A        deferredTargets->clearDownstreamPending();
4165270SN/A        // this clears out deferredTargets too
4175270SN/A        targets->splice(targets->end(), *deferredTargets);
4185270SN/A        deferredTargets->resetFlags();
4195270SN/A    }
4204668SN/A}
4214668SN/A
4224668SN/A
4235314SN/Abool
4245314SN/AMSHR::checkFunctional(PacketPtr pkt)
4255314SN/A{
4265314SN/A    // For printing, we treat the MSHR as a whole as single entity.
4275314SN/A    // For other requests, we iterate over the individual targets
4285314SN/A    // since that's where the actual data lies.
4295314SN/A    if (pkt->isPrint()) {
4305314SN/A        pkt->checkFunctional(this, addr, size, NULL);
4315314SN/A        return false;
4325314SN/A    } else {
4335314SN/A        return (targets->checkFunctional(pkt) ||
4345314SN/A                deferredTargets->checkFunctional(pkt));
4355314SN/A    }
4365314SN/A}
4375314SN/A
4385314SN/A
4394668SN/Avoid
4405314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
4412810SN/A{
4425314SN/A    ccprintf(os, "%s[%x:%x] %s %s %s state: %s %s %s %s\n",
4435314SN/A             prefix, addr, addr+size-1,
4445730SSteve.Reinhardt@amd.com             isForward ? "Forward" : "",
4455730SSteve.Reinhardt@amd.com             isForwardNoResponse() ? "ForwNoResp" : "",
4465314SN/A             needsExclusive() ? "Excl" : "",
4475314SN/A             _isUncacheable ? "Unc" : "",
4485314SN/A             inService ? "InSvc" : "",
4495314SN/A             downstreamPending ? "DwnPend" : "",
4507667Ssteve.reinhardt@amd.com             hasPostInvalidate() ? "PostInv" : "",
4517667Ssteve.reinhardt@amd.com             hasPostDowngrade() ? "PostDowngr" : "");
4522810SN/A
4535314SN/A    ccprintf(os, "%s  Targets:\n", prefix);
4545314SN/A    targets->print(os, verbosity, prefix + "    ");
4555314SN/A    if (!deferredTargets->empty()) {
4565314SN/A        ccprintf(os, "%s  Deferred Targets:\n", prefix);
4575314SN/A        deferredTargets->print(os, verbosity, prefix + "      ");
4582810SN/A    }
4592810SN/A}
4602810SN/A
4612810SN/AMSHR::~MSHR()
4622810SN/A{
4639086Sandreas.hansson@arm.com    delete[] targets;
4649086Sandreas.hansson@arm.com    delete[] deferredTargets;
4652810SN/A}
466