mshr.cc revision 8931
12810SN/A/* 22810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 37636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc. 42810SN/A * All rights reserved. 52810SN/A * 62810SN/A * Redistribution and use in source and binary forms, with or without 72810SN/A * modification, are permitted provided that the following conditions are 82810SN/A * met: redistributions of source code must retain the above copyright 92810SN/A * notice, this list of conditions and the following disclaimer; 102810SN/A * redistributions in binary form must reproduce the above copyright 112810SN/A * notice, this list of conditions and the following disclaimer in the 122810SN/A * documentation and/or other materials provided with the distribution; 132810SN/A * neither the name of the copyright holders nor the names of its 142810SN/A * contributors may be used to endorse or promote products derived from 152810SN/A * this software without specific prior written permission. 162810SN/A * 172810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282810SN/A * 292810SN/A * Authors: Erik Hallnor 302810SN/A * Dave Greene 312810SN/A */ 322810SN/A 332810SN/A/** 342810SN/A * @file 352810SN/A * Miss Status and Handling Register (MSHR) definitions. 362810SN/A */ 372810SN/A 386216Snate@binkert.org#include <algorithm> 396216Snate@binkert.org#include <cassert> 402810SN/A#include <string> 412810SN/A#include <vector> 422810SN/A 436216Snate@binkert.org#include "base/misc.hh" 446216Snate@binkert.org#include "base/types.hh" 458232Snate@binkert.org#include "debug/Cache.hh" 466216Snate@binkert.org#include "mem/cache/cache.hh" 475338Sstever@gmail.com#include "mem/cache/mshr.hh" 486216Snate@binkert.org#include "sim/core.hh" 492810SN/A 502810SN/Ausing namespace std; 512810SN/A 522810SN/AMSHR::MSHR() 532810SN/A{ 542810SN/A inService = false; 552810SN/A ntargets = 0; 566221Snate@binkert.org threadNum = InvalidThreadID; 574903SN/A targets = new TargetList(); 584903SN/A deferredTargets = new TargetList(); 592810SN/A} 602810SN/A 614903SN/A 624903SN/AMSHR::TargetList::TargetList() 634903SN/A : needsExclusive(false), hasUpgrade(false) 644903SN/A{} 654903SN/A 664903SN/A 674903SN/Ainline void 684908SN/AMSHR::TargetList::add(PacketPtr pkt, Tick readyTime, 695875Ssteve.reinhardt@amd.com Counter order, Target::Source source, bool markPending) 704903SN/A{ 715875Ssteve.reinhardt@amd.com if (source != Target::FromSnoop) { 724903SN/A if (pkt->needsExclusive()) { 734903SN/A needsExclusive = true; 744903SN/A } 754903SN/A 767669Ssteve.reinhardt@amd.com // StoreCondReq is effectively an upgrade if it's in an MSHR 777669Ssteve.reinhardt@amd.com // since it would have been failed already if we didn't have a 787669Ssteve.reinhardt@amd.com // read-only copy 797669Ssteve.reinhardt@amd.com if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) { 804903SN/A hasUpgrade = true; 814903SN/A } 825318SN/A } 834908SN/A 845318SN/A if (markPending) { 854908SN/A MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState); 864908SN/A if (mshr != NULL) { 874908SN/A assert(!mshr->downstreamPending); 884908SN/A mshr->downstreamPending = true; 894908SN/A } 904903SN/A } 914903SN/A 925875Ssteve.reinhardt@amd.com push_back(Target(pkt, readyTime, order, source, markPending)); 934903SN/A} 944903SN/A 954903SN/A 967667Ssteve.reinhardt@amd.comstatic void 977667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt) 987667Ssteve.reinhardt@amd.com{ 997667Ssteve.reinhardt@amd.com if (pkt->cmd == MemCmd::UpgradeReq) { 1007667Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::ReadExReq; 1017667Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n"); 1027667Ssteve.reinhardt@amd.com } else if (pkt->cmd == MemCmd::SCUpgradeReq) { 1037667Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::SCUpgradeFailReq; 1047667Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n"); 1057669Ssteve.reinhardt@amd.com } else if (pkt->cmd == MemCmd::StoreCondReq) { 1067669Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::StoreCondFailReq; 1077669Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n"); 1087667Ssteve.reinhardt@amd.com } 1097667Ssteve.reinhardt@amd.com} 1107667Ssteve.reinhardt@amd.com 1117667Ssteve.reinhardt@amd.com 1124903SN/Avoid 1134903SN/AMSHR::TargetList::replaceUpgrades() 1144903SN/A{ 1154903SN/A if (!hasUpgrade) 1164903SN/A return; 1174903SN/A 1184903SN/A Iterator end_i = end(); 1194903SN/A for (Iterator i = begin(); i != end_i; ++i) { 1207667Ssteve.reinhardt@amd.com replaceUpgrade(i->pkt); 1214903SN/A } 1224903SN/A 1234903SN/A hasUpgrade = false; 1244903SN/A} 1254903SN/A 1264903SN/A 1272810SN/Avoid 1284908SN/AMSHR::TargetList::clearDownstreamPending() 1294908SN/A{ 1304908SN/A Iterator end_i = end(); 1314908SN/A for (Iterator i = begin(); i != end_i; ++i) { 1325318SN/A if (i->markedPending) { 1335318SN/A MSHR *mshr = dynamic_cast<MSHR*>(i->pkt->senderState); 1345318SN/A if (mshr != NULL) { 1355318SN/A mshr->clearDownstreamPending(); 1365318SN/A } 1374908SN/A } 1384908SN/A } 1394908SN/A} 1404908SN/A 1414908SN/A 1424920SN/Abool 1434920SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt) 1444920SN/A{ 1454920SN/A Iterator end_i = end(); 1464920SN/A for (Iterator i = begin(); i != end_i; ++i) { 1474920SN/A if (pkt->checkFunctional(i->pkt)) { 1484920SN/A return true; 1494920SN/A } 1504920SN/A } 1514920SN/A 1524920SN/A return false; 1534920SN/A} 1544920SN/A 1554920SN/A 1564908SN/Avoid 1575314SN/AMSHR::TargetList:: 1585314SN/Aprint(std::ostream &os, int verbosity, const std::string &prefix) const 1595314SN/A{ 1605314SN/A ConstIterator end_i = end(); 1615314SN/A for (ConstIterator i = begin(); i != end_i; ++i) { 1625875Ssteve.reinhardt@amd.com const char *s; 1635875Ssteve.reinhardt@amd.com switch (i->source) { 1645875Ssteve.reinhardt@amd.com case Target::FromCPU: s = "FromCPU"; 1655875Ssteve.reinhardt@amd.com case Target::FromSnoop: s = "FromSnoop"; 1665875Ssteve.reinhardt@amd.com case Target::FromPrefetcher: s = "FromPrefetcher"; 1675875Ssteve.reinhardt@amd.com default: s = ""; 1685875Ssteve.reinhardt@amd.com } 1695875Ssteve.reinhardt@amd.com ccprintf(os, "%s%s: ", prefix, s); 1705314SN/A i->pkt->print(os, verbosity, ""); 1715314SN/A } 1725314SN/A} 1735314SN/A 1745314SN/A 1755314SN/Avoid 1764666SN/AMSHR::allocate(Addr _addr, int _size, PacketPtr target, 1774871SN/A Tick whenReady, Counter _order) 1782810SN/A{ 1792885SN/A addr = _addr; 1804626SN/A size = _size; 1814871SN/A readyTime = whenReady; 1824666SN/A order = _order; 1834626SN/A assert(target); 1845730SSteve.Reinhardt@amd.com isForward = false; 1854626SN/A _isUncacheable = target->req->isUncacheable(); 1864626SN/A inService = false; 1874908SN/A downstreamPending = false; 1884626SN/A threadNum = 0; 1894626SN/A ntargets = 1; 1905875Ssteve.reinhardt@amd.com assert(targets->isReset()); 1914626SN/A // Don't know of a case where we would allocate a new MSHR for a 1925875Ssteve.reinhardt@amd.com // snoop (mem-side request), so set source according to request here 1935875Ssteve.reinhardt@amd.com Target::Source source = (target->cmd == MemCmd::HardPFReq) ? 1945875Ssteve.reinhardt@amd.com Target::FromPrefetcher : Target::FromCPU; 1955875Ssteve.reinhardt@amd.com targets->add(target, whenReady, _order, source, true); 1964903SN/A assert(deferredTargets->isReset()); 1974668SN/A data = NULL; 1982810SN/A} 1992810SN/A 2004908SN/A 2015318SN/Avoid 2025318SN/AMSHR::clearDownstreamPending() 2035318SN/A{ 2045318SN/A assert(downstreamPending); 2055318SN/A downstreamPending = false; 2065318SN/A // recursively clear flag on any MSHRs we will be forwarding 2075318SN/A // responses to 2085318SN/A targets->clearDownstreamPending(); 2095318SN/A} 2105318SN/A 2114908SN/Abool 2127667Ssteve.reinhardt@amd.comMSHR::markInService(PacketPtr pkt) 2134908SN/A{ 2144908SN/A assert(!inService); 2155730SSteve.Reinhardt@amd.com if (isForwardNoResponse()) { 2164908SN/A // we just forwarded the request packet & don't expect a 2174908SN/A // response, so get rid of it 2184908SN/A assert(getNumTargets() == 1); 2194908SN/A popTarget(); 2204908SN/A return true; 2214908SN/A } 2224908SN/A inService = true; 2237667Ssteve.reinhardt@amd.com pendingDirty = (targets->needsExclusive || 2247667Ssteve.reinhardt@amd.com (!pkt->sharedAsserted() && pkt->memInhibitAsserted())); 2257667Ssteve.reinhardt@amd.com postInvalidate = postDowngrade = false; 2267667Ssteve.reinhardt@amd.com 2274908SN/A if (!downstreamPending) { 2284908SN/A // let upstream caches know that the request has made it to a 2294908SN/A // level where it's going to get a response 2304908SN/A targets->clearDownstreamPending(); 2314908SN/A } 2324908SN/A return false; 2334908SN/A} 2344908SN/A 2354908SN/A 2362810SN/Avoid 2372810SN/AMSHR::deallocate() 2382810SN/A{ 2394903SN/A assert(targets->empty()); 2404903SN/A targets->resetFlags(); 2414903SN/A assert(deferredTargets->isReset()); 2422810SN/A assert(ntargets == 0); 2432810SN/A inService = false; 2442810SN/A} 2452810SN/A 2462810SN/A/* 2472810SN/A * Adds a target to an MSHR 2482810SN/A */ 2492810SN/Avoid 2504903SN/AMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order) 2512810SN/A{ 2524903SN/A // if there's a request already in service for this MSHR, we will 2534903SN/A // have to defer the new target until after the response if any of 2544903SN/A // the following are true: 2554903SN/A // - there are other targets already deferred 2564903SN/A // - there's a pending invalidate to be applied after the response 2574903SN/A // comes back (but before this target is processed) 2587667Ssteve.reinhardt@amd.com // - this target requires an exclusive block and either we're not 2597667Ssteve.reinhardt@amd.com // getting an exclusive block back or we have already snooped 2607667Ssteve.reinhardt@amd.com // another read request that will downgrade our exclusive block 2617667Ssteve.reinhardt@amd.com // to shared 2625875Ssteve.reinhardt@amd.com 2635875Ssteve.reinhardt@amd.com // assume we'd never issue a prefetch when we've got an 2645875Ssteve.reinhardt@amd.com // outstanding miss 2655875Ssteve.reinhardt@amd.com assert(pkt->cmd != MemCmd::HardPFReq); 2665875Ssteve.reinhardt@amd.com 2674903SN/A if (inService && 2687667Ssteve.reinhardt@amd.com (!deferredTargets->empty() || hasPostInvalidate() || 2697667Ssteve.reinhardt@amd.com (pkt->needsExclusive() && 2707667Ssteve.reinhardt@amd.com (!isPendingDirty() || hasPostDowngrade() || isForward)))) { 2714903SN/A // need to put on deferred list 2727667Ssteve.reinhardt@amd.com if (hasPostInvalidate()) 2737667Ssteve.reinhardt@amd.com replaceUpgrade(pkt); 2745875Ssteve.reinhardt@amd.com deferredTargets->add(pkt, whenReady, _order, Target::FromCPU, true); 2754665SN/A } else { 2765318SN/A // No request outstanding, or still OK to append to 2775318SN/A // outstanding request: append to regular target list. Only 2785318SN/A // mark pending if current request hasn't been issued yet 2795318SN/A // (isn't in service). 2805875Ssteve.reinhardt@amd.com targets->add(pkt, whenReady, _order, Target::FromCPU, !inService); 2812810SN/A } 2822810SN/A 2832810SN/A ++ntargets; 2844665SN/A} 2854665SN/A 2864902SN/Abool 2874902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order) 2884665SN/A{ 2894910SN/A if (!inService || (pkt->isExpressSnoop() && downstreamPending)) { 2904903SN/A // Request has not been issued yet, or it's been issued 2914903SN/A // locally but is buffered unissued at some downstream cache 2924903SN/A // which is forwarding us this snoop. Either way, the packet 2934903SN/A // we're snooping logically precedes this MSHR's request, so 2944903SN/A // the snoop has no impact on the MSHR, but must be processed 2954903SN/A // in the standard way by the cache. The only exception is 2964903SN/A // that if we're an L2+ cache buffering an UpgradeReq from a 2974903SN/A // higher-level cache, and the snoop is invalidating, then our 2984903SN/A // buffered upgrades must be converted to read exclusives, 2994903SN/A // since the upper-level cache no longer has a valid copy. 3004903SN/A // That is, even though the upper-level cache got out on its 3014903SN/A // local bus first, some other invalidating transaction 3024903SN/A // reached the global bus before the upgrade did. 3034903SN/A if (pkt->needsExclusive()) { 3044903SN/A targets->replaceUpgrades(); 3054903SN/A deferredTargets->replaceUpgrades(); 3064903SN/A } 3074903SN/A 3084902SN/A return false; 3094902SN/A } 3104665SN/A 3114903SN/A // From here on down, the request issued by this MSHR logically 3124903SN/A // precedes the request we're snooping. 3134903SN/A if (pkt->needsExclusive()) { 3144903SN/A // snooped request still precedes the re-request we'll have to 3154903SN/A // issue for deferred targets, if any... 3164903SN/A deferredTargets->replaceUpgrades(); 3174903SN/A } 3184903SN/A 3197667Ssteve.reinhardt@amd.com if (hasPostInvalidate()) { 3204665SN/A // a prior snoop has already appended an invalidation, so 3214903SN/A // logically we don't have the block anymore; no need for 3224903SN/A // further snooping. 3234902SN/A return true; 3244665SN/A } 3254665SN/A 3267667Ssteve.reinhardt@amd.com if (isPendingDirty() || pkt->isInvalidate()) { 3277667Ssteve.reinhardt@amd.com // We need to save and replay the packet in two cases: 3287667Ssteve.reinhardt@amd.com // 1. We're awaiting an exclusive copy, so ownership is pending, 3297667Ssteve.reinhardt@amd.com // and we need to respond after we receive data. 3307667Ssteve.reinhardt@amd.com // 2. It's an invalidation (e.g., UpgradeReq), and we need 3317667Ssteve.reinhardt@amd.com // to forward the snoop up the hierarchy after the current 3327667Ssteve.reinhardt@amd.com // transaction completes. 3337667Ssteve.reinhardt@amd.com 3348931Sandreas.hansson@arm.com // Actual target device (typ. a memory) will delete the 3357667Ssteve.reinhardt@amd.com // packet on reception, so we need to save a copy here. 3364970SN/A PacketPtr cp_pkt = new Packet(pkt, true); 3377823Ssteve.reinhardt@amd.com targets->add(cp_pkt, curTick(), _order, Target::FromSnoop, 3385318SN/A downstreamPending && targets->needsExclusive); 3394670SN/A ++ntargets; 3404670SN/A 3417667Ssteve.reinhardt@amd.com if (isPendingDirty()) { 3424670SN/A pkt->assertMemInhibit(); 3434916SN/A pkt->setSupplyExclusive(); 3444670SN/A } 3454670SN/A 3464670SN/A if (pkt->needsExclusive()) { 3474670SN/A // This transaction will take away our pending copy 3487667Ssteve.reinhardt@amd.com postInvalidate = true; 3494670SN/A } 3507667Ssteve.reinhardt@amd.com } 3517667Ssteve.reinhardt@amd.com 3527667Ssteve.reinhardt@amd.com if (!pkt->needsExclusive()) { 3537667Ssteve.reinhardt@amd.com // This transaction will get a read-shared copy, downgrading 3547667Ssteve.reinhardt@amd.com // our copy if we had an exclusive one 3557667Ssteve.reinhardt@amd.com postDowngrade = true; 3564670SN/A pkt->assertShared(); 3574667SN/A } 3584902SN/A 3594902SN/A return true; 3604665SN/A} 3614665SN/A 3624665SN/A 3634665SN/Abool 3644665SN/AMSHR::promoteDeferredTargets() 3654665SN/A{ 3664903SN/A assert(targets->empty()); 3674903SN/A if (deferredTargets->empty()) { 3684665SN/A return false; 3694665SN/A } 3704665SN/A 3714903SN/A // swap targets & deferredTargets lists 3724903SN/A TargetList *tmp = targets; 3734665SN/A targets = deferredTargets; 3744903SN/A deferredTargets = tmp; 3752810SN/A 3764903SN/A assert(targets->size() == ntargets); 3774903SN/A 3784903SN/A // clear deferredTargets flags 3794903SN/A deferredTargets->resetFlags(); 3804903SN/A 3814903SN/A order = targets->front().order; 3827823Ssteve.reinhardt@amd.com readyTime = std::max(curTick(), targets->front().readyTime); 3834665SN/A 3844665SN/A return true; 3852810SN/A} 3862810SN/A 3872810SN/A 3882810SN/Avoid 3894670SN/AMSHR::handleFill(Packet *pkt, CacheBlk *blk) 3904668SN/A{ 3917667Ssteve.reinhardt@amd.com if (!pkt->sharedAsserted() 3927667Ssteve.reinhardt@amd.com && !(hasPostInvalidate() || hasPostDowngrade()) 3935270SN/A && deferredTargets->needsExclusive) { 3945270SN/A // We got an exclusive response, but we have deferred targets 3955270SN/A // which are waiting to request an exclusive copy (not because 3965270SN/A // of a pending invalidate). This can happen if the original 3975270SN/A // request was for a read-only (non-exclusive) block, but we 3985270SN/A // got an exclusive copy anyway because of the E part of the 3995270SN/A // MOESI/MESI protocol. Since we got the exclusive copy 4005270SN/A // there's no need to defer the targets, so move them up to 4015270SN/A // the regular target list. 4025270SN/A assert(!targets->needsExclusive); 4035270SN/A targets->needsExclusive = true; 4045318SN/A // if any of the deferred targets were upper-level cache 4055318SN/A // requests marked downstreamPending, need to clear that 4065318SN/A assert(!downstreamPending); // not pending here anymore 4075318SN/A deferredTargets->clearDownstreamPending(); 4085270SN/A // this clears out deferredTargets too 4095270SN/A targets->splice(targets->end(), *deferredTargets); 4105270SN/A deferredTargets->resetFlags(); 4115270SN/A } 4124668SN/A} 4134668SN/A 4144668SN/A 4155314SN/Abool 4165314SN/AMSHR::checkFunctional(PacketPtr pkt) 4175314SN/A{ 4185314SN/A // For printing, we treat the MSHR as a whole as single entity. 4195314SN/A // For other requests, we iterate over the individual targets 4205314SN/A // since that's where the actual data lies. 4215314SN/A if (pkt->isPrint()) { 4225314SN/A pkt->checkFunctional(this, addr, size, NULL); 4235314SN/A return false; 4245314SN/A } else { 4255314SN/A return (targets->checkFunctional(pkt) || 4265314SN/A deferredTargets->checkFunctional(pkt)); 4275314SN/A } 4285314SN/A} 4295314SN/A 4305314SN/A 4314668SN/Avoid 4325314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const 4332810SN/A{ 4345314SN/A ccprintf(os, "%s[%x:%x] %s %s %s state: %s %s %s %s\n", 4355314SN/A prefix, addr, addr+size-1, 4365730SSteve.Reinhardt@amd.com isForward ? "Forward" : "", 4375730SSteve.Reinhardt@amd.com isForwardNoResponse() ? "ForwNoResp" : "", 4385314SN/A needsExclusive() ? "Excl" : "", 4395314SN/A _isUncacheable ? "Unc" : "", 4405314SN/A inService ? "InSvc" : "", 4415314SN/A downstreamPending ? "DwnPend" : "", 4427667Ssteve.reinhardt@amd.com hasPostInvalidate() ? "PostInv" : "", 4437667Ssteve.reinhardt@amd.com hasPostDowngrade() ? "PostDowngr" : ""); 4442810SN/A 4455314SN/A ccprintf(os, "%s Targets:\n", prefix); 4465314SN/A targets->print(os, verbosity, prefix + " "); 4475314SN/A if (!deferredTargets->empty()) { 4485314SN/A ccprintf(os, "%s Deferred Targets:\n", prefix); 4495314SN/A deferredTargets->print(os, verbosity, prefix + " "); 4502810SN/A } 4512810SN/A} 4522810SN/A 4532810SN/AMSHR::~MSHR() 4542810SN/A{ 4552810SN/A} 456