mshr.cc revision 7669
12810SN/A/* 22810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 37636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc. 42810SN/A * All rights reserved. 52810SN/A * 62810SN/A * Redistribution and use in source and binary forms, with or without 72810SN/A * modification, are permitted provided that the following conditions are 82810SN/A * met: redistributions of source code must retain the above copyright 92810SN/A * notice, this list of conditions and the following disclaimer; 102810SN/A * redistributions in binary form must reproduce the above copyright 112810SN/A * notice, this list of conditions and the following disclaimer in the 122810SN/A * documentation and/or other materials provided with the distribution; 132810SN/A * neither the name of the copyright holders nor the names of its 142810SN/A * contributors may be used to endorse or promote products derived from 152810SN/A * this software without specific prior written permission. 162810SN/A * 172810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282810SN/A * 292810SN/A * Authors: Erik Hallnor 302810SN/A * Dave Greene 312810SN/A */ 322810SN/A 332810SN/A/** 342810SN/A * @file 352810SN/A * Miss Status and Handling Register (MSHR) definitions. 362810SN/A */ 372810SN/A 386216Snate@binkert.org#include <algorithm> 396216Snate@binkert.org#include <cassert> 402810SN/A#include <string> 412810SN/A#include <vector> 422810SN/A 436216Snate@binkert.org#include "base/misc.hh" 446216Snate@binkert.org#include "base/types.hh" 456216Snate@binkert.org#include "mem/cache/cache.hh" 465338Sstever@gmail.com#include "mem/cache/mshr.hh" 476216Snate@binkert.org#include "sim/core.hh" 482810SN/A 492810SN/Ausing namespace std; 502810SN/A 512810SN/AMSHR::MSHR() 522810SN/A{ 532810SN/A inService = false; 542810SN/A ntargets = 0; 556221Snate@binkert.org threadNum = InvalidThreadID; 564903SN/A targets = new TargetList(); 574903SN/A deferredTargets = new TargetList(); 582810SN/A} 592810SN/A 604903SN/A 614903SN/AMSHR::TargetList::TargetList() 624903SN/A : needsExclusive(false), hasUpgrade(false) 634903SN/A{} 644903SN/A 654903SN/A 664903SN/Ainline void 674908SN/AMSHR::TargetList::add(PacketPtr pkt, Tick readyTime, 685875Ssteve.reinhardt@amd.com Counter order, Target::Source source, bool markPending) 694903SN/A{ 705875Ssteve.reinhardt@amd.com if (source != Target::FromSnoop) { 714903SN/A if (pkt->needsExclusive()) { 724903SN/A needsExclusive = true; 734903SN/A } 744903SN/A 757669Ssteve.reinhardt@amd.com // StoreCondReq is effectively an upgrade if it's in an MSHR 767669Ssteve.reinhardt@amd.com // since it would have been failed already if we didn't have a 777669Ssteve.reinhardt@amd.com // read-only copy 787669Ssteve.reinhardt@amd.com if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) { 794903SN/A hasUpgrade = true; 804903SN/A } 815318SN/A } 824908SN/A 835318SN/A if (markPending) { 844908SN/A MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState); 854908SN/A if (mshr != NULL) { 864908SN/A assert(!mshr->downstreamPending); 874908SN/A mshr->downstreamPending = true; 884908SN/A } 894903SN/A } 904903SN/A 915875Ssteve.reinhardt@amd.com push_back(Target(pkt, readyTime, order, source, markPending)); 924903SN/A} 934903SN/A 944903SN/A 957667Ssteve.reinhardt@amd.comstatic void 967667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt) 977667Ssteve.reinhardt@amd.com{ 987667Ssteve.reinhardt@amd.com if (pkt->cmd == MemCmd::UpgradeReq) { 997667Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::ReadExReq; 1007667Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n"); 1017667Ssteve.reinhardt@amd.com } else if (pkt->cmd == MemCmd::SCUpgradeReq) { 1027667Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::SCUpgradeFailReq; 1037667Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n"); 1047669Ssteve.reinhardt@amd.com } else if (pkt->cmd == MemCmd::StoreCondReq) { 1057669Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::StoreCondFailReq; 1067669Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n"); 1077667Ssteve.reinhardt@amd.com } 1087667Ssteve.reinhardt@amd.com} 1097667Ssteve.reinhardt@amd.com 1107667Ssteve.reinhardt@amd.com 1114903SN/Avoid 1124903SN/AMSHR::TargetList::replaceUpgrades() 1134903SN/A{ 1144903SN/A if (!hasUpgrade) 1154903SN/A return; 1164903SN/A 1174903SN/A Iterator end_i = end(); 1184903SN/A for (Iterator i = begin(); i != end_i; ++i) { 1197667Ssteve.reinhardt@amd.com replaceUpgrade(i->pkt); 1204903SN/A } 1214903SN/A 1224903SN/A hasUpgrade = false; 1234903SN/A} 1244903SN/A 1254903SN/A 1262810SN/Avoid 1274908SN/AMSHR::TargetList::clearDownstreamPending() 1284908SN/A{ 1294908SN/A Iterator end_i = end(); 1304908SN/A for (Iterator i = begin(); i != end_i; ++i) { 1315318SN/A if (i->markedPending) { 1325318SN/A MSHR *mshr = dynamic_cast<MSHR*>(i->pkt->senderState); 1335318SN/A if (mshr != NULL) { 1345318SN/A mshr->clearDownstreamPending(); 1355318SN/A } 1364908SN/A } 1374908SN/A } 1384908SN/A} 1394908SN/A 1404908SN/A 1414920SN/Abool 1424920SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt) 1434920SN/A{ 1444920SN/A Iterator end_i = end(); 1454920SN/A for (Iterator i = begin(); i != end_i; ++i) { 1464920SN/A if (pkt->checkFunctional(i->pkt)) { 1474920SN/A return true; 1484920SN/A } 1494920SN/A } 1504920SN/A 1514920SN/A return false; 1524920SN/A} 1534920SN/A 1544920SN/A 1554908SN/Avoid 1565314SN/AMSHR::TargetList:: 1575314SN/Aprint(std::ostream &os, int verbosity, const std::string &prefix) const 1585314SN/A{ 1595314SN/A ConstIterator end_i = end(); 1605314SN/A for (ConstIterator i = begin(); i != end_i; ++i) { 1615875Ssteve.reinhardt@amd.com const char *s; 1625875Ssteve.reinhardt@amd.com switch (i->source) { 1635875Ssteve.reinhardt@amd.com case Target::FromCPU: s = "FromCPU"; 1645875Ssteve.reinhardt@amd.com case Target::FromSnoop: s = "FromSnoop"; 1655875Ssteve.reinhardt@amd.com case Target::FromPrefetcher: s = "FromPrefetcher"; 1665875Ssteve.reinhardt@amd.com default: s = ""; 1675875Ssteve.reinhardt@amd.com } 1685875Ssteve.reinhardt@amd.com ccprintf(os, "%s%s: ", prefix, s); 1695314SN/A i->pkt->print(os, verbosity, ""); 1705314SN/A } 1715314SN/A} 1725314SN/A 1735314SN/A 1745314SN/Avoid 1754666SN/AMSHR::allocate(Addr _addr, int _size, PacketPtr target, 1764871SN/A Tick whenReady, Counter _order) 1772810SN/A{ 1782885SN/A addr = _addr; 1794626SN/A size = _size; 1804871SN/A readyTime = whenReady; 1814666SN/A order = _order; 1824626SN/A assert(target); 1835730SSteve.Reinhardt@amd.com isForward = false; 1844626SN/A _isUncacheable = target->req->isUncacheable(); 1854626SN/A inService = false; 1864908SN/A downstreamPending = false; 1874626SN/A threadNum = 0; 1884626SN/A ntargets = 1; 1895875Ssteve.reinhardt@amd.com assert(targets->isReset()); 1904626SN/A // Don't know of a case where we would allocate a new MSHR for a 1915875Ssteve.reinhardt@amd.com // snoop (mem-side request), so set source according to request here 1925875Ssteve.reinhardt@amd.com Target::Source source = (target->cmd == MemCmd::HardPFReq) ? 1935875Ssteve.reinhardt@amd.com Target::FromPrefetcher : Target::FromCPU; 1945875Ssteve.reinhardt@amd.com targets->add(target, whenReady, _order, source, true); 1954903SN/A assert(deferredTargets->isReset()); 1964668SN/A data = NULL; 1972810SN/A} 1982810SN/A 1994908SN/A 2005318SN/Avoid 2015318SN/AMSHR::clearDownstreamPending() 2025318SN/A{ 2035318SN/A assert(downstreamPending); 2045318SN/A downstreamPending = false; 2055318SN/A // recursively clear flag on any MSHRs we will be forwarding 2065318SN/A // responses to 2075318SN/A targets->clearDownstreamPending(); 2085318SN/A} 2095318SN/A 2104908SN/Abool 2117667Ssteve.reinhardt@amd.comMSHR::markInService(PacketPtr pkt) 2124908SN/A{ 2134908SN/A assert(!inService); 2145730SSteve.Reinhardt@amd.com if (isForwardNoResponse()) { 2154908SN/A // we just forwarded the request packet & don't expect a 2164908SN/A // response, so get rid of it 2174908SN/A assert(getNumTargets() == 1); 2184908SN/A popTarget(); 2194908SN/A return true; 2204908SN/A } 2214908SN/A inService = true; 2227667Ssteve.reinhardt@amd.com pendingDirty = (targets->needsExclusive || 2237667Ssteve.reinhardt@amd.com (!pkt->sharedAsserted() && pkt->memInhibitAsserted())); 2247667Ssteve.reinhardt@amd.com postInvalidate = postDowngrade = false; 2257667Ssteve.reinhardt@amd.com 2264908SN/A if (!downstreamPending) { 2274908SN/A // let upstream caches know that the request has made it to a 2284908SN/A // level where it's going to get a response 2294908SN/A targets->clearDownstreamPending(); 2304908SN/A } 2314908SN/A return false; 2324908SN/A} 2334908SN/A 2344908SN/A 2352810SN/Avoid 2362810SN/AMSHR::deallocate() 2372810SN/A{ 2384903SN/A assert(targets->empty()); 2394903SN/A targets->resetFlags(); 2404903SN/A assert(deferredTargets->isReset()); 2412810SN/A assert(ntargets == 0); 2422810SN/A inService = false; 2432810SN/A} 2442810SN/A 2452810SN/A/* 2462810SN/A * Adds a target to an MSHR 2472810SN/A */ 2482810SN/Avoid 2494903SN/AMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order) 2502810SN/A{ 2514903SN/A // if there's a request already in service for this MSHR, we will 2524903SN/A // have to defer the new target until after the response if any of 2534903SN/A // the following are true: 2544903SN/A // - there are other targets already deferred 2554903SN/A // - there's a pending invalidate to be applied after the response 2564903SN/A // comes back (but before this target is processed) 2577667Ssteve.reinhardt@amd.com // - this target requires an exclusive block and either we're not 2587667Ssteve.reinhardt@amd.com // getting an exclusive block back or we have already snooped 2597667Ssteve.reinhardt@amd.com // another read request that will downgrade our exclusive block 2607667Ssteve.reinhardt@amd.com // to shared 2615875Ssteve.reinhardt@amd.com 2625875Ssteve.reinhardt@amd.com // assume we'd never issue a prefetch when we've got an 2635875Ssteve.reinhardt@amd.com // outstanding miss 2645875Ssteve.reinhardt@amd.com assert(pkt->cmd != MemCmd::HardPFReq); 2655875Ssteve.reinhardt@amd.com 2664903SN/A if (inService && 2677667Ssteve.reinhardt@amd.com (!deferredTargets->empty() || hasPostInvalidate() || 2687667Ssteve.reinhardt@amd.com (pkt->needsExclusive() && 2697667Ssteve.reinhardt@amd.com (!isPendingDirty() || hasPostDowngrade() || isForward)))) { 2704903SN/A // need to put on deferred list 2717667Ssteve.reinhardt@amd.com if (hasPostInvalidate()) 2727667Ssteve.reinhardt@amd.com replaceUpgrade(pkt); 2735875Ssteve.reinhardt@amd.com deferredTargets->add(pkt, whenReady, _order, Target::FromCPU, true); 2744665SN/A } else { 2755318SN/A // No request outstanding, or still OK to append to 2765318SN/A // outstanding request: append to regular target list. Only 2775318SN/A // mark pending if current request hasn't been issued yet 2785318SN/A // (isn't in service). 2795875Ssteve.reinhardt@amd.com targets->add(pkt, whenReady, _order, Target::FromCPU, !inService); 2802810SN/A } 2812810SN/A 2822810SN/A ++ntargets; 2834665SN/A} 2844665SN/A 2854902SN/Abool 2864902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order) 2874665SN/A{ 2884910SN/A if (!inService || (pkt->isExpressSnoop() && downstreamPending)) { 2894903SN/A // Request has not been issued yet, or it's been issued 2904903SN/A // locally but is buffered unissued at some downstream cache 2914903SN/A // which is forwarding us this snoop. Either way, the packet 2924903SN/A // we're snooping logically precedes this MSHR's request, so 2934903SN/A // the snoop has no impact on the MSHR, but must be processed 2944903SN/A // in the standard way by the cache. The only exception is 2954903SN/A // that if we're an L2+ cache buffering an UpgradeReq from a 2964903SN/A // higher-level cache, and the snoop is invalidating, then our 2974903SN/A // buffered upgrades must be converted to read exclusives, 2984903SN/A // since the upper-level cache no longer has a valid copy. 2994903SN/A // That is, even though the upper-level cache got out on its 3004903SN/A // local bus first, some other invalidating transaction 3014903SN/A // reached the global bus before the upgrade did. 3024903SN/A if (pkt->needsExclusive()) { 3034903SN/A targets->replaceUpgrades(); 3044903SN/A deferredTargets->replaceUpgrades(); 3054903SN/A } 3064903SN/A 3074902SN/A return false; 3084902SN/A } 3094665SN/A 3104903SN/A // From here on down, the request issued by this MSHR logically 3114903SN/A // precedes the request we're snooping. 3124903SN/A if (pkt->needsExclusive()) { 3134903SN/A // snooped request still precedes the re-request we'll have to 3144903SN/A // issue for deferred targets, if any... 3154903SN/A deferredTargets->replaceUpgrades(); 3164903SN/A } 3174903SN/A 3187667Ssteve.reinhardt@amd.com if (hasPostInvalidate()) { 3194665SN/A // a prior snoop has already appended an invalidation, so 3204903SN/A // logically we don't have the block anymore; no need for 3214903SN/A // further snooping. 3224902SN/A return true; 3234665SN/A } 3244665SN/A 3257667Ssteve.reinhardt@amd.com if (isPendingDirty() || pkt->isInvalidate()) { 3267667Ssteve.reinhardt@amd.com // We need to save and replay the packet in two cases: 3277667Ssteve.reinhardt@amd.com // 1. We're awaiting an exclusive copy, so ownership is pending, 3287667Ssteve.reinhardt@amd.com // and we need to respond after we receive data. 3297667Ssteve.reinhardt@amd.com // 2. It's an invalidation (e.g., UpgradeReq), and we need 3307667Ssteve.reinhardt@amd.com // to forward the snoop up the hierarchy after the current 3317667Ssteve.reinhardt@amd.com // transaction completes. 3327667Ssteve.reinhardt@amd.com 3337667Ssteve.reinhardt@amd.com // Actual target device (typ. PhysicalMemory) will delete the 3347667Ssteve.reinhardt@amd.com // packet on reception, so we need to save a copy here. 3354970SN/A PacketPtr cp_pkt = new Packet(pkt, true); 3365875Ssteve.reinhardt@amd.com targets->add(cp_pkt, curTick, _order, Target::FromSnoop, 3375318SN/A downstreamPending && targets->needsExclusive); 3384670SN/A ++ntargets; 3394670SN/A 3407667Ssteve.reinhardt@amd.com if (isPendingDirty()) { 3414670SN/A pkt->assertMemInhibit(); 3424916SN/A pkt->setSupplyExclusive(); 3434670SN/A } 3444670SN/A 3454670SN/A if (pkt->needsExclusive()) { 3464670SN/A // This transaction will take away our pending copy 3477667Ssteve.reinhardt@amd.com postInvalidate = true; 3484670SN/A } 3497667Ssteve.reinhardt@amd.com } 3507667Ssteve.reinhardt@amd.com 3517667Ssteve.reinhardt@amd.com if (!pkt->needsExclusive()) { 3527667Ssteve.reinhardt@amd.com // This transaction will get a read-shared copy, downgrading 3537667Ssteve.reinhardt@amd.com // our copy if we had an exclusive one 3547667Ssteve.reinhardt@amd.com postDowngrade = true; 3554670SN/A pkt->assertShared(); 3564667SN/A } 3574902SN/A 3584902SN/A return true; 3594665SN/A} 3604665SN/A 3614665SN/A 3624665SN/Abool 3634665SN/AMSHR::promoteDeferredTargets() 3644665SN/A{ 3654903SN/A assert(targets->empty()); 3664903SN/A if (deferredTargets->empty()) { 3674665SN/A return false; 3684665SN/A } 3694665SN/A 3704903SN/A // swap targets & deferredTargets lists 3714903SN/A TargetList *tmp = targets; 3724665SN/A targets = deferredTargets; 3734903SN/A deferredTargets = tmp; 3742810SN/A 3754903SN/A assert(targets->size() == ntargets); 3764903SN/A 3774903SN/A // clear deferredTargets flags 3784903SN/A deferredTargets->resetFlags(); 3794903SN/A 3804903SN/A order = targets->front().order; 3814903SN/A readyTime = std::max(curTick, targets->front().readyTime); 3824665SN/A 3834665SN/A return true; 3842810SN/A} 3852810SN/A 3862810SN/A 3872810SN/Avoid 3884670SN/AMSHR::handleFill(Packet *pkt, CacheBlk *blk) 3894668SN/A{ 3907667Ssteve.reinhardt@amd.com if (!pkt->sharedAsserted() 3917667Ssteve.reinhardt@amd.com && !(hasPostInvalidate() || hasPostDowngrade()) 3925270SN/A && deferredTargets->needsExclusive) { 3935270SN/A // We got an exclusive response, but we have deferred targets 3945270SN/A // which are waiting to request an exclusive copy (not because 3955270SN/A // of a pending invalidate). This can happen if the original 3965270SN/A // request was for a read-only (non-exclusive) block, but we 3975270SN/A // got an exclusive copy anyway because of the E part of the 3985270SN/A // MOESI/MESI protocol. Since we got the exclusive copy 3995270SN/A // there's no need to defer the targets, so move them up to 4005270SN/A // the regular target list. 4015270SN/A assert(!targets->needsExclusive); 4025270SN/A targets->needsExclusive = true; 4035318SN/A // if any of the deferred targets were upper-level cache 4045318SN/A // requests marked downstreamPending, need to clear that 4055318SN/A assert(!downstreamPending); // not pending here anymore 4065318SN/A deferredTargets->clearDownstreamPending(); 4075270SN/A // this clears out deferredTargets too 4085270SN/A targets->splice(targets->end(), *deferredTargets); 4095270SN/A deferredTargets->resetFlags(); 4105270SN/A } 4114668SN/A} 4124668SN/A 4134668SN/A 4145314SN/Abool 4155314SN/AMSHR::checkFunctional(PacketPtr pkt) 4165314SN/A{ 4175314SN/A // For printing, we treat the MSHR as a whole as single entity. 4185314SN/A // For other requests, we iterate over the individual targets 4195314SN/A // since that's where the actual data lies. 4205314SN/A if (pkt->isPrint()) { 4215314SN/A pkt->checkFunctional(this, addr, size, NULL); 4225314SN/A return false; 4235314SN/A } else { 4245314SN/A return (targets->checkFunctional(pkt) || 4255314SN/A deferredTargets->checkFunctional(pkt)); 4265314SN/A } 4275314SN/A} 4285314SN/A 4295314SN/A 4304668SN/Avoid 4315314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const 4322810SN/A{ 4335314SN/A ccprintf(os, "%s[%x:%x] %s %s %s state: %s %s %s %s\n", 4345314SN/A prefix, addr, addr+size-1, 4355730SSteve.Reinhardt@amd.com isForward ? "Forward" : "", 4365730SSteve.Reinhardt@amd.com isForwardNoResponse() ? "ForwNoResp" : "", 4375314SN/A needsExclusive() ? "Excl" : "", 4385314SN/A _isUncacheable ? "Unc" : "", 4395314SN/A inService ? "InSvc" : "", 4405314SN/A downstreamPending ? "DwnPend" : "", 4417667Ssteve.reinhardt@amd.com hasPostInvalidate() ? "PostInv" : "", 4427667Ssteve.reinhardt@amd.com hasPostDowngrade() ? "PostDowngr" : ""); 4432810SN/A 4445314SN/A ccprintf(os, "%s Targets:\n", prefix); 4455314SN/A targets->print(os, verbosity, prefix + " "); 4465314SN/A if (!deferredTargets->empty()) { 4475314SN/A ccprintf(os, "%s Deferred Targets:\n", prefix); 4485314SN/A deferredTargets->print(os, verbosity, prefix + " "); 4492810SN/A } 4502810SN/A} 4512810SN/A 4522810SN/AMSHR::~MSHR() 4532810SN/A{ 4542810SN/A} 455