mshr.cc revision 13861
17405SAli.Saidi@ARM.com/*
211573SDylan.Johnson@ARM.com * Copyright (c) 2012-2013, 2015-2019 ARM Limited
37405SAli.Saidi@ARM.com * All rights reserved.
47405SAli.Saidi@ARM.com *
57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall
67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual
77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating
87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software
97405SAli.Saidi@ARM.com * licensed hereunder.  You may use the software subject to the license
107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated
117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software,
127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form.
137405SAli.Saidi@ARM.com *
147405SAli.Saidi@ARM.com * Copyright (c) 2002-2005 The Regents of The University of Michigan
157405SAli.Saidi@ARM.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
167405SAli.Saidi@ARM.com * All rights reserved.
177405SAli.Saidi@ARM.com *
187405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without
197405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are
207405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright
217405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer;
227405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright
237405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the
247405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution;
257405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its
267405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from
277405SAli.Saidi@ARM.com * this software without specific prior written permission.
287405SAli.Saidi@ARM.com *
297405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
307405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
317405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
327405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
337405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
347405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
357405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
367405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
377405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
387405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
397405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
407405SAli.Saidi@ARM.com *
417405SAli.Saidi@ARM.com * Authors: Erik Hallnor
4211793Sbrandon.potter@amd.com *          Dave Greene
4310461SAndreas.Sandberg@ARM.com *          Nikos Nikoleris
449050Schander.sudanthi@arm.com */
4511793Sbrandon.potter@amd.com
468887Sgeoffrey.blake@arm.com/**
478232Snate@binkert.org * @file
488232Snate@binkert.org * Miss Status and Handling Register (MSHR) definitions.
4910844Sandreas.sandberg@arm.com */
509384SAndreas.Sandberg@arm.com
517678Sgblack@eecs.umich.edu#include "mem/cache/mshr.hh"
528059SAli.Saidi@ARM.com
538284SAli.Saidi@ARM.com#include <cassert>
547405SAli.Saidi@ARM.com#include <string>
557405SAli.Saidi@ARM.com
567405SAli.Saidi@ARM.com#include "base/logging.hh"
577405SAli.Saidi@ARM.com#include "base/trace.hh"
5810037SARM gem5 Developers#include "base/types.hh"
5910037SARM gem5 Developers#include "debug/Cache.hh"
6011768SCurtis.Dunham@arm.com#include "mem/cache/base.hh"
6110037SARM gem5 Developers#include "mem/request.hh"
6210037SARM gem5 Developers#include "sim/core.hh"
6310037SARM gem5 Developers
6410037SARM gem5 DevelopersMSHR::MSHR() : downstreamPending(false),
6511768SCurtis.Dunham@arm.com               pendingModified(false),
6610037SARM gem5 Developers               postInvalidate(false), postDowngrade(false),
6710037SARM gem5 Developers               wasWholeLineWrite(false), isForward(false)
6811768SCurtis.Dunham@arm.com{
6911768SCurtis.Dunham@arm.com}
7011768SCurtis.Dunham@arm.com
7111768SCurtis.Dunham@arm.comMSHR::TargetList::TargetList()
7211768SCurtis.Dunham@arm.com    : needsWritable(false), hasUpgrade(false), allocOnFill(false),
7311768SCurtis.Dunham@arm.com      hasFromCache(false)
7411768SCurtis.Dunham@arm.com{}
7511768SCurtis.Dunham@arm.com
7611768SCurtis.Dunham@arm.com
7711768SCurtis.Dunham@arm.comvoid
7811768SCurtis.Dunham@arm.comMSHR::TargetList::updateFlags(PacketPtr pkt, Target::Source source,
7911768SCurtis.Dunham@arm.com                              bool alloc_on_fill)
8010037SARM gem5 Developers{
8110037SARM gem5 Developers    if (source != Target::FromSnoop) {
8210037SARM gem5 Developers        if (pkt->needsWritable()) {
8311768SCurtis.Dunham@arm.com            needsWritable = true;
8411768SCurtis.Dunham@arm.com        }
8511768SCurtis.Dunham@arm.com
8611768SCurtis.Dunham@arm.com        // StoreCondReq is effectively an upgrade if it's in an MSHR
8711768SCurtis.Dunham@arm.com        // since it would have been failed already if we didn't have a
8811768SCurtis.Dunham@arm.com        // read-only copy
8911768SCurtis.Dunham@arm.com        if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
9011768SCurtis.Dunham@arm.com            hasUpgrade = true;
9110037SARM gem5 Developers        }
9211768SCurtis.Dunham@arm.com
9311768SCurtis.Dunham@arm.com        // potentially re-evaluate whether we should allocate on a fill or
9411768SCurtis.Dunham@arm.com        // not
9511768SCurtis.Dunham@arm.com        allocOnFill = allocOnFill || alloc_on_fill;
9610037SARM gem5 Developers
9711768SCurtis.Dunham@arm.com        if (source != Target::FromPrefetcher) {
9811768SCurtis.Dunham@arm.com            hasFromCache = hasFromCache || pkt->fromCache();
9911768SCurtis.Dunham@arm.com
10011768SCurtis.Dunham@arm.com            updateWriteFlags(pkt);
10111768SCurtis.Dunham@arm.com        }
10211768SCurtis.Dunham@arm.com    }
10311768SCurtis.Dunham@arm.com}
10411768SCurtis.Dunham@arm.com
10511768SCurtis.Dunham@arm.comvoid
10611768SCurtis.Dunham@arm.comMSHR::TargetList::populateFlags()
10711768SCurtis.Dunham@arm.com{
10811768SCurtis.Dunham@arm.com    resetFlags();
10911768SCurtis.Dunham@arm.com    for (auto& t: *this) {
11011768SCurtis.Dunham@arm.com        updateFlags(t.pkt, t.source, t.allocOnFill);
11111768SCurtis.Dunham@arm.com    }
11211768SCurtis.Dunham@arm.com}
11311768SCurtis.Dunham@arm.com
11411768SCurtis.Dunham@arm.cominline void
11510037SARM gem5 DevelopersMSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
11611768SCurtis.Dunham@arm.com                      Counter order, Target::Source source, bool markPending,
11711768SCurtis.Dunham@arm.com                      bool alloc_on_fill)
11811768SCurtis.Dunham@arm.com{
11911768SCurtis.Dunham@arm.com    updateFlags(pkt, source, alloc_on_fill);
12010037SARM gem5 Developers    if (markPending) {
12111768SCurtis.Dunham@arm.com        // Iterate over the SenderState stack and see if we find
12211768SCurtis.Dunham@arm.com        // an MSHR entry. If we do, set the downstreamPending
12311768SCurtis.Dunham@arm.com        // flag. Otherwise, do nothing.
12411768SCurtis.Dunham@arm.com        MSHR *mshr = pkt->findNextSenderState<MSHR>();
12511768SCurtis.Dunham@arm.com        if (mshr != nullptr) {
12611768SCurtis.Dunham@arm.com            assert(!mshr->downstreamPending);
12710037SARM gem5 Developers            mshr->downstreamPending = true;
12811768SCurtis.Dunham@arm.com        } else {
12911768SCurtis.Dunham@arm.com            // No need to clear downstreamPending later
13011768SCurtis.Dunham@arm.com            markPending = false;
13111768SCurtis.Dunham@arm.com        }
13211768SCurtis.Dunham@arm.com    }
13311768SCurtis.Dunham@arm.com
13411768SCurtis.Dunham@arm.com    emplace_back(pkt, readyTime, order, source, markPending, alloc_on_fill);
13511768SCurtis.Dunham@arm.com}
13611768SCurtis.Dunham@arm.com
13711768SCurtis.Dunham@arm.com
13811768SCurtis.Dunham@arm.comstatic void
13911768SCurtis.Dunham@arm.comreplaceUpgrade(PacketPtr pkt)
14011768SCurtis.Dunham@arm.com{
14111768SCurtis.Dunham@arm.com    // remember if the current packet has data allocated
14211768SCurtis.Dunham@arm.com    bool has_data = pkt->hasData() || pkt->hasRespData();
14311768SCurtis.Dunham@arm.com
14411768SCurtis.Dunham@arm.com    if (pkt->cmd == MemCmd::UpgradeReq) {
14511768SCurtis.Dunham@arm.com        pkt->cmd = MemCmd::ReadExReq;
14611768SCurtis.Dunham@arm.com        DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
14711768SCurtis.Dunham@arm.com    } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
14811768SCurtis.Dunham@arm.com        pkt->cmd = MemCmd::SCUpgradeFailReq;
14911768SCurtis.Dunham@arm.com        DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
15011768SCurtis.Dunham@arm.com    } else if (pkt->cmd == MemCmd::StoreCondReq) {
15111768SCurtis.Dunham@arm.com        pkt->cmd = MemCmd::StoreCondFailReq;
15211768SCurtis.Dunham@arm.com        DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
15311768SCurtis.Dunham@arm.com    }
15411768SCurtis.Dunham@arm.com
15511768SCurtis.Dunham@arm.com    if (!has_data) {
15611768SCurtis.Dunham@arm.com        // there is no sensible way of setting the data field if the
15711768SCurtis.Dunham@arm.com        // new command actually would carry data
15811768SCurtis.Dunham@arm.com        assert(!pkt->hasData());
15911768SCurtis.Dunham@arm.com
16011768SCurtis.Dunham@arm.com        if (pkt->hasRespData()) {
16111768SCurtis.Dunham@arm.com            // we went from a packet that had no data (neither request,
16211768SCurtis.Dunham@arm.com            // nor response), to one that does, and therefore we need to
16311768SCurtis.Dunham@arm.com            // actually allocate space for the data payload
16411768SCurtis.Dunham@arm.com            pkt->allocate();
16511768SCurtis.Dunham@arm.com        }
16611768SCurtis.Dunham@arm.com    }
16711768SCurtis.Dunham@arm.com}
16811768SCurtis.Dunham@arm.com
16911768SCurtis.Dunham@arm.com
17011768SCurtis.Dunham@arm.comvoid
17111768SCurtis.Dunham@arm.comMSHR::TargetList::replaceUpgrades()
17211768SCurtis.Dunham@arm.com{
17311768SCurtis.Dunham@arm.com    if (!hasUpgrade)
17411768SCurtis.Dunham@arm.com        return;
17511768SCurtis.Dunham@arm.com
17611768SCurtis.Dunham@arm.com    for (auto& t : *this) {
17711768SCurtis.Dunham@arm.com        replaceUpgrade(t.pkt);
17811768SCurtis.Dunham@arm.com    }
17911768SCurtis.Dunham@arm.com
18011768SCurtis.Dunham@arm.com    hasUpgrade = false;
18111768SCurtis.Dunham@arm.com}
18211768SCurtis.Dunham@arm.com
18311768SCurtis.Dunham@arm.com
18411768SCurtis.Dunham@arm.comvoid
18511768SCurtis.Dunham@arm.comMSHR::TargetList::clearDownstreamPending(MSHR::TargetList::iterator begin,
18611768SCurtis.Dunham@arm.com                                         MSHR::TargetList::iterator end)
18711768SCurtis.Dunham@arm.com{
18811768SCurtis.Dunham@arm.com    for (auto t = begin; t != end; t++) {
18911768SCurtis.Dunham@arm.com        if (t->markedPending) {
19011768SCurtis.Dunham@arm.com            // Iterate over the SenderState stack and see if we find
19111768SCurtis.Dunham@arm.com            // an MSHR entry. If we find one, clear the
19211768SCurtis.Dunham@arm.com            // downstreamPending flag by calling
19311768SCurtis.Dunham@arm.com            // clearDownstreamPending(). This recursively clears the
19411768SCurtis.Dunham@arm.com            // downstreamPending flag in all caches this packet has
19511768SCurtis.Dunham@arm.com            // passed through.
19611768SCurtis.Dunham@arm.com            MSHR *mshr = t->pkt->findNextSenderState<MSHR>();
19711768SCurtis.Dunham@arm.com            if (mshr != nullptr) {
19811768SCurtis.Dunham@arm.com                mshr->clearDownstreamPending();
19911768SCurtis.Dunham@arm.com            }
20011768SCurtis.Dunham@arm.com            t->markedPending = false;
20111768SCurtis.Dunham@arm.com        }
20211768SCurtis.Dunham@arm.com    }
20311768SCurtis.Dunham@arm.com}
20411768SCurtis.Dunham@arm.com
20510037SARM gem5 Developersvoid
20610037SARM gem5 DevelopersMSHR::TargetList::clearDownstreamPending()
20710037SARM gem5 Developers{
2089384SAndreas.Sandberg@arm.com    clearDownstreamPending(begin(), end());
20910461SAndreas.Sandberg@ARM.com}
21010461SAndreas.Sandberg@ARM.com
21111165SRekai.GonzalezAlberquilla@arm.com
21210461SAndreas.Sandberg@ARM.combool
21310461SAndreas.Sandberg@ARM.comMSHR::TargetList::trySatisfyFunctional(PacketPtr pkt)
2149384SAndreas.Sandberg@arm.com{
21511770SCurtis.Dunham@arm.com    for (auto& t : *this) {
21610037SARM gem5 Developers        if (pkt->trySatisfyFunctional(t.pkt)) {
21710461SAndreas.Sandberg@ARM.com            return true;
21810461SAndreas.Sandberg@ARM.com        }
21910461SAndreas.Sandberg@ARM.com    }
22010461SAndreas.Sandberg@ARM.com
22110461SAndreas.Sandberg@ARM.com    return false;
22210461SAndreas.Sandberg@ARM.com}
22310609Sandreas.sandberg@arm.com
22410609Sandreas.sandberg@arm.com
22510609Sandreas.sandberg@arm.comvoid
22610037SARM gem5 DevelopersMSHR::TargetList::print(std::ostream &os, int verbosity,
22710037SARM gem5 Developers                        const std::string &prefix) const
22810037SARM gem5 Developers{
22910037SARM gem5 Developers    for (auto& t : *this) {
23011771SCurtis.Dunham@arm.com        const char *s;
23110037SARM gem5 Developers        switch (t.source) {
23210037SARM gem5 Developers          case Target::FromCPU:
23310037SARM gem5 Developers            s = "FromCPU";
23410037SARM gem5 Developers            break;
23510037SARM gem5 Developers          case Target::FromSnoop:
23610037SARM gem5 Developers            s = "FromSnoop";
23711771SCurtis.Dunham@arm.com            break;
23810037SARM gem5 Developers          case Target::FromPrefetcher:
23910037SARM gem5 Developers            s = "FromPrefetcher";
24010037SARM gem5 Developers            break;
24110037SARM gem5 Developers          default:
24210037SARM gem5 Developers            s = "";
24310037SARM gem5 Developers            break;
24411768SCurtis.Dunham@arm.com        }
24511768SCurtis.Dunham@arm.com        ccprintf(os, "%s%s: ", prefix, s);
24610037SARM gem5 Developers        t.pkt->print(os, verbosity, "");
24710037SARM gem5 Developers        ccprintf(os, "\n");
24810037SARM gem5 Developers    }
24910037SARM gem5 Developers}
2509384SAndreas.Sandberg@arm.com
2519384SAndreas.Sandberg@arm.com
2529384SAndreas.Sandberg@arm.comvoid
2539384SAndreas.Sandberg@arm.comMSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
2549384SAndreas.Sandberg@arm.com               Tick when_ready, Counter _order, bool alloc_on_fill)
2559384SAndreas.Sandberg@arm.com{
2569384SAndreas.Sandberg@arm.com    blkAddr = blk_addr;
2579384SAndreas.Sandberg@arm.com    blkSize = blk_size;
2589384SAndreas.Sandberg@arm.com    isSecure = target->isSecure();
2597427Sgblack@eecs.umich.edu    readyTime = when_ready;
2607427Sgblack@eecs.umich.edu    order = _order;
2617427Sgblack@eecs.umich.edu    assert(target);
2629385SAndreas.Sandberg@arm.com    isForward = false;
2639385SAndreas.Sandberg@arm.com    wasWholeLineWrite = false;
2647427Sgblack@eecs.umich.edu    _isUncacheable = target->req->isUncacheable();
2657427Sgblack@eecs.umich.edu    inService = false;
26610037SARM gem5 Developers    downstreamPending = false;
26710037SARM gem5 Developers
26810037SARM gem5 Developers    targets.init(blkAddr, blkSize);
26910037SARM gem5 Developers    deferredTargets.init(blkAddr, blkSize);
27010037SARM gem5 Developers
27110037SARM gem5 Developers    // Don't know of a case where we would allocate a new MSHR for a
27210037SARM gem5 Developers    // snoop (mem-side request), so set source according to request here
27310037SARM gem5 Developers    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
27410037SARM gem5 Developers        Target::FromPrefetcher : Target::FromCPU;
27510037SARM gem5 Developers    targets.add(target, when_ready, _order, source, true, alloc_on_fill);
27610037SARM gem5 Developers
27710037SARM gem5 Developers    // All targets must refer to the same block
27810037SARM gem5 Developers    assert(target->matchBlockAddr(targets.front().pkt, blkSize));
27910037SARM gem5 Developers}
2807427Sgblack@eecs.umich.edu
2817427Sgblack@eecs.umich.edu
2827427Sgblack@eecs.umich.eduvoid
2837427Sgblack@eecs.umich.eduMSHR::clearDownstreamPending()
2847427Sgblack@eecs.umich.edu{
2857427Sgblack@eecs.umich.edu    assert(downstreamPending);
28610037SARM gem5 Developers    downstreamPending = false;
28710037SARM gem5 Developers    // recursively clear flag on any MSHRs we will be forwarding
28810037SARM gem5 Developers    // responses to
28910037SARM gem5 Developers    targets.clearDownstreamPending();
2907427Sgblack@eecs.umich.edu}
2917427Sgblack@eecs.umich.edu
2927427Sgblack@eecs.umich.eduvoid
29310037SARM gem5 DevelopersMSHR::markInService(bool pending_modified_resp)
29410204SAli.Saidi@ARM.com{
29510204SAli.Saidi@ARM.com    assert(!inService);
29610037SARM gem5 Developers
2977427Sgblack@eecs.umich.edu    inService = true;
29810037SARM gem5 Developers    pendingModified = targets.needsWritable || pending_modified_resp;
2997427Sgblack@eecs.umich.edu    postInvalidate = postDowngrade = false;
30010037SARM gem5 Developers
3017427Sgblack@eecs.umich.edu    if (!downstreamPending) {
3027427Sgblack@eecs.umich.edu        // let upstream caches know that the request has made it to a
30310037SARM gem5 Developers        // level where it's going to get a response
3047427Sgblack@eecs.umich.edu        targets.clearDownstreamPending();
3057427Sgblack@eecs.umich.edu    }
3067427Sgblack@eecs.umich.edu    // if the line is not considered a whole-line write when sent
3077427Sgblack@eecs.umich.edu    // downstream, make sure it is also not considered a whole-line
3087427Sgblack@eecs.umich.edu    // write when receiving the response, and vice versa
3097427Sgblack@eecs.umich.edu    wasWholeLineWrite = isWholeLineWrite();
3107427Sgblack@eecs.umich.edu}
3117427Sgblack@eecs.umich.edu
3127427Sgblack@eecs.umich.edu
3137427Sgblack@eecs.umich.eduvoid
3147427Sgblack@eecs.umich.eduMSHR::deallocate()
3157427Sgblack@eecs.umich.edu{
3167427Sgblack@eecs.umich.edu    assert(targets.empty());
3177427Sgblack@eecs.umich.edu    targets.resetFlags();
3187427Sgblack@eecs.umich.edu    assert(deferredTargets.isReset());
3197427Sgblack@eecs.umich.edu    inService = false;
3207427Sgblack@eecs.umich.edu}
3217427Sgblack@eecs.umich.edu
3227427Sgblack@eecs.umich.edu/*
3237427Sgblack@eecs.umich.edu * Adds a target to an MSHR
3247427Sgblack@eecs.umich.edu */
3257427Sgblack@eecs.umich.eduvoid
3267427Sgblack@eecs.umich.eduMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order,
3277436Sdam.sunwoo@arm.com                     bool alloc_on_fill)
3287436Sdam.sunwoo@arm.com{
32910037SARM gem5 Developers    // assume we'd never issue a prefetch when we've got an
33010037SARM gem5 Developers    // outstanding miss
3317436Sdam.sunwoo@arm.com    assert(pkt->cmd != MemCmd::HardPFReq);
3327436Sdam.sunwoo@arm.com
3337436Sdam.sunwoo@arm.com    // if there's a request already in service for this MSHR, we will
3347436Sdam.sunwoo@arm.com    // have to defer the new target until after the response if any of
3357436Sdam.sunwoo@arm.com    // the following are true:
3367436Sdam.sunwoo@arm.com    // - there are other targets already deferred
3377436Sdam.sunwoo@arm.com    // - there's a pending invalidate to be applied after the response
3387436Sdam.sunwoo@arm.com    //   comes back (but before this target is processed)
3397436Sdam.sunwoo@arm.com    // - the MSHR's first (and only) non-deferred target is a cache
3407436Sdam.sunwoo@arm.com    //   maintenance packet
3417436Sdam.sunwoo@arm.com    // - the new target is a cache maintenance packet (this is probably
3427436Sdam.sunwoo@arm.com    //   overly conservative but certainly safe)
34310037SARM gem5 Developers    // - this target requires a writable block and either we're not
3447436Sdam.sunwoo@arm.com    //   getting a writable block back or we have already snooped
3457436Sdam.sunwoo@arm.com    //   another read request that will downgrade our writable block
3467436Sdam.sunwoo@arm.com    //   to non-writable (Shared or Owned)
3477436Sdam.sunwoo@arm.com    PacketPtr tgt_pkt = targets.front().pkt;
3487436Sdam.sunwoo@arm.com    if (pkt->req->isCacheMaintenance() ||
3497436Sdam.sunwoo@arm.com        tgt_pkt->req->isCacheMaintenance() ||
3507436Sdam.sunwoo@arm.com        !deferredTargets.empty() ||
3517436Sdam.sunwoo@arm.com        (inService &&
3527436Sdam.sunwoo@arm.com         (hasPostInvalidate() ||
3537436Sdam.sunwoo@arm.com          (pkt->needsWritable() &&
3547436Sdam.sunwoo@arm.com           (!isPendingModified() || hasPostDowngrade() || isForward))))) {
3557436Sdam.sunwoo@arm.com        // need to put on deferred list
3567436Sdam.sunwoo@arm.com        if (inService && hasPostInvalidate())
3577436Sdam.sunwoo@arm.com            replaceUpgrade(pkt);
3587436Sdam.sunwoo@arm.com        deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true,
3597436Sdam.sunwoo@arm.com                            alloc_on_fill);
3607644Sali.saidi@arm.com    } else {
3618147SAli.Saidi@ARM.com        // No request outstanding, or still OK to append to
3629385SAndreas.Sandberg@arm.com        // outstanding request: append to regular target list.  Only
3639385SAndreas.Sandberg@arm.com        // mark pending if current request hasn't been issued yet
3649385SAndreas.Sandberg@arm.com        // (isn't in service).
3659385SAndreas.Sandberg@arm.com        targets.add(pkt, whenReady, _order, Target::FromCPU, !inService,
3669385SAndreas.Sandberg@arm.com                    alloc_on_fill);
3679385SAndreas.Sandberg@arm.com    }
3689385SAndreas.Sandberg@arm.com}
3699385SAndreas.Sandberg@arm.com
3709385SAndreas.Sandberg@arm.combool
3719385SAndreas.Sandberg@arm.comMSHR::handleSnoop(PacketPtr pkt, Counter _order)
3729385SAndreas.Sandberg@arm.com{
3739385SAndreas.Sandberg@arm.com    DPRINTF(Cache, "%s for %s\n", __func__, pkt->print());
3749385SAndreas.Sandberg@arm.com
3759385SAndreas.Sandberg@arm.com    // when we snoop packets the needsWritable and isInvalidate flags
37610037SARM gem5 Developers    // should always be the same, however, this assumes that we never
37710037SARM gem5 Developers    // snoop writes as they are currently not marked as invalidations
37810037SARM gem5 Developers    panic_if((pkt->needsWritable() != pkt->isInvalidate()) &&
37910037SARM gem5 Developers             !pkt->req->isCacheMaintenance(),
38010037SARM gem5 Developers             "%s got snoop %s where needsWritable, "
38110037SARM gem5 Developers             "does not match isInvalidate", name(), pkt->print());
38210037SARM gem5 Developers
38310037SARM gem5 Developers    if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
38410037SARM gem5 Developers        // Request has not been issued yet, or it's been issued
38510037SARM gem5 Developers        // locally but is buffered unissued at some downstream cache
38610037SARM gem5 Developers        // which is forwarding us this snoop.  Either way, the packet
38710037SARM gem5 Developers        // we're snooping logically precedes this MSHR's request, so
38810037SARM gem5 Developers        // the snoop has no impact on the MSHR, but must be processed
38910037SARM gem5 Developers        // in the standard way by the cache.  The only exception is
39010037SARM gem5 Developers        // that if we're an L2+ cache buffering an UpgradeReq from a
39110037SARM gem5 Developers        // higher-level cache, and the snoop is invalidating, then our
3928147SAli.Saidi@ARM.com        // buffered upgrades must be converted to read exclusives,
3937427Sgblack@eecs.umich.edu        // since the upper-level cache no longer has a valid copy.
3947427Sgblack@eecs.umich.edu        // That is, even though the upper-level cache got out on its
3957427Sgblack@eecs.umich.edu        // local bus first, some other invalidating transaction
39610037SARM gem5 Developers        // reached the global bus before the upgrade did.
39710037SARM gem5 Developers        if (pkt->needsWritable() || pkt->req->isCacheInvalidate()) {
39810037SARM gem5 Developers            targets.replaceUpgrades();
39910037SARM gem5 Developers            deferredTargets.replaceUpgrades();
40010037SARM gem5 Developers        }
40110037SARM gem5 Developers
40210037SARM gem5 Developers        return false;
40310037SARM gem5 Developers    }
40410037SARM gem5 Developers
40510037SARM gem5 Developers    // From here on down, the request issued by this MSHR logically
40610037SARM gem5 Developers    // precedes the request we're snooping.
40710037SARM gem5 Developers    if (pkt->needsWritable() || pkt->req->isCacheInvalidate()) {
40810037SARM gem5 Developers        // snooped request still precedes the re-request we'll have to
40910037SARM gem5 Developers        // issue for deferred targets, if any...
41010037SARM gem5 Developers        deferredTargets.replaceUpgrades();
41110037SARM gem5 Developers    }
41210037SARM gem5 Developers
41310037SARM gem5 Developers    PacketPtr tgt_pkt = targets.front().pkt;
41410037SARM gem5 Developers    if (hasPostInvalidate() || tgt_pkt->req->isCacheInvalidate()) {
41510037SARM gem5 Developers        // a prior snoop has already appended an invalidation or a
41610037SARM gem5 Developers        // cache invalidation operation is in progress, so logically
41710037SARM gem5 Developers        // we don't have the block anymore; no need for further
41810037SARM gem5 Developers        // snooping.
41910037SARM gem5 Developers        return true;
42010037SARM gem5 Developers    }
42110037SARM gem5 Developers
42210037SARM gem5 Developers    if (isPendingModified() || pkt->isInvalidate()) {
42310037SARM gem5 Developers        // We need to save and replay the packet in two cases:
42410037SARM gem5 Developers        // 1. We're awaiting a writable copy (Modified or Exclusive),
42510037SARM gem5 Developers        //    so this MSHR is the orgering point, and we need to respond
42610037SARM gem5 Developers        //    after we receive data.
42710037SARM gem5 Developers        // 2. It's an invalidation (e.g., UpgradeReq), and we need
42810037SARM gem5 Developers        //    to forward the snoop up the hierarchy after the current
42910037SARM gem5 Developers        //    transaction completes.
43010037SARM gem5 Developers
43110037SARM gem5 Developers        // Start by determining if we will eventually respond or not,
43211770SCurtis.Dunham@arm.com        // matching the conditions checked in Cache::handleSnoop
43310037SARM gem5 Developers        bool will_respond = isPendingModified() && pkt->needsResponse() &&
43411574SCurtis.Dunham@arm.com                      !pkt->isClean();
43511770SCurtis.Dunham@arm.com
43611770SCurtis.Dunham@arm.com        // The packet we are snooping may be deleted by the time we
43710037SARM gem5 Developers        // actually process the target, and we consequently need to
43811770SCurtis.Dunham@arm.com        // save a copy here. Clear flags and also allocate new data as
43911770SCurtis.Dunham@arm.com        // the original packet data storage may have been deleted by
44010037SARM gem5 Developers        // the time we get to process this packet. In the cases where
44110037SARM gem5 Developers        // we are not responding after handling the snoop we also need
44210037SARM gem5 Developers        // to create a copy of the request to be on the safe side. In
44310037SARM gem5 Developers        // the latter case the cache is responsible for deleting both
44410037SARM gem5 Developers        // the packet and the request as part of handling the deferred
44510037SARM gem5 Developers        // snoop.
44610037SARM gem5 Developers        PacketPtr cp_pkt = will_respond ? new Packet(pkt, true, true) :
44710461SAndreas.Sandberg@ARM.com            new Packet(std::make_shared<Request>(*pkt->req), pkt->cmd,
44810461SAndreas.Sandberg@ARM.com                       blkSize, pkt->id);
44910461SAndreas.Sandberg@ARM.com
45010461SAndreas.Sandberg@ARM.com        if (will_respond) {
45110037SARM gem5 Developers            // we are the ordering point, and will consequently
45210037SARM gem5 Developers            // respond, and depending on whether the packet
45310037SARM gem5 Developers            // needsWritable or not we either pass a Shared line or a
45410037SARM gem5 Developers            // Modified line
45510037SARM gem5 Developers            pkt->setCacheResponding();
45610037SARM gem5 Developers
45710461SAndreas.Sandberg@ARM.com            // inform the cache hierarchy that this cache had the line
45810461SAndreas.Sandberg@ARM.com            // in the Modified state, even if the response is passed
45910461SAndreas.Sandberg@ARM.com            // as Shared (and thus non-writable)
46010461SAndreas.Sandberg@ARM.com            pkt->setResponderHadWritable();
46110461SAndreas.Sandberg@ARM.com
46210037SARM gem5 Developers            // in the case of an uncacheable request there is no need
46310037SARM gem5 Developers            // to set the responderHadWritable flag, but since the
46410037SARM gem5 Developers            // recipient does not care there is no harm in doing so
46510037SARM gem5 Developers        } else if (isPendingModified() && pkt->isClean()) {
46610037SARM gem5 Developers            // this cache doesn't respond to the clean request, a
46711574SCurtis.Dunham@arm.com            // destination xbar will respond to this request, but to
46810037SARM gem5 Developers            // do so it needs to know if it should wait for the
46910037SARM gem5 Developers            // WriteCleanReq
47010037SARM gem5 Developers            pkt->setSatisfied();
47111574SCurtis.Dunham@arm.com        }
47210037SARM gem5 Developers
47310037SARM gem5 Developers        targets.add(cp_pkt, curTick(), _order, Target::FromSnoop,
47410037SARM gem5 Developers                    downstreamPending && targets.needsWritable, false);
47510037SARM gem5 Developers
47610037SARM gem5 Developers        if (pkt->needsWritable() || pkt->isInvalidate()) {
47710037SARM gem5 Developers            // This transaction will take away our pending copy
47810037SARM gem5 Developers            postInvalidate = true;
47910037SARM gem5 Developers        }
48010037SARM gem5 Developers    }
48110037SARM gem5 Developers
4827405SAli.Saidi@ARM.com    if (!pkt->needsWritable() && !pkt->req->isUncacheable()) {
48310035Sandreas.hansson@arm.com        // This transaction will get a read-shared copy, downgrading
4847405SAli.Saidi@ARM.com        // our copy if we had a writable one
4857405SAli.Saidi@ARM.com        postDowngrade = true;
4867614Sminkyu.jeong@arm.com        // make sure that any downstream cache does not respond with a
48711771SCurtis.Dunham@arm.com        // writable (and dirty) copy even if it has one, unless it was
48811771SCurtis.Dunham@arm.com        // explicitly asked for one
48911771SCurtis.Dunham@arm.com        pkt->setHasSharers();
49011771SCurtis.Dunham@arm.com    }
4917405SAli.Saidi@ARM.com
4927405SAli.Saidi@ARM.com    return true;
4937405SAli.Saidi@ARM.com}
4947405SAli.Saidi@ARM.com
4957405SAli.Saidi@ARM.comMSHR::TargetList
4967405SAli.Saidi@ARM.comMSHR::extractServiceableTargets(PacketPtr pkt)
49710037SARM gem5 Developers{
49810037SARM gem5 Developers    TargetList ready_targets;
49910037SARM gem5 Developers    ready_targets.init(blkAddr, blkSize);
5009050Schander.sudanthi@arm.com    // If the downstream MSHR got an invalidation request then we only
5017405SAli.Saidi@ARM.com    // service the first of the FromCPU targets and any other
50210037SARM gem5 Developers    // non-FromCPU target. This way the remaining FromCPU targets
50310037SARM gem5 Developers    // issue a new request and get a fresh copy of the block and we
5047720Sgblack@eecs.umich.edu    // avoid memory consistency violations.
5057720Sgblack@eecs.umich.edu    if (pkt->cmd == MemCmd::ReadRespWithInvalidate) {
5067405SAli.Saidi@ARM.com        auto it = targets.begin();
5077405SAli.Saidi@ARM.com        assert((it->source == Target::FromCPU) ||
5087757SAli.Saidi@ARM.com               (it->source == Target::FromPrefetcher));
50910037SARM gem5 Developers        ready_targets.push_back(*it);
51010037SARM gem5 Developers        it = targets.erase(it);
51110037SARM gem5 Developers        while (it != targets.end()) {
51210037SARM gem5 Developers            if (it->source == Target::FromCPU) {
51310037SARM gem5 Developers                it++;
51410037SARM gem5 Developers            } else {
51510037SARM gem5 Developers                assert(it->source == Target::FromSnoop);
51610037SARM gem5 Developers                ready_targets.push_back(*it);
51710037SARM gem5 Developers                it = targets.erase(it);
51810037SARM gem5 Developers            }
51910037SARM gem5 Developers        }
52010037SARM gem5 Developers        ready_targets.populateFlags();
52110037SARM gem5 Developers    } else {
52210037SARM gem5 Developers        std::swap(ready_targets, targets);
52310037SARM gem5 Developers    }
52410037SARM gem5 Developers    targets.populateFlags();
52510037SARM gem5 Developers
52610037SARM gem5 Developers    return ready_targets;
52710037SARM gem5 Developers}
52810037SARM gem5 Developers
52910037SARM gem5 Developersbool
53010037SARM gem5 DevelopersMSHR::promoteDeferredTargets()
53110037SARM gem5 Developers{
53210037SARM gem5 Developers    if (targets.empty() && deferredTargets.empty()) {
53310037SARM gem5 Developers        // nothing to promote
53410037SARM gem5 Developers        return false;
53510037SARM gem5 Developers    }
53610037SARM gem5 Developers
53710037SARM gem5 Developers    // the deferred targets can be generally promoted unless they
53810037SARM gem5 Developers    // contain a cache maintenance request
53910037SARM gem5 Developers
54010037SARM gem5 Developers    // find the first target that is a cache maintenance request
54110037SARM gem5 Developers    auto it = std::find_if(deferredTargets.begin(), deferredTargets.end(),
54210037SARM gem5 Developers                           [](MSHR::Target &t) {
54310037SARM gem5 Developers                               return t.pkt->req->isCacheMaintenance();
54410037SARM gem5 Developers                           });
54510037SARM gem5 Developers    if (it == deferredTargets.begin()) {
54610037SARM gem5 Developers        // if the first deferred target is a cache maintenance packet
54710037SARM gem5 Developers        // then we can promote provided the targets list is empty and
54810037SARM gem5 Developers        // we can service it on its own
54910037SARM gem5 Developers        if (targets.empty()) {
55010037SARM gem5 Developers            targets.splice(targets.end(), deferredTargets, it);
55110037SARM gem5 Developers        }
55210037SARM gem5 Developers    } else {
55310037SARM gem5 Developers        // if a cache maintenance operation exists, we promote all the
55410037SARM gem5 Developers        // deferred targets that precede it, or all deferred targets
5558284SAli.Saidi@ARM.com        // otherwise
55610037SARM gem5 Developers        targets.splice(targets.end(), deferredTargets,
55710037SARM gem5 Developers                       deferredTargets.begin(), it);
55810037SARM gem5 Developers    }
55910037SARM gem5 Developers
5609050Schander.sudanthi@arm.com    deferredTargets.populateFlags();
56110037SARM gem5 Developers    targets.populateFlags();
56210037SARM gem5 Developers    order = targets.front().order;
56310037SARM gem5 Developers    readyTime = std::max(curTick(), targets.front().readyTime);
56410037SARM gem5 Developers
56510037SARM gem5 Developers    return true;
56610037SARM gem5 Developers}
56710037SARM gem5 Developers
56810037SARM gem5 Developersvoid
56910037SARM gem5 DevelopersMSHR::promoteIf(const std::function<bool (Target &)>& pred)
57010037SARM gem5 Developers{
57110037SARM gem5 Developers    // if any of the deferred targets were upper-level cache
57210037SARM gem5 Developers    // requests marked downstreamPending, need to clear that
57310037SARM gem5 Developers    assert(!downstreamPending);  // not pending here anymore
57410037SARM gem5 Developers
57510037SARM gem5 Developers    // find the first target does not satisfy the condition
57610037SARM gem5 Developers    auto last_it = std::find_if_not(deferredTargets.begin(),
57710037SARM gem5 Developers                                    deferredTargets.end(),
57810037SARM gem5 Developers                                    pred);
5799050Schander.sudanthi@arm.com
5808284SAli.Saidi@ARM.com    // for the prefix of the deferredTargets [begin(), last_it) clear
58110037SARM gem5 Developers    // the downstreamPending flag and move them to the target list
58210037SARM gem5 Developers    deferredTargets.clearDownstreamPending(deferredTargets.begin(),
58310037SARM gem5 Developers                                           last_it);
58410037SARM gem5 Developers    targets.splice(targets.end(), deferredTargets,
58510037SARM gem5 Developers                   deferredTargets.begin(), last_it);
58610037SARM gem5 Developers    // We need to update the flags for the target lists after the
58710037SARM gem5 Developers    // modifications
5887405SAli.Saidi@ARM.com    deferredTargets.populateFlags();
5897731SAli.Saidi@ARM.com}
5908468Swade.walker@arm.com
5918468Swade.walker@arm.comvoid
5928468Swade.walker@arm.comMSHR::promoteReadable()
5937405SAli.Saidi@ARM.com{
5947731SAli.Saidi@ARM.com    if (!deferredTargets.empty() && !hasPostInvalidate()) {
5957405SAli.Saidi@ARM.com        // We got a non invalidating response, and we have the block
5967405SAli.Saidi@ARM.com        // but we have deferred targets which are waiting and they do
5977583SAli.Saidi@arm.com        // not need writable. This can happen if the original request
5989130Satgutier@umich.edu        // was for a cache clean operation and we had a copy of the
5999130Satgutier@umich.edu        // block. Since we serviced the cache clean operation and we
6009130Satgutier@umich.edu        // have the block, there's no need to defer the targets, so
6019130Satgutier@umich.edu        // move them up to the regular target list.
6029814Sandreas.hansson@arm.com
6039130Satgutier@umich.edu        auto pred = [](Target &t) {
6049130Satgutier@umich.edu            assert(t.source == Target::FromCPU);
6059130Satgutier@umich.edu            return !t.pkt->req->isCacheInvalidate() &&
6069130Satgutier@umich.edu                   !t.pkt->needsWritable();
6079130Satgutier@umich.edu        };
6089130Satgutier@umich.edu        promoteIf(pred);
6099130Satgutier@umich.edu    }
6109130Satgutier@umich.edu}
6119130Satgutier@umich.edu
6129130Satgutier@umich.eduvoid
6139130Satgutier@umich.eduMSHR::promoteWritable()
6149130Satgutier@umich.edu{
6159130Satgutier@umich.edu    if (deferredTargets.needsWritable &&
6169130Satgutier@umich.edu        !(hasPostInvalidate() || hasPostDowngrade())) {
6179130Satgutier@umich.edu        // We got a writable response, but we have deferred targets
6189130Satgutier@umich.edu        // which are waiting to request a writable copy (not because
6199130Satgutier@umich.edu        // of a pending invalidate).  This can happen if the original
6209130Satgutier@umich.edu        // request was for a read-only block, but we got a writable
6219130Satgutier@umich.edu        // response anyway. Since we got the writable copy there's no
6229130Satgutier@umich.edu        // need to defer the targets, so move them up to the regular
6239130Satgutier@umich.edu        // target list.
6249130Satgutier@umich.edu        assert(!targets.needsWritable);
6257583SAli.Saidi@arm.com        targets.needsWritable = true;
6267583SAli.Saidi@arm.com
6277583SAli.Saidi@arm.com        auto pred = [](Target &t) {
62810461SAndreas.Sandberg@ARM.com            assert(t.source == Target::FromCPU);
62910461SAndreas.Sandberg@ARM.com            return !t.pkt->req->isCacheInvalidate();
63010461SAndreas.Sandberg@ARM.com        };
63110461SAndreas.Sandberg@ARM.com
63210461SAndreas.Sandberg@ARM.com        promoteIf(pred);
63310461SAndreas.Sandberg@ARM.com    }
63410461SAndreas.Sandberg@ARM.com}
6358302SAli.Saidi@ARM.com
6368302SAli.Saidi@ARM.com
6377783SGiacomo.Gabrielli@arm.combool
6387783SGiacomo.Gabrielli@arm.comMSHR::trySatisfyFunctional(PacketPtr pkt)
6397783SGiacomo.Gabrielli@arm.com{
6407783SGiacomo.Gabrielli@arm.com    // For printing, we treat the MSHR as a whole as single entity.
64110037SARM gem5 Developers    // For other requests, we iterate over the individual targets
64210037SARM gem5 Developers    // since that's where the actual data lies.
64310037SARM gem5 Developers    if (pkt->isPrint()) {
64410037SARM gem5 Developers        pkt->trySatisfyFunctional(this, blkAddr, isSecure, blkSize, nullptr);
64510037SARM gem5 Developers        return false;
64610037SARM gem5 Developers    } else {
64710037SARM gem5 Developers        return (targets.trySatisfyFunctional(pkt) ||
64810037SARM gem5 Developers                deferredTargets.trySatisfyFunctional(pkt));
64910037SARM gem5 Developers    }
65010037SARM gem5 Developers}
65110037SARM gem5 Developers
65210037SARM gem5 Developersbool
65310037SARM gem5 DevelopersMSHR::sendPacket(BaseCache &cache)
65410037SARM gem5 Developers{
65510037SARM gem5 Developers    return cache.sendMSHRQueuePacket(this);
65610037SARM gem5 Developers}
65710037SARM gem5 Developers
65810037SARM gem5 Developersvoid
65910037SARM gem5 DevelopersMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
66010037SARM gem5 Developers{
66110037SARM gem5 Developers    ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s %s\n",
66210037SARM gem5 Developers             prefix, blkAddr, blkAddr + blkSize - 1,
66310037SARM gem5 Developers             isSecure ? "s" : "ns",
66410037SARM gem5 Developers             isForward ? "Forward" : "",
66510037SARM gem5 Developers             allocOnFill() ? "AllocOnFill" : "",
66610037SARM gem5 Developers             needsWritable() ? "Wrtbl" : "",
66710037SARM gem5 Developers             _isUncacheable ? "Unc" : "",
66810037SARM gem5 Developers             inService ? "InSvc" : "",
66910037SARM gem5 Developers             downstreamPending ? "DwnPend" : "",
67010037SARM gem5 Developers             postInvalidate ? "PostInv" : "",
67110037SARM gem5 Developers             postDowngrade ? "PostDowngr" : "",
67210037SARM gem5 Developers             hasFromCache() ? "HasFromCache" : "");
67310037SARM gem5 Developers
67410037SARM gem5 Developers    if (!targets.empty()) {
67510037SARM gem5 Developers        ccprintf(os, "%s  Targets:\n", prefix);
67610037SARM gem5 Developers        targets.print(os, verbosity, prefix + "    ");
67710037SARM gem5 Developers    }
67810037SARM gem5 Developers    if (!deferredTargets.empty()) {
67910338SCurtis.Dunham@arm.com        ccprintf(os, "%s  Deferred Targets:\n", prefix);
68010338SCurtis.Dunham@arm.com        deferredTargets.print(os, verbosity, prefix + "      ");
68110338SCurtis.Dunham@arm.com    }
68210037SARM gem5 Developers}
68310037SARM gem5 Developers
68410037SARM gem5 Developersstd::string
68510037SARM gem5 DevelopersMSHR::print() const
68610037SARM gem5 Developers{
68710037SARM gem5 Developers    std::ostringstream str;
68810037SARM gem5 Developers    print(str);
68910037SARM gem5 Developers    return str.str();
69010037SARM gem5 Developers}
69110037SARM gem5 Developers
69210037SARM gem5 Developersbool
69310037SARM gem5 DevelopersMSHR::matchBlockAddr(const Addr addr, const bool is_secure) const
69410037SARM gem5 Developers{
69510037SARM gem5 Developers    assert(hasTargets());
69610037SARM gem5 Developers    return (blkAddr == addr) && (isSecure == is_secure);
69710037SARM gem5 Developers}
69810037SARM gem5 Developers
69910037SARM gem5 Developersbool
70010037SARM gem5 DevelopersMSHR::matchBlockAddr(const PacketPtr pkt) const
70110037SARM gem5 Developers{
70210037SARM gem5 Developers    assert(hasTargets());
70310037SARM gem5 Developers    return pkt->matchBlockAddr(blkAddr, isSecure, blkSize);
70410037SARM gem5 Developers}
70510037SARM gem5 Developers
70610037SARM gem5 Developersbool
70710037SARM gem5 DevelopersMSHR::conflictAddr(const QueueEntry* entry) const
70810037SARM gem5 Developers{
70910037SARM gem5 Developers    assert(hasTargets());
7108549Sdaniel.johnson@arm.com    return entry->matchBlockAddr(blkAddr, isSecure);
7118868SMatt.Horsnell@arm.com}
7128868SMatt.Horsnell@arm.com