mshr.cc revision 13349
12810SN/A/* 212501Snikos.nikoleris@arm.com * Copyright (c) 2012-2013, 2015-2018 ARM Limited 39663Suri.wiener@arm.com * All rights reserved. 49663Suri.wiener@arm.com * 59663Suri.wiener@arm.com * The license below extends only to copyright in the software and shall 69663Suri.wiener@arm.com * not be construed as granting a license to any other intellectual 79663Suri.wiener@arm.com * property including but not limited to intellectual property relating 89663Suri.wiener@arm.com * to a hardware implementation of the functionality of the software 99663Suri.wiener@arm.com * licensed hereunder. You may use the software subject to the license 109663Suri.wiener@arm.com * terms below provided that you ensure that this notice is replicated 119663Suri.wiener@arm.com * unmodified and in its entirety in all distributions of the software, 129663Suri.wiener@arm.com * modified or unmodified, in source code or in binary form. 139663Suri.wiener@arm.com * 142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc. 162810SN/A * All rights reserved. 172810SN/A * 182810SN/A * Redistribution and use in source and binary forms, with or without 192810SN/A * modification, are permitted provided that the following conditions are 202810SN/A * met: redistributions of source code must retain the above copyright 212810SN/A * notice, this list of conditions and the following disclaimer; 222810SN/A * redistributions in binary form must reproduce the above copyright 232810SN/A * notice, this list of conditions and the following disclaimer in the 242810SN/A * documentation and/or other materials provided with the distribution; 252810SN/A * neither the name of the copyright holders nor the names of its 262810SN/A * contributors may be used to endorse or promote products derived from 272810SN/A * this software without specific prior written permission. 282810SN/A * 292810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810SN/A * 412810SN/A * Authors: Erik Hallnor 422810SN/A * Dave Greene 4313349Snikos.nikoleris@arm.com * Nikos Nikoleris 442810SN/A */ 452810SN/A 462810SN/A/** 472810SN/A * @file 482810SN/A * Miss Status and Handling Register (MSHR) definitions. 492810SN/A */ 502810SN/A 5111486Snikos.nikoleris@arm.com#include "mem/cache/mshr.hh" 5211486Snikos.nikoleris@arm.com 536216Snate@binkert.org#include <cassert> 542810SN/A#include <string> 552810SN/A 5612334Sgabeblack@google.com#include "base/logging.hh" 5712727Snikos.nikoleris@arm.com#include "base/trace.hh" 586216Snate@binkert.org#include "base/types.hh" 598232Snate@binkert.org#include "debug/Cache.hh" 6012727Snikos.nikoleris@arm.com#include "mem/cache/base.hh" 6112727Snikos.nikoleris@arm.com#include "mem/request.hh" 626216Snate@binkert.org#include "sim/core.hh" 632810SN/A 6411375Sandreas.hansson@arm.comMSHR::MSHR() : downstreamPending(false), 6511284Sandreas.hansson@arm.com pendingModified(false), 6610503SCurtis.Dunham@arm.com postInvalidate(false), postDowngrade(false), 6713349Snikos.nikoleris@arm.com wasWholeLineWrite(false), isForward(false) 682810SN/A{ 692810SN/A} 702810SN/A 714903SN/AMSHR::TargetList::TargetList() 7212715Snikos.nikoleris@arm.com : needsWritable(false), hasUpgrade(false), allocOnFill(false), 7312715Snikos.nikoleris@arm.com hasFromCache(false) 744903SN/A{} 754903SN/A 764903SN/A 7711740Snikos.nikoleris@arm.comvoid 7811741Snikos.nikoleris@arm.comMSHR::TargetList::updateFlags(PacketPtr pkt, Target::Source source, 7911741Snikos.nikoleris@arm.com bool alloc_on_fill) 804903SN/A{ 815875Ssteve.reinhardt@amd.com if (source != Target::FromSnoop) { 8211284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 8311284Sandreas.hansson@arm.com needsWritable = true; 844903SN/A } 854903SN/A 867669Ssteve.reinhardt@amd.com // StoreCondReq is effectively an upgrade if it's in an MSHR 877669Ssteve.reinhardt@amd.com // since it would have been failed already if we didn't have a 887669Ssteve.reinhardt@amd.com // read-only copy 897669Ssteve.reinhardt@amd.com if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) { 904903SN/A hasUpgrade = true; 914903SN/A } 9211741Snikos.nikoleris@arm.com 9311741Snikos.nikoleris@arm.com // potentially re-evaluate whether we should allocate on a fill or 9411741Snikos.nikoleris@arm.com // not 9511741Snikos.nikoleris@arm.com allocOnFill = allocOnFill || alloc_on_fill; 9612715Snikos.nikoleris@arm.com 9712715Snikos.nikoleris@arm.com if (source != Target::FromPrefetcher) { 9812715Snikos.nikoleris@arm.com hasFromCache = hasFromCache || pkt->fromCache(); 9913349Snikos.nikoleris@arm.com 10013349Snikos.nikoleris@arm.com updateWriteFlags(pkt); 10112715Snikos.nikoleris@arm.com } 1025318SN/A } 10311740Snikos.nikoleris@arm.com} 1044908SN/A 10511740Snikos.nikoleris@arm.comvoid 10611740Snikos.nikoleris@arm.comMSHR::TargetList::populateFlags() 10711740Snikos.nikoleris@arm.com{ 10811740Snikos.nikoleris@arm.com resetFlags(); 10911740Snikos.nikoleris@arm.com for (auto& t: *this) { 11011741Snikos.nikoleris@arm.com updateFlags(t.pkt, t.source, t.allocOnFill); 11111740Snikos.nikoleris@arm.com } 11211740Snikos.nikoleris@arm.com} 11311740Snikos.nikoleris@arm.com 11411740Snikos.nikoleris@arm.cominline void 11511740Snikos.nikoleris@arm.comMSHR::TargetList::add(PacketPtr pkt, Tick readyTime, 11611741Snikos.nikoleris@arm.com Counter order, Target::Source source, bool markPending, 11711741Snikos.nikoleris@arm.com bool alloc_on_fill) 11811740Snikos.nikoleris@arm.com{ 11911741Snikos.nikoleris@arm.com updateFlags(pkt, source, alloc_on_fill); 1205318SN/A if (markPending) { 1219543Ssascha.bischoff@arm.com // Iterate over the SenderState stack and see if we find 1229543Ssascha.bischoff@arm.com // an MSHR entry. If we do, set the downstreamPending 1239543Ssascha.bischoff@arm.com // flag. Otherwise, do nothing. 1249543Ssascha.bischoff@arm.com MSHR *mshr = pkt->findNextSenderState<MSHR>(); 12511484Snikos.nikoleris@arm.com if (mshr != nullptr) { 1264908SN/A assert(!mshr->downstreamPending); 1274908SN/A mshr->downstreamPending = true; 12811083Sandreas.hansson@arm.com } else { 12911083Sandreas.hansson@arm.com // No need to clear downstreamPending later 13011083Sandreas.hansson@arm.com markPending = false; 1314908SN/A } 1324903SN/A } 1334903SN/A 13411741Snikos.nikoleris@arm.com emplace_back(pkt, readyTime, order, source, markPending, alloc_on_fill); 1354903SN/A} 1364903SN/A 1374903SN/A 1387667Ssteve.reinhardt@amd.comstatic void 1397667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt) 1407667Ssteve.reinhardt@amd.com{ 14111286Sandreas.hansson@arm.com // remember if the current packet has data allocated 14211286Sandreas.hansson@arm.com bool has_data = pkt->hasData() || pkt->hasRespData(); 14311286Sandreas.hansson@arm.com 1447667Ssteve.reinhardt@amd.com if (pkt->cmd == MemCmd::UpgradeReq) { 1457667Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::ReadExReq; 1467667Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n"); 1477667Ssteve.reinhardt@amd.com } else if (pkt->cmd == MemCmd::SCUpgradeReq) { 1487667Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::SCUpgradeFailReq; 1497667Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n"); 1507669Ssteve.reinhardt@amd.com } else if (pkt->cmd == MemCmd::StoreCondReq) { 1517669Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::StoreCondFailReq; 1527669Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n"); 1537667Ssteve.reinhardt@amd.com } 15411286Sandreas.hansson@arm.com 15511286Sandreas.hansson@arm.com if (!has_data) { 15611286Sandreas.hansson@arm.com // there is no sensible way of setting the data field if the 15711286Sandreas.hansson@arm.com // new command actually would carry data 15811286Sandreas.hansson@arm.com assert(!pkt->hasData()); 15911286Sandreas.hansson@arm.com 16011286Sandreas.hansson@arm.com if (pkt->hasRespData()) { 16111286Sandreas.hansson@arm.com // we went from a packet that had no data (neither request, 16211286Sandreas.hansson@arm.com // nor response), to one that does, and therefore we need to 16311286Sandreas.hansson@arm.com // actually allocate space for the data payload 16411286Sandreas.hansson@arm.com pkt->allocate(); 16511286Sandreas.hansson@arm.com } 16611286Sandreas.hansson@arm.com } 1677667Ssteve.reinhardt@amd.com} 1687667Ssteve.reinhardt@amd.com 1697667Ssteve.reinhardt@amd.com 1704903SN/Avoid 1714903SN/AMSHR::TargetList::replaceUpgrades() 1724903SN/A{ 1734903SN/A if (!hasUpgrade) 1744903SN/A return; 1754903SN/A 17610766Sandreas.hansson@arm.com for (auto& t : *this) { 17710766Sandreas.hansson@arm.com replaceUpgrade(t.pkt); 1784903SN/A } 1794903SN/A 1804903SN/A hasUpgrade = false; 1814903SN/A} 1824903SN/A 1834903SN/A 1842810SN/Avoid 18512791Snikos.nikoleris@arm.comMSHR::TargetList::clearDownstreamPending(MSHR::TargetList::iterator begin, 18612791Snikos.nikoleris@arm.com MSHR::TargetList::iterator end) 1874908SN/A{ 18812791Snikos.nikoleris@arm.com for (auto t = begin; t != end; t++) { 18912791Snikos.nikoleris@arm.com if (t->markedPending) { 1909543Ssascha.bischoff@arm.com // Iterate over the SenderState stack and see if we find 1919543Ssascha.bischoff@arm.com // an MSHR entry. If we find one, clear the 1929543Ssascha.bischoff@arm.com // downstreamPending flag by calling 1939543Ssascha.bischoff@arm.com // clearDownstreamPending(). This recursively clears the 1949543Ssascha.bischoff@arm.com // downstreamPending flag in all caches this packet has 1959543Ssascha.bischoff@arm.com // passed through. 19612791Snikos.nikoleris@arm.com MSHR *mshr = t->pkt->findNextSenderState<MSHR>(); 19711484Snikos.nikoleris@arm.com if (mshr != nullptr) { 1985318SN/A mshr->clearDownstreamPending(); 1995318SN/A } 20012791Snikos.nikoleris@arm.com t->markedPending = false; 2014908SN/A } 2024908SN/A } 2034908SN/A} 2044908SN/A 20512791Snikos.nikoleris@arm.comvoid 20612791Snikos.nikoleris@arm.comMSHR::TargetList::clearDownstreamPending() 20712791Snikos.nikoleris@arm.com{ 20812791Snikos.nikoleris@arm.com clearDownstreamPending(begin(), end()); 20912791Snikos.nikoleris@arm.com} 21012791Snikos.nikoleris@arm.com 2114908SN/A 2124920SN/Abool 21312823Srmk35@cl.cam.ac.ukMSHR::TargetList::trySatisfyFunctional(PacketPtr pkt) 2144920SN/A{ 21510766Sandreas.hansson@arm.com for (auto& t : *this) { 21612823Srmk35@cl.cam.ac.uk if (pkt->trySatisfyFunctional(t.pkt)) { 2174920SN/A return true; 2184920SN/A } 2194920SN/A } 2204920SN/A 2214920SN/A return false; 2224920SN/A} 2234920SN/A 2244920SN/A 2254908SN/Avoid 22610766Sandreas.hansson@arm.comMSHR::TargetList::print(std::ostream &os, int verbosity, 22710766Sandreas.hansson@arm.com const std::string &prefix) const 2285314SN/A{ 22910766Sandreas.hansson@arm.com for (auto& t : *this) { 2305875Ssteve.reinhardt@amd.com const char *s; 23110766Sandreas.hansson@arm.com switch (t.source) { 2328988SAli.Saidi@ARM.com case Target::FromCPU: 2338988SAli.Saidi@ARM.com s = "FromCPU"; 2348988SAli.Saidi@ARM.com break; 2358988SAli.Saidi@ARM.com case Target::FromSnoop: 2368988SAli.Saidi@ARM.com s = "FromSnoop"; 2378988SAli.Saidi@ARM.com break; 2388988SAli.Saidi@ARM.com case Target::FromPrefetcher: 2398988SAli.Saidi@ARM.com s = "FromPrefetcher"; 2408988SAli.Saidi@ARM.com break; 2418988SAli.Saidi@ARM.com default: 2428988SAli.Saidi@ARM.com s = ""; 2438988SAli.Saidi@ARM.com break; 2445875Ssteve.reinhardt@amd.com } 2455875Ssteve.reinhardt@amd.com ccprintf(os, "%s%s: ", prefix, s); 24610766Sandreas.hansson@arm.com t.pkt->print(os, verbosity, ""); 24711744Snikos.nikoleris@arm.com ccprintf(os, "\n"); 2485314SN/A } 2495314SN/A} 2505314SN/A 2515314SN/A 2525314SN/Avoid 25310764Sandreas.hansson@arm.comMSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target, 25411197Sandreas.hansson@arm.com Tick when_ready, Counter _order, bool alloc_on_fill) 2552810SN/A{ 25610764Sandreas.hansson@arm.com blkAddr = blk_addr; 25710764Sandreas.hansson@arm.com blkSize = blk_size; 25810028SGiacomo.Gabrielli@arm.com isSecure = target->isSecure(); 25910764Sandreas.hansson@arm.com readyTime = when_ready; 2604666SN/A order = _order; 2614626SN/A assert(target); 2625730SSteve.Reinhardt@amd.com isForward = false; 26313349Snikos.nikoleris@arm.com wasWholeLineWrite = false; 2644626SN/A _isUncacheable = target->req->isUncacheable(); 2654626SN/A inService = false; 2664908SN/A downstreamPending = false; 26713349Snikos.nikoleris@arm.com 26813349Snikos.nikoleris@arm.com targets.init(blkAddr, blkSize); 26913349Snikos.nikoleris@arm.com deferredTargets.init(blkAddr, blkSize); 27013349Snikos.nikoleris@arm.com 2714626SN/A // Don't know of a case where we would allocate a new MSHR for a 2725875Ssteve.reinhardt@amd.com // snoop (mem-side request), so set source according to request here 2735875Ssteve.reinhardt@amd.com Target::Source source = (target->cmd == MemCmd::HardPFReq) ? 2745875Ssteve.reinhardt@amd.com Target::FromPrefetcher : Target::FromCPU; 27511741Snikos.nikoleris@arm.com targets.add(target, when_ready, _order, source, true, alloc_on_fill); 2762810SN/A} 2772810SN/A 2784908SN/A 2795318SN/Avoid 2805318SN/AMSHR::clearDownstreamPending() 2815318SN/A{ 2825318SN/A assert(downstreamPending); 2835318SN/A downstreamPending = false; 2845318SN/A // recursively clear flag on any MSHRs we will be forwarding 2855318SN/A // responses to 2869725Sandreas.hansson@arm.com targets.clearDownstreamPending(); 2875318SN/A} 2885318SN/A 28911375Sandreas.hansson@arm.comvoid 29011284Sandreas.hansson@arm.comMSHR::markInService(bool pending_modified_resp) 2914908SN/A{ 2924908SN/A assert(!inService); 29310424Sandreas.hansson@arm.com 2944908SN/A inService = true; 29511284Sandreas.hansson@arm.com pendingModified = targets.needsWritable || pending_modified_resp; 2967667Ssteve.reinhardt@amd.com postInvalidate = postDowngrade = false; 2977667Ssteve.reinhardt@amd.com 2984908SN/A if (!downstreamPending) { 2994908SN/A // let upstream caches know that the request has made it to a 3004908SN/A // level where it's going to get a response 3019725Sandreas.hansson@arm.com targets.clearDownstreamPending(); 3024908SN/A } 30313349Snikos.nikoleris@arm.com // if the line is not considered a whole-line write when sent 30413349Snikos.nikoleris@arm.com // downstream, make sure it is also not considered a whole-line 30513349Snikos.nikoleris@arm.com // write when receiving the response, and vice versa 30613349Snikos.nikoleris@arm.com wasWholeLineWrite = isWholeLineWrite(); 3074908SN/A} 3084908SN/A 3094908SN/A 3102810SN/Avoid 3112810SN/AMSHR::deallocate() 3122810SN/A{ 3139725Sandreas.hansson@arm.com assert(targets.empty()); 3149725Sandreas.hansson@arm.com targets.resetFlags(); 3159725Sandreas.hansson@arm.com assert(deferredTargets.isReset()); 3162810SN/A inService = false; 3172810SN/A} 3182810SN/A 3192810SN/A/* 3202810SN/A * Adds a target to an MSHR 3212810SN/A */ 3222810SN/Avoid 32311197Sandreas.hansson@arm.comMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order, 32411197Sandreas.hansson@arm.com bool alloc_on_fill) 3252810SN/A{ 32610768Sandreas.hansson@arm.com // assume we'd never issue a prefetch when we've got an 32710768Sandreas.hansson@arm.com // outstanding miss 32810768Sandreas.hansson@arm.com assert(pkt->cmd != MemCmd::HardPFReq); 32910768Sandreas.hansson@arm.com 3304903SN/A // if there's a request already in service for this MSHR, we will 3314903SN/A // have to defer the new target until after the response if any of 3324903SN/A // the following are true: 3334903SN/A // - there are other targets already deferred 3344903SN/A // - there's a pending invalidate to be applied after the response 3354903SN/A // comes back (but before this target is processed) 33612350Snikos.nikoleris@arm.com // - the MSHR's first (and only) non-deferred target is a cache 33712350Snikos.nikoleris@arm.com // maintenance packet 33812350Snikos.nikoleris@arm.com // - the new target is a cache maintenance packet (this is probably 33912350Snikos.nikoleris@arm.com // overly conservative but certainly safe) 34011284Sandreas.hansson@arm.com // - this target requires a writable block and either we're not 34111284Sandreas.hansson@arm.com // getting a writable block back or we have already snooped 34211284Sandreas.hansson@arm.com // another read request that will downgrade our writable block 34311284Sandreas.hansson@arm.com // to non-writable (Shared or Owned) 34412350Snikos.nikoleris@arm.com PacketPtr tgt_pkt = targets.front().pkt; 34512350Snikos.nikoleris@arm.com if (pkt->req->isCacheMaintenance() || 34612350Snikos.nikoleris@arm.com tgt_pkt->req->isCacheMaintenance() || 34712350Snikos.nikoleris@arm.com !deferredTargets.empty() || 34812350Snikos.nikoleris@arm.com (inService && 34912350Snikos.nikoleris@arm.com (hasPostInvalidate() || 35012350Snikos.nikoleris@arm.com (pkt->needsWritable() && 35112350Snikos.nikoleris@arm.com (!isPendingModified() || hasPostDowngrade() || isForward))))) { 3524903SN/A // need to put on deferred list 35312350Snikos.nikoleris@arm.com if (inService && hasPostInvalidate()) 3547667Ssteve.reinhardt@amd.com replaceUpgrade(pkt); 35511741Snikos.nikoleris@arm.com deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true, 35611741Snikos.nikoleris@arm.com alloc_on_fill); 3574665SN/A } else { 3585318SN/A // No request outstanding, or still OK to append to 3595318SN/A // outstanding request: append to regular target list. Only 3605318SN/A // mark pending if current request hasn't been issued yet 3615318SN/A // (isn't in service). 36211741Snikos.nikoleris@arm.com targets.add(pkt, whenReady, _order, Target::FromCPU, !inService, 36311741Snikos.nikoleris@arm.com alloc_on_fill); 3642810SN/A } 3654665SN/A} 3664665SN/A 3674902SN/Abool 3684902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order) 3694665SN/A{ 37011744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 37111279Sandreas.hansson@arm.com 37211284Sandreas.hansson@arm.com // when we snoop packets the needsWritable and isInvalidate flags 37311279Sandreas.hansson@arm.com // should always be the same, however, this assumes that we never 37411279Sandreas.hansson@arm.com // snoop writes as they are currently not marked as invalidations 37512350Snikos.nikoleris@arm.com panic_if((pkt->needsWritable() != pkt->isInvalidate()) && 37612350Snikos.nikoleris@arm.com !pkt->req->isCacheMaintenance(), 37711744Snikos.nikoleris@arm.com "%s got snoop %s where needsWritable, " 37811863Snikos.nikoleris@arm.com "does not match isInvalidate", name(), pkt->print()); 37911279Sandreas.hansson@arm.com 3804910SN/A if (!inService || (pkt->isExpressSnoop() && downstreamPending)) { 3814903SN/A // Request has not been issued yet, or it's been issued 3824903SN/A // locally but is buffered unissued at some downstream cache 3834903SN/A // which is forwarding us this snoop. Either way, the packet 3844903SN/A // we're snooping logically precedes this MSHR's request, so 3854903SN/A // the snoop has no impact on the MSHR, but must be processed 3864903SN/A // in the standard way by the cache. The only exception is 3874903SN/A // that if we're an L2+ cache buffering an UpgradeReq from a 3884903SN/A // higher-level cache, and the snoop is invalidating, then our 3894903SN/A // buffered upgrades must be converted to read exclusives, 3904903SN/A // since the upper-level cache no longer has a valid copy. 3914903SN/A // That is, even though the upper-level cache got out on its 3924903SN/A // local bus first, some other invalidating transaction 3934903SN/A // reached the global bus before the upgrade did. 39412350Snikos.nikoleris@arm.com if (pkt->needsWritable() || pkt->req->isCacheInvalidate()) { 3959725Sandreas.hansson@arm.com targets.replaceUpgrades(); 3969725Sandreas.hansson@arm.com deferredTargets.replaceUpgrades(); 3974903SN/A } 3984903SN/A 3994902SN/A return false; 4004902SN/A } 4014665SN/A 4024903SN/A // From here on down, the request issued by this MSHR logically 4034903SN/A // precedes the request we're snooping. 40412350Snikos.nikoleris@arm.com if (pkt->needsWritable() || pkt->req->isCacheInvalidate()) { 4054903SN/A // snooped request still precedes the re-request we'll have to 4064903SN/A // issue for deferred targets, if any... 4079725Sandreas.hansson@arm.com deferredTargets.replaceUpgrades(); 4084903SN/A } 4094903SN/A 41012350Snikos.nikoleris@arm.com PacketPtr tgt_pkt = targets.front().pkt; 41112350Snikos.nikoleris@arm.com if (hasPostInvalidate() || tgt_pkt->req->isCacheInvalidate()) { 41212350Snikos.nikoleris@arm.com // a prior snoop has already appended an invalidation or a 41312350Snikos.nikoleris@arm.com // cache invalidation operation is in progress, so logically 41412350Snikos.nikoleris@arm.com // we don't have the block anymore; no need for further 41512350Snikos.nikoleris@arm.com // snooping. 4164902SN/A return true; 4174665SN/A } 4184665SN/A 41911284Sandreas.hansson@arm.com if (isPendingModified() || pkt->isInvalidate()) { 4207667Ssteve.reinhardt@amd.com // We need to save and replay the packet in two cases: 42111284Sandreas.hansson@arm.com // 1. We're awaiting a writable copy (Modified or Exclusive), 42211284Sandreas.hansson@arm.com // so this MSHR is the orgering point, and we need to respond 42311284Sandreas.hansson@arm.com // after we receive data. 4247667Ssteve.reinhardt@amd.com // 2. It's an invalidation (e.g., UpgradeReq), and we need 4257667Ssteve.reinhardt@amd.com // to forward the snoop up the hierarchy after the current 4267667Ssteve.reinhardt@amd.com // transaction completes. 42710571Sandreas.hansson@arm.com 42811271Sandreas.hansson@arm.com // Start by determining if we will eventually respond or not, 42911271Sandreas.hansson@arm.com // matching the conditions checked in Cache::handleSnoop 43012350Snikos.nikoleris@arm.com bool will_respond = isPendingModified() && pkt->needsResponse() && 43112350Snikos.nikoleris@arm.com !pkt->isClean(); 43211271Sandreas.hansson@arm.com 43311271Sandreas.hansson@arm.com // The packet we are snooping may be deleted by the time we 43411271Sandreas.hansson@arm.com // actually process the target, and we consequently need to 43511271Sandreas.hansson@arm.com // save a copy here. Clear flags and also allocate new data as 43611271Sandreas.hansson@arm.com // the original packet data storage may have been deleted by 43711271Sandreas.hansson@arm.com // the time we get to process this packet. In the cases where 43811271Sandreas.hansson@arm.com // we are not responding after handling the snoop we also need 43911271Sandreas.hansson@arm.com // to create a copy of the request to be on the safe side. In 44011271Sandreas.hansson@arm.com // the latter case the cache is responsible for deleting both 44111271Sandreas.hansson@arm.com // the packet and the request as part of handling the deferred 44211271Sandreas.hansson@arm.com // snoop. 44311271Sandreas.hansson@arm.com PacketPtr cp_pkt = will_respond ? new Packet(pkt, true, true) : 44412749Sgiacomo.travaglini@arm.com new Packet(std::make_shared<Request>(*pkt->req), pkt->cmd, 44512749Sgiacomo.travaglini@arm.com blkSize, pkt->id); 4464670SN/A 44711490Sandreas.hansson@arm.com if (will_respond) { 44811284Sandreas.hansson@arm.com // we are the ordering point, and will consequently 44911284Sandreas.hansson@arm.com // respond, and depending on whether the packet 45011284Sandreas.hansson@arm.com // needsWritable or not we either pass a Shared line or a 45111284Sandreas.hansson@arm.com // Modified line 45211284Sandreas.hansson@arm.com pkt->setCacheResponding(); 45311284Sandreas.hansson@arm.com 45411284Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 45511284Sandreas.hansson@arm.com // in the Modified state, even if the response is passed 45611284Sandreas.hansson@arm.com // as Shared (and thus non-writable) 45711284Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 45811284Sandreas.hansson@arm.com 45910821Sandreas.hansson@arm.com // in the case of an uncacheable request there is no need 46011284Sandreas.hansson@arm.com // to set the responderHadWritable flag, but since the 46111284Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 4624670SN/A } 46310826Sstephan.diestelhorst@ARM.com targets.add(cp_pkt, curTick(), _order, Target::FromSnoop, 46411741Snikos.nikoleris@arm.com downstreamPending && targets.needsWritable, false); 4654670SN/A 46612350Snikos.nikoleris@arm.com if (pkt->needsWritable() || pkt->isInvalidate()) { 4674670SN/A // This transaction will take away our pending copy 4687667Ssteve.reinhardt@amd.com postInvalidate = true; 4694670SN/A } 47012350Snikos.nikoleris@arm.com 47112501Snikos.nikoleris@arm.com if (isPendingModified() && pkt->isClean()) { 47212350Snikos.nikoleris@arm.com pkt->setSatisfied(); 47312350Snikos.nikoleris@arm.com } 4747667Ssteve.reinhardt@amd.com } 4757667Ssteve.reinhardt@amd.com 47611284Sandreas.hansson@arm.com if (!pkt->needsWritable() && !pkt->req->isUncacheable()) { 4777667Ssteve.reinhardt@amd.com // This transaction will get a read-shared copy, downgrading 47811284Sandreas.hansson@arm.com // our copy if we had a writable one 4797667Ssteve.reinhardt@amd.com postDowngrade = true; 48011284Sandreas.hansson@arm.com // make sure that any downstream cache does not respond with a 48111284Sandreas.hansson@arm.com // writable (and dirty) copy even if it has one, unless it was 48211284Sandreas.hansson@arm.com // explicitly asked for one 48311284Sandreas.hansson@arm.com pkt->setHasSharers(); 4844667SN/A } 4854902SN/A 4864902SN/A return true; 4874665SN/A} 4884665SN/A 48911742Snikos.nikoleris@arm.comMSHR::TargetList 49011742Snikos.nikoleris@arm.comMSHR::extractServiceableTargets(PacketPtr pkt) 49111742Snikos.nikoleris@arm.com{ 49211742Snikos.nikoleris@arm.com TargetList ready_targets; 49313349Snikos.nikoleris@arm.com ready_targets.init(blkAddr, blkSize); 49411742Snikos.nikoleris@arm.com // If the downstream MSHR got an invalidation request then we only 49511742Snikos.nikoleris@arm.com // service the first of the FromCPU targets and any other 49611742Snikos.nikoleris@arm.com // non-FromCPU target. This way the remaining FromCPU targets 49711742Snikos.nikoleris@arm.com // issue a new request and get a fresh copy of the block and we 49811742Snikos.nikoleris@arm.com // avoid memory consistency violations. 49911742Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::ReadRespWithInvalidate) { 50011742Snikos.nikoleris@arm.com auto it = targets.begin(); 50111866Ssascha.bischoff@arm.com assert((it->source == Target::FromCPU) || 50211866Ssascha.bischoff@arm.com (it->source == Target::FromPrefetcher)); 50311742Snikos.nikoleris@arm.com ready_targets.push_back(*it); 50411742Snikos.nikoleris@arm.com it = targets.erase(it); 50511742Snikos.nikoleris@arm.com while (it != targets.end()) { 50611742Snikos.nikoleris@arm.com if (it->source == Target::FromCPU) { 50711742Snikos.nikoleris@arm.com it++; 50811742Snikos.nikoleris@arm.com } else { 50911742Snikos.nikoleris@arm.com assert(it->source == Target::FromSnoop); 51011742Snikos.nikoleris@arm.com ready_targets.push_back(*it); 51111742Snikos.nikoleris@arm.com it = targets.erase(it); 51211742Snikos.nikoleris@arm.com } 51311742Snikos.nikoleris@arm.com } 51411742Snikos.nikoleris@arm.com ready_targets.populateFlags(); 51511742Snikos.nikoleris@arm.com } else { 51611742Snikos.nikoleris@arm.com std::swap(ready_targets, targets); 51711742Snikos.nikoleris@arm.com } 51811742Snikos.nikoleris@arm.com targets.populateFlags(); 51911742Snikos.nikoleris@arm.com 52011742Snikos.nikoleris@arm.com return ready_targets; 52111742Snikos.nikoleris@arm.com} 5224665SN/A 5234665SN/Abool 5244665SN/AMSHR::promoteDeferredTargets() 5254665SN/A{ 52612350Snikos.nikoleris@arm.com if (targets.empty() && deferredTargets.empty()) { 52712350Snikos.nikoleris@arm.com // nothing to promote 52812350Snikos.nikoleris@arm.com return false; 5294665SN/A } 5304665SN/A 53112350Snikos.nikoleris@arm.com // the deferred targets can be generally promoted unless they 53212350Snikos.nikoleris@arm.com // contain a cache maintenance request 5334903SN/A 53412350Snikos.nikoleris@arm.com // find the first target that is a cache maintenance request 53512350Snikos.nikoleris@arm.com auto it = std::find_if(deferredTargets.begin(), deferredTargets.end(), 53612350Snikos.nikoleris@arm.com [](MSHR::Target &t) { 53712350Snikos.nikoleris@arm.com return t.pkt->req->isCacheMaintenance(); 53812350Snikos.nikoleris@arm.com }); 53912350Snikos.nikoleris@arm.com if (it == deferredTargets.begin()) { 54012350Snikos.nikoleris@arm.com // if the first deferred target is a cache maintenance packet 54112350Snikos.nikoleris@arm.com // then we can promote provided the targets list is empty and 54212350Snikos.nikoleris@arm.com // we can service it on its own 54312350Snikos.nikoleris@arm.com if (targets.empty()) { 54412350Snikos.nikoleris@arm.com targets.splice(targets.end(), deferredTargets, it); 54512350Snikos.nikoleris@arm.com } 54612350Snikos.nikoleris@arm.com } else { 54712350Snikos.nikoleris@arm.com // if a cache maintenance operation exists, we promote all the 54812350Snikos.nikoleris@arm.com // deferred targets that precede it, or all deferred targets 54912350Snikos.nikoleris@arm.com // otherwise 55012350Snikos.nikoleris@arm.com targets.splice(targets.end(), deferredTargets, 55112350Snikos.nikoleris@arm.com deferredTargets.begin(), it); 55212350Snikos.nikoleris@arm.com } 55312350Snikos.nikoleris@arm.com 55412350Snikos.nikoleris@arm.com deferredTargets.populateFlags(); 55512350Snikos.nikoleris@arm.com targets.populateFlags(); 5569725Sandreas.hansson@arm.com order = targets.front().order; 5579725Sandreas.hansson@arm.com readyTime = std::max(curTick(), targets.front().readyTime); 5584665SN/A 5594665SN/A return true; 5602810SN/A} 5612810SN/A 56212793Snikos.nikoleris@arm.comvoid 56312793Snikos.nikoleris@arm.comMSHR::promoteIf(const std::function<bool (Target &)>& pred) 56412793Snikos.nikoleris@arm.com{ 56512793Snikos.nikoleris@arm.com // if any of the deferred targets were upper-level cache 56612793Snikos.nikoleris@arm.com // requests marked downstreamPending, need to clear that 56712793Snikos.nikoleris@arm.com assert(!downstreamPending); // not pending here anymore 56812793Snikos.nikoleris@arm.com 56912793Snikos.nikoleris@arm.com // find the first target does not satisfy the condition 57012793Snikos.nikoleris@arm.com auto last_it = std::find_if_not(deferredTargets.begin(), 57112793Snikos.nikoleris@arm.com deferredTargets.end(), 57212793Snikos.nikoleris@arm.com pred); 57312793Snikos.nikoleris@arm.com 57412793Snikos.nikoleris@arm.com // for the prefix of the deferredTargets [begin(), last_it) clear 57512793Snikos.nikoleris@arm.com // the downstreamPending flag and move them to the target list 57612793Snikos.nikoleris@arm.com deferredTargets.clearDownstreamPending(deferredTargets.begin(), 57712793Snikos.nikoleris@arm.com last_it); 57812793Snikos.nikoleris@arm.com targets.splice(targets.end(), deferredTargets, 57912793Snikos.nikoleris@arm.com deferredTargets.begin(), last_it); 58012793Snikos.nikoleris@arm.com // We need to update the flags for the target lists after the 58112793Snikos.nikoleris@arm.com // modifications 58212793Snikos.nikoleris@arm.com deferredTargets.populateFlags(); 58312793Snikos.nikoleris@arm.com} 58412793Snikos.nikoleris@arm.com 58512793Snikos.nikoleris@arm.comvoid 58612793Snikos.nikoleris@arm.comMSHR::promoteReadable() 58712793Snikos.nikoleris@arm.com{ 58812793Snikos.nikoleris@arm.com if (!deferredTargets.empty() && !hasPostInvalidate()) { 58912793Snikos.nikoleris@arm.com // We got a non invalidating response, and we have the block 59012793Snikos.nikoleris@arm.com // but we have deferred targets which are waiting and they do 59112793Snikos.nikoleris@arm.com // not need writable. This can happen if the original request 59212793Snikos.nikoleris@arm.com // was for a cache clean operation and we had a copy of the 59312793Snikos.nikoleris@arm.com // block. Since we serviced the cache clean operation and we 59412793Snikos.nikoleris@arm.com // have the block, there's no need to defer the targets, so 59512793Snikos.nikoleris@arm.com // move them up to the regular target list. 59612793Snikos.nikoleris@arm.com 59712793Snikos.nikoleris@arm.com auto pred = [](Target &t) { 59812793Snikos.nikoleris@arm.com assert(t.source == Target::FromCPU); 59912793Snikos.nikoleris@arm.com return !t.pkt->req->isCacheInvalidate() && 60012793Snikos.nikoleris@arm.com !t.pkt->needsWritable(); 60112793Snikos.nikoleris@arm.com }; 60212793Snikos.nikoleris@arm.com promoteIf(pred); 60312793Snikos.nikoleris@arm.com } 60412793Snikos.nikoleris@arm.com} 6052810SN/A 6062810SN/Avoid 60711284Sandreas.hansson@arm.comMSHR::promoteWritable() 6084668SN/A{ 60911284Sandreas.hansson@arm.com if (deferredTargets.needsWritable && 61011177Sandreas.hansson@arm.com !(hasPostInvalidate() || hasPostDowngrade())) { 61111284Sandreas.hansson@arm.com // We got a writable response, but we have deferred targets 61211284Sandreas.hansson@arm.com // which are waiting to request a writable copy (not because 6135270SN/A // of a pending invalidate). This can happen if the original 61411284Sandreas.hansson@arm.com // request was for a read-only block, but we got a writable 61511284Sandreas.hansson@arm.com // response anyway. Since we got the writable copy there's no 61611284Sandreas.hansson@arm.com // need to defer the targets, so move them up to the regular 61711284Sandreas.hansson@arm.com // target list. 61811284Sandreas.hansson@arm.com assert(!targets.needsWritable); 61911284Sandreas.hansson@arm.com targets.needsWritable = true; 62012792Snikos.nikoleris@arm.com 62112793Snikos.nikoleris@arm.com auto pred = [](Target &t) { 62212793Snikos.nikoleris@arm.com assert(t.source == Target::FromCPU); 62312793Snikos.nikoleris@arm.com return !t.pkt->req->isCacheInvalidate(); 62412793Snikos.nikoleris@arm.com }; 62512793Snikos.nikoleris@arm.com 62612793Snikos.nikoleris@arm.com promoteIf(pred); 6275270SN/A } 6284668SN/A} 6294668SN/A 6304668SN/A 6315314SN/Abool 63212823Srmk35@cl.cam.ac.ukMSHR::trySatisfyFunctional(PacketPtr pkt) 6335314SN/A{ 6345314SN/A // For printing, we treat the MSHR as a whole as single entity. 6355314SN/A // For other requests, we iterate over the individual targets 6365314SN/A // since that's where the actual data lies. 6375314SN/A if (pkt->isPrint()) { 63812823Srmk35@cl.cam.ac.uk pkt->trySatisfyFunctional(this, blkAddr, isSecure, blkSize, nullptr); 6395314SN/A return false; 6405314SN/A } else { 64112823Srmk35@cl.cam.ac.uk return (targets.trySatisfyFunctional(pkt) || 64212823Srmk35@cl.cam.ac.uk deferredTargets.trySatisfyFunctional(pkt)); 6435314SN/A } 6445314SN/A} 6455314SN/A 64611375Sandreas.hansson@arm.combool 64712724Snikos.nikoleris@arm.comMSHR::sendPacket(BaseCache &cache) 64811375Sandreas.hansson@arm.com{ 64911375Sandreas.hansson@arm.com return cache.sendMSHRQueuePacket(this); 65011375Sandreas.hansson@arm.com} 6515314SN/A 6524668SN/Avoid 6535314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const 6542810SN/A{ 65512715Snikos.nikoleris@arm.com ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s %s\n", 65610764Sandreas.hansson@arm.com prefix, blkAddr, blkAddr + blkSize - 1, 65710028SGiacomo.Gabrielli@arm.com isSecure ? "s" : "ns", 6585730SSteve.Reinhardt@amd.com isForward ? "Forward" : "", 65911741Snikos.nikoleris@arm.com allocOnFill() ? "AllocOnFill" : "", 66011284Sandreas.hansson@arm.com needsWritable() ? "Wrtbl" : "", 6615314SN/A _isUncacheable ? "Unc" : "", 6625314SN/A inService ? "InSvc" : "", 6635314SN/A downstreamPending ? "DwnPend" : "", 66411610Snikos.nikoleris@arm.com postInvalidate ? "PostInv" : "", 66512715Snikos.nikoleris@arm.com postDowngrade ? "PostDowngr" : "", 66612715Snikos.nikoleris@arm.com hasFromCache() ? "HasFromCache" : ""); 6672810SN/A 66811610Snikos.nikoleris@arm.com if (!targets.empty()) { 66911610Snikos.nikoleris@arm.com ccprintf(os, "%s Targets:\n", prefix); 67011610Snikos.nikoleris@arm.com targets.print(os, verbosity, prefix + " "); 67111610Snikos.nikoleris@arm.com } 6729725Sandreas.hansson@arm.com if (!deferredTargets.empty()) { 6735314SN/A ccprintf(os, "%s Deferred Targets:\n", prefix); 6749725Sandreas.hansson@arm.com deferredTargets.print(os, verbosity, prefix + " "); 6752810SN/A } 6762810SN/A} 6772810SN/A 6789663Suri.wiener@arm.comstd::string 6799663Suri.wiener@arm.comMSHR::print() const 6809663Suri.wiener@arm.com{ 68112637Sodanrc@yahoo.com.br std::ostringstream str; 6829663Suri.wiener@arm.com print(str); 6839663Suri.wiener@arm.com return str.str(); 6849663Suri.wiener@arm.com} 685