mshr.cc revision 12791
12810SN/A/*
212501Snikos.nikoleris@arm.com * Copyright (c) 2012-2013, 2015-2018 ARM Limited
39663Suri.wiener@arm.com * All rights reserved.
49663Suri.wiener@arm.com *
59663Suri.wiener@arm.com * The license below extends only to copyright in the software and shall
69663Suri.wiener@arm.com * not be construed as granting a license to any other intellectual
79663Suri.wiener@arm.com * property including but not limited to intellectual property relating
89663Suri.wiener@arm.com * to a hardware implementation of the functionality of the software
99663Suri.wiener@arm.com * licensed hereunder.  You may use the software subject to the license
109663Suri.wiener@arm.com * terms below provided that you ensure that this notice is replicated
119663Suri.wiener@arm.com * unmodified and in its entirety in all distributions of the software,
129663Suri.wiener@arm.com * modified or unmodified, in source code or in binary form.
139663Suri.wiener@arm.com *
142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
157636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
162810SN/A * All rights reserved.
172810SN/A *
182810SN/A * Redistribution and use in source and binary forms, with or without
192810SN/A * modification, are permitted provided that the following conditions are
202810SN/A * met: redistributions of source code must retain the above copyright
212810SN/A * notice, this list of conditions and the following disclaimer;
222810SN/A * redistributions in binary form must reproduce the above copyright
232810SN/A * notice, this list of conditions and the following disclaimer in the
242810SN/A * documentation and/or other materials provided with the distribution;
252810SN/A * neither the name of the copyright holders nor the names of its
262810SN/A * contributors may be used to endorse or promote products derived from
272810SN/A * this software without specific prior written permission.
282810SN/A *
292810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402810SN/A *
412810SN/A * Authors: Erik Hallnor
422810SN/A *          Dave Greene
432810SN/A */
442810SN/A
452810SN/A/**
462810SN/A * @file
472810SN/A * Miss Status and Handling Register (MSHR) definitions.
482810SN/A */
492810SN/A
5011486Snikos.nikoleris@arm.com#include "mem/cache/mshr.hh"
5111486Snikos.nikoleris@arm.com
526216Snate@binkert.org#include <cassert>
532810SN/A#include <string>
542810SN/A
5512334Sgabeblack@google.com#include "base/logging.hh"
5612727Snikos.nikoleris@arm.com#include "base/trace.hh"
576216Snate@binkert.org#include "base/types.hh"
588232Snate@binkert.org#include "debug/Cache.hh"
5912727Snikos.nikoleris@arm.com#include "mem/cache/base.hh"
6012727Snikos.nikoleris@arm.com#include "mem/request.hh"
616216Snate@binkert.org#include "sim/core.hh"
622810SN/A
6311375Sandreas.hansson@arm.comMSHR::MSHR() : downstreamPending(false),
6411284Sandreas.hansson@arm.com               pendingModified(false),
6510503SCurtis.Dunham@arm.com               postInvalidate(false), postDowngrade(false),
6611741Snikos.nikoleris@arm.com               isForward(false)
672810SN/A{
682810SN/A}
692810SN/A
704903SN/AMSHR::TargetList::TargetList()
7112715Snikos.nikoleris@arm.com    : needsWritable(false), hasUpgrade(false), allocOnFill(false),
7212715Snikos.nikoleris@arm.com      hasFromCache(false)
734903SN/A{}
744903SN/A
754903SN/A
7611740Snikos.nikoleris@arm.comvoid
7711741Snikos.nikoleris@arm.comMSHR::TargetList::updateFlags(PacketPtr pkt, Target::Source source,
7811741Snikos.nikoleris@arm.com                              bool alloc_on_fill)
794903SN/A{
805875Ssteve.reinhardt@amd.com    if (source != Target::FromSnoop) {
8111284Sandreas.hansson@arm.com        if (pkt->needsWritable()) {
8211284Sandreas.hansson@arm.com            needsWritable = true;
834903SN/A        }
844903SN/A
857669Ssteve.reinhardt@amd.com        // StoreCondReq is effectively an upgrade if it's in an MSHR
867669Ssteve.reinhardt@amd.com        // since it would have been failed already if we didn't have a
877669Ssteve.reinhardt@amd.com        // read-only copy
887669Ssteve.reinhardt@amd.com        if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
894903SN/A            hasUpgrade = true;
904903SN/A        }
9111741Snikos.nikoleris@arm.com
9211741Snikos.nikoleris@arm.com        // potentially re-evaluate whether we should allocate on a fill or
9311741Snikos.nikoleris@arm.com        // not
9411741Snikos.nikoleris@arm.com        allocOnFill = allocOnFill || alloc_on_fill;
9512715Snikos.nikoleris@arm.com
9612715Snikos.nikoleris@arm.com        if (source != Target::FromPrefetcher) {
9712715Snikos.nikoleris@arm.com            hasFromCache = hasFromCache || pkt->fromCache();
9812715Snikos.nikoleris@arm.com        }
995318SN/A    }
10011740Snikos.nikoleris@arm.com}
1014908SN/A
10211740Snikos.nikoleris@arm.comvoid
10311740Snikos.nikoleris@arm.comMSHR::TargetList::populateFlags()
10411740Snikos.nikoleris@arm.com{
10511740Snikos.nikoleris@arm.com    resetFlags();
10611740Snikos.nikoleris@arm.com    for (auto& t: *this) {
10711741Snikos.nikoleris@arm.com        updateFlags(t.pkt, t.source, t.allocOnFill);
10811740Snikos.nikoleris@arm.com    }
10911740Snikos.nikoleris@arm.com}
11011740Snikos.nikoleris@arm.com
11111740Snikos.nikoleris@arm.cominline void
11211740Snikos.nikoleris@arm.comMSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
11311741Snikos.nikoleris@arm.com                      Counter order, Target::Source source, bool markPending,
11411741Snikos.nikoleris@arm.com                      bool alloc_on_fill)
11511740Snikos.nikoleris@arm.com{
11611741Snikos.nikoleris@arm.com    updateFlags(pkt, source, alloc_on_fill);
1175318SN/A    if (markPending) {
1189543Ssascha.bischoff@arm.com        // Iterate over the SenderState stack and see if we find
1199543Ssascha.bischoff@arm.com        // an MSHR entry. If we do, set the downstreamPending
1209543Ssascha.bischoff@arm.com        // flag. Otherwise, do nothing.
1219543Ssascha.bischoff@arm.com        MSHR *mshr = pkt->findNextSenderState<MSHR>();
12211484Snikos.nikoleris@arm.com        if (mshr != nullptr) {
1234908SN/A            assert(!mshr->downstreamPending);
1244908SN/A            mshr->downstreamPending = true;
12511083Sandreas.hansson@arm.com        } else {
12611083Sandreas.hansson@arm.com            // No need to clear downstreamPending later
12711083Sandreas.hansson@arm.com            markPending = false;
1284908SN/A        }
1294903SN/A    }
1304903SN/A
13111741Snikos.nikoleris@arm.com    emplace_back(pkt, readyTime, order, source, markPending, alloc_on_fill);
1324903SN/A}
1334903SN/A
1344903SN/A
1357667Ssteve.reinhardt@amd.comstatic void
1367667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt)
1377667Ssteve.reinhardt@amd.com{
13811286Sandreas.hansson@arm.com    // remember if the current packet has data allocated
13911286Sandreas.hansson@arm.com    bool has_data = pkt->hasData() || pkt->hasRespData();
14011286Sandreas.hansson@arm.com
1417667Ssteve.reinhardt@amd.com    if (pkt->cmd == MemCmd::UpgradeReq) {
1427667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::ReadExReq;
1437667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
1447667Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
1457667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::SCUpgradeFailReq;
1467667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
1477669Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::StoreCondReq) {
1487669Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::StoreCondFailReq;
1497669Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
1507667Ssteve.reinhardt@amd.com    }
15111286Sandreas.hansson@arm.com
15211286Sandreas.hansson@arm.com    if (!has_data) {
15311286Sandreas.hansson@arm.com        // there is no sensible way of setting the data field if the
15411286Sandreas.hansson@arm.com        // new command actually would carry data
15511286Sandreas.hansson@arm.com        assert(!pkt->hasData());
15611286Sandreas.hansson@arm.com
15711286Sandreas.hansson@arm.com        if (pkt->hasRespData()) {
15811286Sandreas.hansson@arm.com            // we went from a packet that had no data (neither request,
15911286Sandreas.hansson@arm.com            // nor response), to one that does, and therefore we need to
16011286Sandreas.hansson@arm.com            // actually allocate space for the data payload
16111286Sandreas.hansson@arm.com            pkt->allocate();
16211286Sandreas.hansson@arm.com        }
16311286Sandreas.hansson@arm.com    }
1647667Ssteve.reinhardt@amd.com}
1657667Ssteve.reinhardt@amd.com
1667667Ssteve.reinhardt@amd.com
1674903SN/Avoid
1684903SN/AMSHR::TargetList::replaceUpgrades()
1694903SN/A{
1704903SN/A    if (!hasUpgrade)
1714903SN/A        return;
1724903SN/A
17310766Sandreas.hansson@arm.com    for (auto& t : *this) {
17410766Sandreas.hansson@arm.com        replaceUpgrade(t.pkt);
1754903SN/A    }
1764903SN/A
1774903SN/A    hasUpgrade = false;
1784903SN/A}
1794903SN/A
1804903SN/A
1812810SN/Avoid
18212791Snikos.nikoleris@arm.comMSHR::TargetList::clearDownstreamPending(MSHR::TargetList::iterator begin,
18312791Snikos.nikoleris@arm.com                                         MSHR::TargetList::iterator end)
1844908SN/A{
18512791Snikos.nikoleris@arm.com    for (auto t = begin; t != end; t++) {
18612791Snikos.nikoleris@arm.com        if (t->markedPending) {
1879543Ssascha.bischoff@arm.com            // Iterate over the SenderState stack and see if we find
1889543Ssascha.bischoff@arm.com            // an MSHR entry. If we find one, clear the
1899543Ssascha.bischoff@arm.com            // downstreamPending flag by calling
1909543Ssascha.bischoff@arm.com            // clearDownstreamPending(). This recursively clears the
1919543Ssascha.bischoff@arm.com            // downstreamPending flag in all caches this packet has
1929543Ssascha.bischoff@arm.com            // passed through.
19312791Snikos.nikoleris@arm.com            MSHR *mshr = t->pkt->findNextSenderState<MSHR>();
19411484Snikos.nikoleris@arm.com            if (mshr != nullptr) {
1955318SN/A                mshr->clearDownstreamPending();
1965318SN/A            }
19712791Snikos.nikoleris@arm.com            t->markedPending = false;
1984908SN/A        }
1994908SN/A    }
2004908SN/A}
2014908SN/A
20212791Snikos.nikoleris@arm.comvoid
20312791Snikos.nikoleris@arm.comMSHR::TargetList::clearDownstreamPending()
20412791Snikos.nikoleris@arm.com{
20512791Snikos.nikoleris@arm.com    clearDownstreamPending(begin(), end());
20612791Snikos.nikoleris@arm.com}
20712791Snikos.nikoleris@arm.com
2084908SN/A
2094920SN/Abool
2104920SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt)
2114920SN/A{
21210766Sandreas.hansson@arm.com    for (auto& t : *this) {
21310766Sandreas.hansson@arm.com        if (pkt->checkFunctional(t.pkt)) {
2144920SN/A            return true;
2154920SN/A        }
2164920SN/A    }
2174920SN/A
2184920SN/A    return false;
2194920SN/A}
2204920SN/A
2214920SN/A
2224908SN/Avoid
22310766Sandreas.hansson@arm.comMSHR::TargetList::print(std::ostream &os, int verbosity,
22410766Sandreas.hansson@arm.com                        const std::string &prefix) const
2255314SN/A{
22610766Sandreas.hansson@arm.com    for (auto& t : *this) {
2275875Ssteve.reinhardt@amd.com        const char *s;
22810766Sandreas.hansson@arm.com        switch (t.source) {
2298988SAli.Saidi@ARM.com          case Target::FromCPU:
2308988SAli.Saidi@ARM.com            s = "FromCPU";
2318988SAli.Saidi@ARM.com            break;
2328988SAli.Saidi@ARM.com          case Target::FromSnoop:
2338988SAli.Saidi@ARM.com            s = "FromSnoop";
2348988SAli.Saidi@ARM.com            break;
2358988SAli.Saidi@ARM.com          case Target::FromPrefetcher:
2368988SAli.Saidi@ARM.com            s = "FromPrefetcher";
2378988SAli.Saidi@ARM.com            break;
2388988SAli.Saidi@ARM.com          default:
2398988SAli.Saidi@ARM.com            s = "";
2408988SAli.Saidi@ARM.com            break;
2415875Ssteve.reinhardt@amd.com        }
2425875Ssteve.reinhardt@amd.com        ccprintf(os, "%s%s: ", prefix, s);
24310766Sandreas.hansson@arm.com        t.pkt->print(os, verbosity, "");
24411744Snikos.nikoleris@arm.com        ccprintf(os, "\n");
2455314SN/A    }
2465314SN/A}
2475314SN/A
2485314SN/A
2495314SN/Avoid
25010764Sandreas.hansson@arm.comMSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
25111197Sandreas.hansson@arm.com               Tick when_ready, Counter _order, bool alloc_on_fill)
2522810SN/A{
25310764Sandreas.hansson@arm.com    blkAddr = blk_addr;
25410764Sandreas.hansson@arm.com    blkSize = blk_size;
25510028SGiacomo.Gabrielli@arm.com    isSecure = target->isSecure();
25610764Sandreas.hansson@arm.com    readyTime = when_ready;
2574666SN/A    order = _order;
2584626SN/A    assert(target);
2595730SSteve.Reinhardt@amd.com    isForward = false;
2604626SN/A    _isUncacheable = target->req->isUncacheable();
2614626SN/A    inService = false;
2624908SN/A    downstreamPending = false;
2639725Sandreas.hansson@arm.com    assert(targets.isReset());
2644626SN/A    // Don't know of a case where we would allocate a new MSHR for a
2655875Ssteve.reinhardt@amd.com    // snoop (mem-side request), so set source according to request here
2665875Ssteve.reinhardt@amd.com    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
2675875Ssteve.reinhardt@amd.com        Target::FromPrefetcher : Target::FromCPU;
26811741Snikos.nikoleris@arm.com    targets.add(target, when_ready, _order, source, true, alloc_on_fill);
2699725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
2702810SN/A}
2712810SN/A
2724908SN/A
2735318SN/Avoid
2745318SN/AMSHR::clearDownstreamPending()
2755318SN/A{
2765318SN/A    assert(downstreamPending);
2775318SN/A    downstreamPending = false;
2785318SN/A    // recursively clear flag on any MSHRs we will be forwarding
2795318SN/A    // responses to
2809725Sandreas.hansson@arm.com    targets.clearDownstreamPending();
2815318SN/A}
2825318SN/A
28311375Sandreas.hansson@arm.comvoid
28411284Sandreas.hansson@arm.comMSHR::markInService(bool pending_modified_resp)
2854908SN/A{
2864908SN/A    assert(!inService);
28710424Sandreas.hansson@arm.com
2884908SN/A    inService = true;
28911284Sandreas.hansson@arm.com    pendingModified = targets.needsWritable || pending_modified_resp;
2907667Ssteve.reinhardt@amd.com    postInvalidate = postDowngrade = false;
2917667Ssteve.reinhardt@amd.com
2924908SN/A    if (!downstreamPending) {
2934908SN/A        // let upstream caches know that the request has made it to a
2944908SN/A        // level where it's going to get a response
2959725Sandreas.hansson@arm.com        targets.clearDownstreamPending();
2964908SN/A    }
2974908SN/A}
2984908SN/A
2994908SN/A
3002810SN/Avoid
3012810SN/AMSHR::deallocate()
3022810SN/A{
3039725Sandreas.hansson@arm.com    assert(targets.empty());
3049725Sandreas.hansson@arm.com    targets.resetFlags();
3059725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
3062810SN/A    inService = false;
3072810SN/A}
3082810SN/A
3092810SN/A/*
3102810SN/A * Adds a target to an MSHR
3112810SN/A */
3122810SN/Avoid
31311197Sandreas.hansson@arm.comMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order,
31411197Sandreas.hansson@arm.com                     bool alloc_on_fill)
3152810SN/A{
31610768Sandreas.hansson@arm.com    // assume we'd never issue a prefetch when we've got an
31710768Sandreas.hansson@arm.com    // outstanding miss
31810768Sandreas.hansson@arm.com    assert(pkt->cmd != MemCmd::HardPFReq);
31910768Sandreas.hansson@arm.com
3204903SN/A    // if there's a request already in service for this MSHR, we will
3214903SN/A    // have to defer the new target until after the response if any of
3224903SN/A    // the following are true:
3234903SN/A    // - there are other targets already deferred
3244903SN/A    // - there's a pending invalidate to be applied after the response
3254903SN/A    //   comes back (but before this target is processed)
32612350Snikos.nikoleris@arm.com    // - the MSHR's first (and only) non-deferred target is a cache
32712350Snikos.nikoleris@arm.com    //   maintenance packet
32812350Snikos.nikoleris@arm.com    // - the new target is a cache maintenance packet (this is probably
32912350Snikos.nikoleris@arm.com    //   overly conservative but certainly safe)
33011284Sandreas.hansson@arm.com    // - this target requires a writable block and either we're not
33111284Sandreas.hansson@arm.com    //   getting a writable block back or we have already snooped
33211284Sandreas.hansson@arm.com    //   another read request that will downgrade our writable block
33311284Sandreas.hansson@arm.com    //   to non-writable (Shared or Owned)
33412350Snikos.nikoleris@arm.com    PacketPtr tgt_pkt = targets.front().pkt;
33512350Snikos.nikoleris@arm.com    if (pkt->req->isCacheMaintenance() ||
33612350Snikos.nikoleris@arm.com        tgt_pkt->req->isCacheMaintenance() ||
33712350Snikos.nikoleris@arm.com        !deferredTargets.empty() ||
33812350Snikos.nikoleris@arm.com        (inService &&
33912350Snikos.nikoleris@arm.com         (hasPostInvalidate() ||
34012350Snikos.nikoleris@arm.com          (pkt->needsWritable() &&
34112350Snikos.nikoleris@arm.com           (!isPendingModified() || hasPostDowngrade() || isForward))))) {
3424903SN/A        // need to put on deferred list
34312350Snikos.nikoleris@arm.com        if (inService && hasPostInvalidate())
3447667Ssteve.reinhardt@amd.com            replaceUpgrade(pkt);
34511741Snikos.nikoleris@arm.com        deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true,
34611741Snikos.nikoleris@arm.com                            alloc_on_fill);
3474665SN/A    } else {
3485318SN/A        // No request outstanding, or still OK to append to
3495318SN/A        // outstanding request: append to regular target list.  Only
3505318SN/A        // mark pending if current request hasn't been issued yet
3515318SN/A        // (isn't in service).
35211741Snikos.nikoleris@arm.com        targets.add(pkt, whenReady, _order, Target::FromCPU, !inService,
35311741Snikos.nikoleris@arm.com                    alloc_on_fill);
3542810SN/A    }
3554665SN/A}
3564665SN/A
3574902SN/Abool
3584902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order)
3594665SN/A{
36011744Snikos.nikoleris@arm.com    DPRINTF(Cache, "%s for %s\n", __func__, pkt->print());
36111279Sandreas.hansson@arm.com
36211284Sandreas.hansson@arm.com    // when we snoop packets the needsWritable and isInvalidate flags
36311279Sandreas.hansson@arm.com    // should always be the same, however, this assumes that we never
36411279Sandreas.hansson@arm.com    // snoop writes as they are currently not marked as invalidations
36512350Snikos.nikoleris@arm.com    panic_if((pkt->needsWritable() != pkt->isInvalidate()) &&
36612350Snikos.nikoleris@arm.com             !pkt->req->isCacheMaintenance(),
36711744Snikos.nikoleris@arm.com             "%s got snoop %s where needsWritable, "
36811863Snikos.nikoleris@arm.com             "does not match isInvalidate", name(), pkt->print());
36911279Sandreas.hansson@arm.com
3704910SN/A    if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
3714903SN/A        // Request has not been issued yet, or it's been issued
3724903SN/A        // locally but is buffered unissued at some downstream cache
3734903SN/A        // which is forwarding us this snoop.  Either way, the packet
3744903SN/A        // we're snooping logically precedes this MSHR's request, so
3754903SN/A        // the snoop has no impact on the MSHR, but must be processed
3764903SN/A        // in the standard way by the cache.  The only exception is
3774903SN/A        // that if we're an L2+ cache buffering an UpgradeReq from a
3784903SN/A        // higher-level cache, and the snoop is invalidating, then our
3794903SN/A        // buffered upgrades must be converted to read exclusives,
3804903SN/A        // since the upper-level cache no longer has a valid copy.
3814903SN/A        // That is, even though the upper-level cache got out on its
3824903SN/A        // local bus first, some other invalidating transaction
3834903SN/A        // reached the global bus before the upgrade did.
38412350Snikos.nikoleris@arm.com        if (pkt->needsWritable() || pkt->req->isCacheInvalidate()) {
3859725Sandreas.hansson@arm.com            targets.replaceUpgrades();
3869725Sandreas.hansson@arm.com            deferredTargets.replaceUpgrades();
3874903SN/A        }
3884903SN/A
3894902SN/A        return false;
3904902SN/A    }
3914665SN/A
3924903SN/A    // From here on down, the request issued by this MSHR logically
3934903SN/A    // precedes the request we're snooping.
39412350Snikos.nikoleris@arm.com    if (pkt->needsWritable() || pkt->req->isCacheInvalidate()) {
3954903SN/A        // snooped request still precedes the re-request we'll have to
3964903SN/A        // issue for deferred targets, if any...
3979725Sandreas.hansson@arm.com        deferredTargets.replaceUpgrades();
3984903SN/A    }
3994903SN/A
40012350Snikos.nikoleris@arm.com    PacketPtr tgt_pkt = targets.front().pkt;
40112350Snikos.nikoleris@arm.com    if (hasPostInvalidate() || tgt_pkt->req->isCacheInvalidate()) {
40212350Snikos.nikoleris@arm.com        // a prior snoop has already appended an invalidation or a
40312350Snikos.nikoleris@arm.com        // cache invalidation operation is in progress, so logically
40412350Snikos.nikoleris@arm.com        // we don't have the block anymore; no need for further
40512350Snikos.nikoleris@arm.com        // snooping.
4064902SN/A        return true;
4074665SN/A    }
4084665SN/A
40911284Sandreas.hansson@arm.com    if (isPendingModified() || pkt->isInvalidate()) {
4107667Ssteve.reinhardt@amd.com        // We need to save and replay the packet in two cases:
41111284Sandreas.hansson@arm.com        // 1. We're awaiting a writable copy (Modified or Exclusive),
41211284Sandreas.hansson@arm.com        //    so this MSHR is the orgering point, and we need to respond
41311284Sandreas.hansson@arm.com        //    after we receive data.
4147667Ssteve.reinhardt@amd.com        // 2. It's an invalidation (e.g., UpgradeReq), and we need
4157667Ssteve.reinhardt@amd.com        //    to forward the snoop up the hierarchy after the current
4167667Ssteve.reinhardt@amd.com        //    transaction completes.
41710571Sandreas.hansson@arm.com
41811271Sandreas.hansson@arm.com        // Start by determining if we will eventually respond or not,
41911271Sandreas.hansson@arm.com        // matching the conditions checked in Cache::handleSnoop
42012350Snikos.nikoleris@arm.com        bool will_respond = isPendingModified() && pkt->needsResponse() &&
42112350Snikos.nikoleris@arm.com                      !pkt->isClean();
42211271Sandreas.hansson@arm.com
42311271Sandreas.hansson@arm.com        // The packet we are snooping may be deleted by the time we
42411271Sandreas.hansson@arm.com        // actually process the target, and we consequently need to
42511271Sandreas.hansson@arm.com        // save a copy here. Clear flags and also allocate new data as
42611271Sandreas.hansson@arm.com        // the original packet data storage may have been deleted by
42711271Sandreas.hansson@arm.com        // the time we get to process this packet. In the cases where
42811271Sandreas.hansson@arm.com        // we are not responding after handling the snoop we also need
42911271Sandreas.hansson@arm.com        // to create a copy of the request to be on the safe side. In
43011271Sandreas.hansson@arm.com        // the latter case the cache is responsible for deleting both
43111271Sandreas.hansson@arm.com        // the packet and the request as part of handling the deferred
43211271Sandreas.hansson@arm.com        // snoop.
43311271Sandreas.hansson@arm.com        PacketPtr cp_pkt = will_respond ? new Packet(pkt, true, true) :
43412749Sgiacomo.travaglini@arm.com            new Packet(std::make_shared<Request>(*pkt->req), pkt->cmd,
43512749Sgiacomo.travaglini@arm.com                       blkSize, pkt->id);
4364670SN/A
43711490Sandreas.hansson@arm.com        if (will_respond) {
43811284Sandreas.hansson@arm.com            // we are the ordering point, and will consequently
43911284Sandreas.hansson@arm.com            // respond, and depending on whether the packet
44011284Sandreas.hansson@arm.com            // needsWritable or not we either pass a Shared line or a
44111284Sandreas.hansson@arm.com            // Modified line
44211284Sandreas.hansson@arm.com            pkt->setCacheResponding();
44311284Sandreas.hansson@arm.com
44411284Sandreas.hansson@arm.com            // inform the cache hierarchy that this cache had the line
44511284Sandreas.hansson@arm.com            // in the Modified state, even if the response is passed
44611284Sandreas.hansson@arm.com            // as Shared (and thus non-writable)
44711284Sandreas.hansson@arm.com            pkt->setResponderHadWritable();
44811284Sandreas.hansson@arm.com
44910821Sandreas.hansson@arm.com            // in the case of an uncacheable request there is no need
45011284Sandreas.hansson@arm.com            // to set the responderHadWritable flag, but since the
45111284Sandreas.hansson@arm.com            // recipient does not care there is no harm in doing so
4524670SN/A        }
45310826Sstephan.diestelhorst@ARM.com        targets.add(cp_pkt, curTick(), _order, Target::FromSnoop,
45411741Snikos.nikoleris@arm.com                    downstreamPending && targets.needsWritable, false);
4554670SN/A
45612350Snikos.nikoleris@arm.com        if (pkt->needsWritable() || pkt->isInvalidate()) {
4574670SN/A            // This transaction will take away our pending copy
4587667Ssteve.reinhardt@amd.com            postInvalidate = true;
4594670SN/A        }
46012350Snikos.nikoleris@arm.com
46112501Snikos.nikoleris@arm.com        if (isPendingModified() && pkt->isClean()) {
46212350Snikos.nikoleris@arm.com            pkt->setSatisfied();
46312350Snikos.nikoleris@arm.com        }
4647667Ssteve.reinhardt@amd.com    }
4657667Ssteve.reinhardt@amd.com
46611284Sandreas.hansson@arm.com    if (!pkt->needsWritable() && !pkt->req->isUncacheable()) {
4677667Ssteve.reinhardt@amd.com        // This transaction will get a read-shared copy, downgrading
46811284Sandreas.hansson@arm.com        // our copy if we had a writable one
4697667Ssteve.reinhardt@amd.com        postDowngrade = true;
47011284Sandreas.hansson@arm.com        // make sure that any downstream cache does not respond with a
47111284Sandreas.hansson@arm.com        // writable (and dirty) copy even if it has one, unless it was
47211284Sandreas.hansson@arm.com        // explicitly asked for one
47311284Sandreas.hansson@arm.com        pkt->setHasSharers();
4744667SN/A    }
4754902SN/A
4764902SN/A    return true;
4774665SN/A}
4784665SN/A
47911742Snikos.nikoleris@arm.comMSHR::TargetList
48011742Snikos.nikoleris@arm.comMSHR::extractServiceableTargets(PacketPtr pkt)
48111742Snikos.nikoleris@arm.com{
48211742Snikos.nikoleris@arm.com    TargetList ready_targets;
48311742Snikos.nikoleris@arm.com    // If the downstream MSHR got an invalidation request then we only
48411742Snikos.nikoleris@arm.com    // service the first of the FromCPU targets and any other
48511742Snikos.nikoleris@arm.com    // non-FromCPU target. This way the remaining FromCPU targets
48611742Snikos.nikoleris@arm.com    // issue a new request and get a fresh copy of the block and we
48711742Snikos.nikoleris@arm.com    // avoid memory consistency violations.
48811742Snikos.nikoleris@arm.com    if (pkt->cmd == MemCmd::ReadRespWithInvalidate) {
48911742Snikos.nikoleris@arm.com        auto it = targets.begin();
49011866Ssascha.bischoff@arm.com        assert((it->source == Target::FromCPU) ||
49111866Ssascha.bischoff@arm.com               (it->source == Target::FromPrefetcher));
49211742Snikos.nikoleris@arm.com        ready_targets.push_back(*it);
49311742Snikos.nikoleris@arm.com        it = targets.erase(it);
49411742Snikos.nikoleris@arm.com        while (it != targets.end()) {
49511742Snikos.nikoleris@arm.com            if (it->source == Target::FromCPU) {
49611742Snikos.nikoleris@arm.com                it++;
49711742Snikos.nikoleris@arm.com            } else {
49811742Snikos.nikoleris@arm.com                assert(it->source == Target::FromSnoop);
49911742Snikos.nikoleris@arm.com                ready_targets.push_back(*it);
50011742Snikos.nikoleris@arm.com                it = targets.erase(it);
50111742Snikos.nikoleris@arm.com            }
50211742Snikos.nikoleris@arm.com        }
50311742Snikos.nikoleris@arm.com        ready_targets.populateFlags();
50411742Snikos.nikoleris@arm.com    } else {
50511742Snikos.nikoleris@arm.com        std::swap(ready_targets, targets);
50611742Snikos.nikoleris@arm.com    }
50711742Snikos.nikoleris@arm.com    targets.populateFlags();
50811742Snikos.nikoleris@arm.com
50911742Snikos.nikoleris@arm.com    return ready_targets;
51011742Snikos.nikoleris@arm.com}
5114665SN/A
5124665SN/Abool
5134665SN/AMSHR::promoteDeferredTargets()
5144665SN/A{
51512350Snikos.nikoleris@arm.com    if (targets.empty() && deferredTargets.empty()) {
51612350Snikos.nikoleris@arm.com        // nothing to promote
51712350Snikos.nikoleris@arm.com        return false;
5184665SN/A    }
5194665SN/A
52012350Snikos.nikoleris@arm.com    // the deferred targets can be generally promoted unless they
52112350Snikos.nikoleris@arm.com    // contain a cache maintenance request
5224903SN/A
52312350Snikos.nikoleris@arm.com    // find the first target that is a cache maintenance request
52412350Snikos.nikoleris@arm.com    auto it = std::find_if(deferredTargets.begin(), deferredTargets.end(),
52512350Snikos.nikoleris@arm.com                           [](MSHR::Target &t) {
52612350Snikos.nikoleris@arm.com                               return t.pkt->req->isCacheMaintenance();
52712350Snikos.nikoleris@arm.com                           });
52812350Snikos.nikoleris@arm.com    if (it == deferredTargets.begin()) {
52912350Snikos.nikoleris@arm.com        // if the first deferred target is a cache maintenance packet
53012350Snikos.nikoleris@arm.com        // then we can promote provided the targets list is empty and
53112350Snikos.nikoleris@arm.com        // we can service it on its own
53212350Snikos.nikoleris@arm.com        if (targets.empty()) {
53312350Snikos.nikoleris@arm.com            targets.splice(targets.end(), deferredTargets, it);
53412350Snikos.nikoleris@arm.com        }
53512350Snikos.nikoleris@arm.com    } else {
53612350Snikos.nikoleris@arm.com        // if a cache maintenance operation exists, we promote all the
53712350Snikos.nikoleris@arm.com        // deferred targets that precede it, or all deferred targets
53812350Snikos.nikoleris@arm.com        // otherwise
53912350Snikos.nikoleris@arm.com        targets.splice(targets.end(), deferredTargets,
54012350Snikos.nikoleris@arm.com                       deferredTargets.begin(), it);
54112350Snikos.nikoleris@arm.com    }
54212350Snikos.nikoleris@arm.com
54312350Snikos.nikoleris@arm.com    deferredTargets.populateFlags();
54412350Snikos.nikoleris@arm.com    targets.populateFlags();
5459725Sandreas.hansson@arm.com    order = targets.front().order;
5469725Sandreas.hansson@arm.com    readyTime = std::max(curTick(), targets.front().readyTime);
5474665SN/A
5484665SN/A    return true;
5492810SN/A}
5502810SN/A
5512810SN/A
5522810SN/Avoid
55311284Sandreas.hansson@arm.comMSHR::promoteWritable()
5544668SN/A{
55511284Sandreas.hansson@arm.com    if (deferredTargets.needsWritable &&
55611177Sandreas.hansson@arm.com        !(hasPostInvalidate() || hasPostDowngrade())) {
55711284Sandreas.hansson@arm.com        // We got a writable response, but we have deferred targets
55811284Sandreas.hansson@arm.com        // which are waiting to request a writable copy (not because
5595270SN/A        // of a pending invalidate).  This can happen if the original
56011284Sandreas.hansson@arm.com        // request was for a read-only block, but we got a writable
56111284Sandreas.hansson@arm.com        // response anyway. Since we got the writable copy there's no
56211284Sandreas.hansson@arm.com        // need to defer the targets, so move them up to the regular
56311284Sandreas.hansson@arm.com        // target list.
56411284Sandreas.hansson@arm.com        assert(!targets.needsWritable);
56511284Sandreas.hansson@arm.com        targets.needsWritable = true;
5665318SN/A        // if any of the deferred targets were upper-level cache
5675318SN/A        // requests marked downstreamPending, need to clear that
5685318SN/A        assert(!downstreamPending);  // not pending here anymore
5699725Sandreas.hansson@arm.com        deferredTargets.clearDownstreamPending();
5705270SN/A        // this clears out deferredTargets too
5719725Sandreas.hansson@arm.com        targets.splice(targets.end(), deferredTargets);
5729725Sandreas.hansson@arm.com        deferredTargets.resetFlags();
5735270SN/A    }
5744668SN/A}
5754668SN/A
5764668SN/A
5775314SN/Abool
5785314SN/AMSHR::checkFunctional(PacketPtr pkt)
5795314SN/A{
5805314SN/A    // For printing, we treat the MSHR as a whole as single entity.
5815314SN/A    // For other requests, we iterate over the individual targets
5825314SN/A    // since that's where the actual data lies.
5835314SN/A    if (pkt->isPrint()) {
58411484Snikos.nikoleris@arm.com        pkt->checkFunctional(this, blkAddr, isSecure, blkSize, nullptr);
5855314SN/A        return false;
5865314SN/A    } else {
5879725Sandreas.hansson@arm.com        return (targets.checkFunctional(pkt) ||
5889725Sandreas.hansson@arm.com                deferredTargets.checkFunctional(pkt));
5895314SN/A    }
5905314SN/A}
5915314SN/A
59211375Sandreas.hansson@arm.combool
59312724Snikos.nikoleris@arm.comMSHR::sendPacket(BaseCache &cache)
59411375Sandreas.hansson@arm.com{
59511375Sandreas.hansson@arm.com    return cache.sendMSHRQueuePacket(this);
59611375Sandreas.hansson@arm.com}
5975314SN/A
5984668SN/Avoid
5995314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
6002810SN/A{
60112715Snikos.nikoleris@arm.com    ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s %s\n",
60210764Sandreas.hansson@arm.com             prefix, blkAddr, blkAddr + blkSize - 1,
60310028SGiacomo.Gabrielli@arm.com             isSecure ? "s" : "ns",
6045730SSteve.Reinhardt@amd.com             isForward ? "Forward" : "",
60511741Snikos.nikoleris@arm.com             allocOnFill() ? "AllocOnFill" : "",
60611284Sandreas.hansson@arm.com             needsWritable() ? "Wrtbl" : "",
6075314SN/A             _isUncacheable ? "Unc" : "",
6085314SN/A             inService ? "InSvc" : "",
6095314SN/A             downstreamPending ? "DwnPend" : "",
61011610Snikos.nikoleris@arm.com             postInvalidate ? "PostInv" : "",
61112715Snikos.nikoleris@arm.com             postDowngrade ? "PostDowngr" : "",
61212715Snikos.nikoleris@arm.com             hasFromCache() ? "HasFromCache" : "");
6132810SN/A
61411610Snikos.nikoleris@arm.com    if (!targets.empty()) {
61511610Snikos.nikoleris@arm.com        ccprintf(os, "%s  Targets:\n", prefix);
61611610Snikos.nikoleris@arm.com        targets.print(os, verbosity, prefix + "    ");
61711610Snikos.nikoleris@arm.com    }
6189725Sandreas.hansson@arm.com    if (!deferredTargets.empty()) {
6195314SN/A        ccprintf(os, "%s  Deferred Targets:\n", prefix);
6209725Sandreas.hansson@arm.com        deferredTargets.print(os, verbosity, prefix + "      ");
6212810SN/A    }
6222810SN/A}
6232810SN/A
6249663Suri.wiener@arm.comstd::string
6259663Suri.wiener@arm.comMSHR::print() const
6269663Suri.wiener@arm.com{
62712637Sodanrc@yahoo.com.br    std::ostringstream str;
6289663Suri.wiener@arm.com    print(str);
6299663Suri.wiener@arm.com    return str.str();
6309663Suri.wiener@arm.com}
631