mshr.cc revision 11866
12810SN/A/*
211866Ssascha.bischoff@arm.com * Copyright (c) 2012-2013, 2015-2017 ARM Limited
39663Suri.wiener@arm.com * All rights reserved.
49663Suri.wiener@arm.com *
59663Suri.wiener@arm.com * The license below extends only to copyright in the software and shall
69663Suri.wiener@arm.com * not be construed as granting a license to any other intellectual
79663Suri.wiener@arm.com * property including but not limited to intellectual property relating
89663Suri.wiener@arm.com * to a hardware implementation of the functionality of the software
99663Suri.wiener@arm.com * licensed hereunder.  You may use the software subject to the license
109663Suri.wiener@arm.com * terms below provided that you ensure that this notice is replicated
119663Suri.wiener@arm.com * unmodified and in its entirety in all distributions of the software,
129663Suri.wiener@arm.com * modified or unmodified, in source code or in binary form.
139663Suri.wiener@arm.com *
142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
157636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
162810SN/A * All rights reserved.
172810SN/A *
182810SN/A * Redistribution and use in source and binary forms, with or without
192810SN/A * modification, are permitted provided that the following conditions are
202810SN/A * met: redistributions of source code must retain the above copyright
212810SN/A * notice, this list of conditions and the following disclaimer;
222810SN/A * redistributions in binary form must reproduce the above copyright
232810SN/A * notice, this list of conditions and the following disclaimer in the
242810SN/A * documentation and/or other materials provided with the distribution;
252810SN/A * neither the name of the copyright holders nor the names of its
262810SN/A * contributors may be used to endorse or promote products derived from
272810SN/A * this software without specific prior written permission.
282810SN/A *
292810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402810SN/A *
412810SN/A * Authors: Erik Hallnor
422810SN/A *          Dave Greene
432810SN/A */
442810SN/A
452810SN/A/**
462810SN/A * @file
472810SN/A * Miss Status and Handling Register (MSHR) definitions.
482810SN/A */
492810SN/A
5011486Snikos.nikoleris@arm.com#include "mem/cache/mshr.hh"
5111486Snikos.nikoleris@arm.com
526216Snate@binkert.org#include <algorithm>
536216Snate@binkert.org#include <cassert>
542810SN/A#include <string>
552810SN/A#include <vector>
562810SN/A
576216Snate@binkert.org#include "base/misc.hh"
586216Snate@binkert.org#include "base/types.hh"
598232Snate@binkert.org#include "debug/Cache.hh"
606216Snate@binkert.org#include "mem/cache/cache.hh"
616216Snate@binkert.org#include "sim/core.hh"
622810SN/A
632810SN/Ausing namespace std;
642810SN/A
6511375Sandreas.hansson@arm.comMSHR::MSHR() : downstreamPending(false),
6611284Sandreas.hansson@arm.com               pendingModified(false),
6710503SCurtis.Dunham@arm.com               postInvalidate(false), postDowngrade(false),
6811741Snikos.nikoleris@arm.com               isForward(false)
692810SN/A{
702810SN/A}
712810SN/A
724903SN/AMSHR::TargetList::TargetList()
7311741Snikos.nikoleris@arm.com    : needsWritable(false), hasUpgrade(false), allocOnFill(false)
744903SN/A{}
754903SN/A
764903SN/A
7711740Snikos.nikoleris@arm.comvoid
7811741Snikos.nikoleris@arm.comMSHR::TargetList::updateFlags(PacketPtr pkt, Target::Source source,
7911741Snikos.nikoleris@arm.com                              bool alloc_on_fill)
804903SN/A{
815875Ssteve.reinhardt@amd.com    if (source != Target::FromSnoop) {
8211284Sandreas.hansson@arm.com        if (pkt->needsWritable()) {
8311284Sandreas.hansson@arm.com            needsWritable = true;
844903SN/A        }
854903SN/A
867669Ssteve.reinhardt@amd.com        // StoreCondReq is effectively an upgrade if it's in an MSHR
877669Ssteve.reinhardt@amd.com        // since it would have been failed already if we didn't have a
887669Ssteve.reinhardt@amd.com        // read-only copy
897669Ssteve.reinhardt@amd.com        if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
904903SN/A            hasUpgrade = true;
914903SN/A        }
9211741Snikos.nikoleris@arm.com
9311741Snikos.nikoleris@arm.com        // potentially re-evaluate whether we should allocate on a fill or
9411741Snikos.nikoleris@arm.com        // not
9511741Snikos.nikoleris@arm.com        allocOnFill = allocOnFill || alloc_on_fill;
965318SN/A    }
9711740Snikos.nikoleris@arm.com}
984908SN/A
9911740Snikos.nikoleris@arm.comvoid
10011740Snikos.nikoleris@arm.comMSHR::TargetList::populateFlags()
10111740Snikos.nikoleris@arm.com{
10211740Snikos.nikoleris@arm.com    resetFlags();
10311740Snikos.nikoleris@arm.com    for (auto& t: *this) {
10411741Snikos.nikoleris@arm.com        updateFlags(t.pkt, t.source, t.allocOnFill);
10511740Snikos.nikoleris@arm.com    }
10611740Snikos.nikoleris@arm.com}
10711740Snikos.nikoleris@arm.com
10811740Snikos.nikoleris@arm.cominline void
10911740Snikos.nikoleris@arm.comMSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
11011741Snikos.nikoleris@arm.com                      Counter order, Target::Source source, bool markPending,
11111741Snikos.nikoleris@arm.com                      bool alloc_on_fill)
11211740Snikos.nikoleris@arm.com{
11311741Snikos.nikoleris@arm.com    updateFlags(pkt, source, alloc_on_fill);
1145318SN/A    if (markPending) {
1159543Ssascha.bischoff@arm.com        // Iterate over the SenderState stack and see if we find
1169543Ssascha.bischoff@arm.com        // an MSHR entry. If we do, set the downstreamPending
1179543Ssascha.bischoff@arm.com        // flag. Otherwise, do nothing.
1189543Ssascha.bischoff@arm.com        MSHR *mshr = pkt->findNextSenderState<MSHR>();
11911484Snikos.nikoleris@arm.com        if (mshr != nullptr) {
1204908SN/A            assert(!mshr->downstreamPending);
1214908SN/A            mshr->downstreamPending = true;
12211083Sandreas.hansson@arm.com        } else {
12311083Sandreas.hansson@arm.com            // No need to clear downstreamPending later
12411083Sandreas.hansson@arm.com            markPending = false;
1254908SN/A        }
1264903SN/A    }
1274903SN/A
12811741Snikos.nikoleris@arm.com    emplace_back(pkt, readyTime, order, source, markPending, alloc_on_fill);
1294903SN/A}
1304903SN/A
1314903SN/A
1327667Ssteve.reinhardt@amd.comstatic void
1337667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt)
1347667Ssteve.reinhardt@amd.com{
13511286Sandreas.hansson@arm.com    // remember if the current packet has data allocated
13611286Sandreas.hansson@arm.com    bool has_data = pkt->hasData() || pkt->hasRespData();
13711286Sandreas.hansson@arm.com
1387667Ssteve.reinhardt@amd.com    if (pkt->cmd == MemCmd::UpgradeReq) {
1397667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::ReadExReq;
1407667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
1417667Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
1427667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::SCUpgradeFailReq;
1437667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
1447669Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::StoreCondReq) {
1457669Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::StoreCondFailReq;
1467669Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
1477667Ssteve.reinhardt@amd.com    }
14811286Sandreas.hansson@arm.com
14911286Sandreas.hansson@arm.com    if (!has_data) {
15011286Sandreas.hansson@arm.com        // there is no sensible way of setting the data field if the
15111286Sandreas.hansson@arm.com        // new command actually would carry data
15211286Sandreas.hansson@arm.com        assert(!pkt->hasData());
15311286Sandreas.hansson@arm.com
15411286Sandreas.hansson@arm.com        if (pkt->hasRespData()) {
15511286Sandreas.hansson@arm.com            // we went from a packet that had no data (neither request,
15611286Sandreas.hansson@arm.com            // nor response), to one that does, and therefore we need to
15711286Sandreas.hansson@arm.com            // actually allocate space for the data payload
15811286Sandreas.hansson@arm.com            pkt->allocate();
15911286Sandreas.hansson@arm.com        }
16011286Sandreas.hansson@arm.com    }
1617667Ssteve.reinhardt@amd.com}
1627667Ssteve.reinhardt@amd.com
1637667Ssteve.reinhardt@amd.com
1644903SN/Avoid
1654903SN/AMSHR::TargetList::replaceUpgrades()
1664903SN/A{
1674903SN/A    if (!hasUpgrade)
1684903SN/A        return;
1694903SN/A
17010766Sandreas.hansson@arm.com    for (auto& t : *this) {
17110766Sandreas.hansson@arm.com        replaceUpgrade(t.pkt);
1724903SN/A    }
1734903SN/A
1744903SN/A    hasUpgrade = false;
1754903SN/A}
1764903SN/A
1774903SN/A
1782810SN/Avoid
1794908SN/AMSHR::TargetList::clearDownstreamPending()
1804908SN/A{
18110766Sandreas.hansson@arm.com    for (auto& t : *this) {
18210766Sandreas.hansson@arm.com        if (t.markedPending) {
1839543Ssascha.bischoff@arm.com            // Iterate over the SenderState stack and see if we find
1849543Ssascha.bischoff@arm.com            // an MSHR entry. If we find one, clear the
1859543Ssascha.bischoff@arm.com            // downstreamPending flag by calling
1869543Ssascha.bischoff@arm.com            // clearDownstreamPending(). This recursively clears the
1879543Ssascha.bischoff@arm.com            // downstreamPending flag in all caches this packet has
1889543Ssascha.bischoff@arm.com            // passed through.
18910766Sandreas.hansson@arm.com            MSHR *mshr = t.pkt->findNextSenderState<MSHR>();
19011484Snikos.nikoleris@arm.com            if (mshr != nullptr) {
1915318SN/A                mshr->clearDownstreamPending();
1925318SN/A            }
19311742Snikos.nikoleris@arm.com            t.markedPending = false;
1944908SN/A        }
1954908SN/A    }
1964908SN/A}
1974908SN/A
1984908SN/A
1994920SN/Abool
2004920SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt)
2014920SN/A{
20210766Sandreas.hansson@arm.com    for (auto& t : *this) {
20310766Sandreas.hansson@arm.com        if (pkt->checkFunctional(t.pkt)) {
2044920SN/A            return true;
2054920SN/A        }
2064920SN/A    }
2074920SN/A
2084920SN/A    return false;
2094920SN/A}
2104920SN/A
2114920SN/A
2124908SN/Avoid
21310766Sandreas.hansson@arm.comMSHR::TargetList::print(std::ostream &os, int verbosity,
21410766Sandreas.hansson@arm.com                        const std::string &prefix) const
2155314SN/A{
21610766Sandreas.hansson@arm.com    for (auto& t : *this) {
2175875Ssteve.reinhardt@amd.com        const char *s;
21810766Sandreas.hansson@arm.com        switch (t.source) {
2198988SAli.Saidi@ARM.com          case Target::FromCPU:
2208988SAli.Saidi@ARM.com            s = "FromCPU";
2218988SAli.Saidi@ARM.com            break;
2228988SAli.Saidi@ARM.com          case Target::FromSnoop:
2238988SAli.Saidi@ARM.com            s = "FromSnoop";
2248988SAli.Saidi@ARM.com            break;
2258988SAli.Saidi@ARM.com          case Target::FromPrefetcher:
2268988SAli.Saidi@ARM.com            s = "FromPrefetcher";
2278988SAli.Saidi@ARM.com            break;
2288988SAli.Saidi@ARM.com          default:
2298988SAli.Saidi@ARM.com            s = "";
2308988SAli.Saidi@ARM.com            break;
2315875Ssteve.reinhardt@amd.com        }
2325875Ssteve.reinhardt@amd.com        ccprintf(os, "%s%s: ", prefix, s);
23310766Sandreas.hansson@arm.com        t.pkt->print(os, verbosity, "");
23411744Snikos.nikoleris@arm.com        ccprintf(os, "\n");
2355314SN/A    }
2365314SN/A}
2375314SN/A
2385314SN/A
2395314SN/Avoid
24010764Sandreas.hansson@arm.comMSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
24111197Sandreas.hansson@arm.com               Tick when_ready, Counter _order, bool alloc_on_fill)
2422810SN/A{
24310764Sandreas.hansson@arm.com    blkAddr = blk_addr;
24410764Sandreas.hansson@arm.com    blkSize = blk_size;
24510028SGiacomo.Gabrielli@arm.com    isSecure = target->isSecure();
24610764Sandreas.hansson@arm.com    readyTime = when_ready;
2474666SN/A    order = _order;
2484626SN/A    assert(target);
2495730SSteve.Reinhardt@amd.com    isForward = false;
2504626SN/A    _isUncacheable = target->req->isUncacheable();
2514626SN/A    inService = false;
2524908SN/A    downstreamPending = false;
2539725Sandreas.hansson@arm.com    assert(targets.isReset());
2544626SN/A    // Don't know of a case where we would allocate a new MSHR for a
2555875Ssteve.reinhardt@amd.com    // snoop (mem-side request), so set source according to request here
2565875Ssteve.reinhardt@amd.com    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
2575875Ssteve.reinhardt@amd.com        Target::FromPrefetcher : Target::FromCPU;
25811741Snikos.nikoleris@arm.com    targets.add(target, when_ready, _order, source, true, alloc_on_fill);
2599725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
2602810SN/A}
2612810SN/A
2624908SN/A
2635318SN/Avoid
2645318SN/AMSHR::clearDownstreamPending()
2655318SN/A{
2665318SN/A    assert(downstreamPending);
2675318SN/A    downstreamPending = false;
2685318SN/A    // recursively clear flag on any MSHRs we will be forwarding
2695318SN/A    // responses to
2709725Sandreas.hansson@arm.com    targets.clearDownstreamPending();
2715318SN/A}
2725318SN/A
27311375Sandreas.hansson@arm.comvoid
27411284Sandreas.hansson@arm.comMSHR::markInService(bool pending_modified_resp)
2754908SN/A{
2764908SN/A    assert(!inService);
27710424Sandreas.hansson@arm.com
2784908SN/A    inService = true;
27911284Sandreas.hansson@arm.com    pendingModified = targets.needsWritable || pending_modified_resp;
2807667Ssteve.reinhardt@amd.com    postInvalidate = postDowngrade = false;
2817667Ssteve.reinhardt@amd.com
2824908SN/A    if (!downstreamPending) {
2834908SN/A        // let upstream caches know that the request has made it to a
2844908SN/A        // level where it's going to get a response
2859725Sandreas.hansson@arm.com        targets.clearDownstreamPending();
2864908SN/A    }
2874908SN/A}
2884908SN/A
2894908SN/A
2902810SN/Avoid
2912810SN/AMSHR::deallocate()
2922810SN/A{
2939725Sandreas.hansson@arm.com    assert(targets.empty());
2949725Sandreas.hansson@arm.com    targets.resetFlags();
2959725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
2962810SN/A    inService = false;
2972810SN/A}
2982810SN/A
2992810SN/A/*
3002810SN/A * Adds a target to an MSHR
3012810SN/A */
3022810SN/Avoid
30311197Sandreas.hansson@arm.comMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order,
30411197Sandreas.hansson@arm.com                     bool alloc_on_fill)
3052810SN/A{
30610768Sandreas.hansson@arm.com    // assume we'd never issue a prefetch when we've got an
30710768Sandreas.hansson@arm.com    // outstanding miss
30810768Sandreas.hansson@arm.com    assert(pkt->cmd != MemCmd::HardPFReq);
30910768Sandreas.hansson@arm.com
31010768Sandreas.hansson@arm.com    // uncacheable accesses always allocate a new MSHR, and cacheable
31110768Sandreas.hansson@arm.com    // accesses ignore any uncacheable MSHRs, thus we should never
31210768Sandreas.hansson@arm.com    // have targets addded if originally allocated uncacheable
31310768Sandreas.hansson@arm.com    assert(!_isUncacheable);
31410768Sandreas.hansson@arm.com
3154903SN/A    // if there's a request already in service for this MSHR, we will
3164903SN/A    // have to defer the new target until after the response if any of
3174903SN/A    // the following are true:
3184903SN/A    // - there are other targets already deferred
3194903SN/A    // - there's a pending invalidate to be applied after the response
3204903SN/A    //   comes back (but before this target is processed)
32111284Sandreas.hansson@arm.com    // - this target requires a writable block and either we're not
32211284Sandreas.hansson@arm.com    //   getting a writable block back or we have already snooped
32311284Sandreas.hansson@arm.com    //   another read request that will downgrade our writable block
32411284Sandreas.hansson@arm.com    //   to non-writable (Shared or Owned)
3254903SN/A    if (inService &&
3269725Sandreas.hansson@arm.com        (!deferredTargets.empty() || hasPostInvalidate() ||
32711284Sandreas.hansson@arm.com         (pkt->needsWritable() &&
32811284Sandreas.hansson@arm.com          (!isPendingModified() || hasPostDowngrade() || isForward)))) {
3294903SN/A        // need to put on deferred list
3307667Ssteve.reinhardt@amd.com        if (hasPostInvalidate())
3317667Ssteve.reinhardt@amd.com            replaceUpgrade(pkt);
33211741Snikos.nikoleris@arm.com        deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true,
33311741Snikos.nikoleris@arm.com                            alloc_on_fill);
3344665SN/A    } else {
3355318SN/A        // No request outstanding, or still OK to append to
3365318SN/A        // outstanding request: append to regular target list.  Only
3375318SN/A        // mark pending if current request hasn't been issued yet
3385318SN/A        // (isn't in service).
33911741Snikos.nikoleris@arm.com        targets.add(pkt, whenReady, _order, Target::FromCPU, !inService,
34011741Snikos.nikoleris@arm.com                    alloc_on_fill);
3412810SN/A    }
3424665SN/A}
3434665SN/A
3444902SN/Abool
3454902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order)
3464665SN/A{
34711744Snikos.nikoleris@arm.com    DPRINTF(Cache, "%s for %s\n", __func__, pkt->print());
34811279Sandreas.hansson@arm.com
34911284Sandreas.hansson@arm.com    // when we snoop packets the needsWritable and isInvalidate flags
35011279Sandreas.hansson@arm.com    // should always be the same, however, this assumes that we never
35111279Sandreas.hansson@arm.com    // snoop writes as they are currently not marked as invalidations
35211284Sandreas.hansson@arm.com    panic_if(pkt->needsWritable() != pkt->isInvalidate(),
35311744Snikos.nikoleris@arm.com             "%s got snoop %s where needsWritable, "
35411863Snikos.nikoleris@arm.com             "does not match isInvalidate", name(), pkt->print());
35511279Sandreas.hansson@arm.com
3564910SN/A    if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
3574903SN/A        // Request has not been issued yet, or it's been issued
3584903SN/A        // locally but is buffered unissued at some downstream cache
3594903SN/A        // which is forwarding us this snoop.  Either way, the packet
3604903SN/A        // we're snooping logically precedes this MSHR's request, so
3614903SN/A        // the snoop has no impact on the MSHR, but must be processed
3624903SN/A        // in the standard way by the cache.  The only exception is
3634903SN/A        // that if we're an L2+ cache buffering an UpgradeReq from a
3644903SN/A        // higher-level cache, and the snoop is invalidating, then our
3654903SN/A        // buffered upgrades must be converted to read exclusives,
3664903SN/A        // since the upper-level cache no longer has a valid copy.
3674903SN/A        // That is, even though the upper-level cache got out on its
3684903SN/A        // local bus first, some other invalidating transaction
3694903SN/A        // reached the global bus before the upgrade did.
37011284Sandreas.hansson@arm.com        if (pkt->needsWritable()) {
3719725Sandreas.hansson@arm.com            targets.replaceUpgrades();
3729725Sandreas.hansson@arm.com            deferredTargets.replaceUpgrades();
3734903SN/A        }
3744903SN/A
3754902SN/A        return false;
3764902SN/A    }
3774665SN/A
3784903SN/A    // From here on down, the request issued by this MSHR logically
3794903SN/A    // precedes the request we're snooping.
38011284Sandreas.hansson@arm.com    if (pkt->needsWritable()) {
3814903SN/A        // snooped request still precedes the re-request we'll have to
3824903SN/A        // issue for deferred targets, if any...
3839725Sandreas.hansson@arm.com        deferredTargets.replaceUpgrades();
3844903SN/A    }
3854903SN/A
3867667Ssteve.reinhardt@amd.com    if (hasPostInvalidate()) {
3874665SN/A        // a prior snoop has already appended an invalidation, so
3884903SN/A        // logically we don't have the block anymore; no need for
3894903SN/A        // further snooping.
3904902SN/A        return true;
3914665SN/A    }
3924665SN/A
39311284Sandreas.hansson@arm.com    if (isPendingModified() || pkt->isInvalidate()) {
3947667Ssteve.reinhardt@amd.com        // We need to save and replay the packet in two cases:
39511284Sandreas.hansson@arm.com        // 1. We're awaiting a writable copy (Modified or Exclusive),
39611284Sandreas.hansson@arm.com        //    so this MSHR is the orgering point, and we need to respond
39711284Sandreas.hansson@arm.com        //    after we receive data.
3987667Ssteve.reinhardt@amd.com        // 2. It's an invalidation (e.g., UpgradeReq), and we need
3997667Ssteve.reinhardt@amd.com        //    to forward the snoop up the hierarchy after the current
4007667Ssteve.reinhardt@amd.com        //    transaction completes.
40110571Sandreas.hansson@arm.com
40211271Sandreas.hansson@arm.com        // Start by determining if we will eventually respond or not,
40311271Sandreas.hansson@arm.com        // matching the conditions checked in Cache::handleSnoop
40411751Snikos.nikoleris@arm.com        bool will_respond = isPendingModified() && pkt->needsResponse();
40511271Sandreas.hansson@arm.com
40611271Sandreas.hansson@arm.com        // The packet we are snooping may be deleted by the time we
40711271Sandreas.hansson@arm.com        // actually process the target, and we consequently need to
40811271Sandreas.hansson@arm.com        // save a copy here. Clear flags and also allocate new data as
40911271Sandreas.hansson@arm.com        // the original packet data storage may have been deleted by
41011271Sandreas.hansson@arm.com        // the time we get to process this packet. In the cases where
41111271Sandreas.hansson@arm.com        // we are not responding after handling the snoop we also need
41211271Sandreas.hansson@arm.com        // to create a copy of the request to be on the safe side. In
41311271Sandreas.hansson@arm.com        // the latter case the cache is responsible for deleting both
41411271Sandreas.hansson@arm.com        // the packet and the request as part of handling the deferred
41511271Sandreas.hansson@arm.com        // snoop.
41611271Sandreas.hansson@arm.com        PacketPtr cp_pkt = will_respond ? new Packet(pkt, true, true) :
41711858Sandreas.hansson@arm.com            new Packet(new Request(*pkt->req), pkt->cmd, blkSize);
4184670SN/A
41911490Sandreas.hansson@arm.com        if (will_respond) {
42011284Sandreas.hansson@arm.com            // we are the ordering point, and will consequently
42111284Sandreas.hansson@arm.com            // respond, and depending on whether the packet
42211284Sandreas.hansson@arm.com            // needsWritable or not we either pass a Shared line or a
42311284Sandreas.hansson@arm.com            // Modified line
42411284Sandreas.hansson@arm.com            pkt->setCacheResponding();
42511284Sandreas.hansson@arm.com
42611284Sandreas.hansson@arm.com            // inform the cache hierarchy that this cache had the line
42711284Sandreas.hansson@arm.com            // in the Modified state, even if the response is passed
42811284Sandreas.hansson@arm.com            // as Shared (and thus non-writable)
42911284Sandreas.hansson@arm.com            pkt->setResponderHadWritable();
43011284Sandreas.hansson@arm.com
43110821Sandreas.hansson@arm.com            // in the case of an uncacheable request there is no need
43211284Sandreas.hansson@arm.com            // to set the responderHadWritable flag, but since the
43311284Sandreas.hansson@arm.com            // recipient does not care there is no harm in doing so
4344670SN/A        }
43510826Sstephan.diestelhorst@ARM.com        targets.add(cp_pkt, curTick(), _order, Target::FromSnoop,
43611741Snikos.nikoleris@arm.com                    downstreamPending && targets.needsWritable, false);
4374670SN/A
43811284Sandreas.hansson@arm.com        if (pkt->needsWritable()) {
4394670SN/A            // This transaction will take away our pending copy
4407667Ssteve.reinhardt@amd.com            postInvalidate = true;
4414670SN/A        }
4427667Ssteve.reinhardt@amd.com    }
4437667Ssteve.reinhardt@amd.com
44411284Sandreas.hansson@arm.com    if (!pkt->needsWritable() && !pkt->req->isUncacheable()) {
4457667Ssteve.reinhardt@amd.com        // This transaction will get a read-shared copy, downgrading
44611284Sandreas.hansson@arm.com        // our copy if we had a writable one
4477667Ssteve.reinhardt@amd.com        postDowngrade = true;
44811284Sandreas.hansson@arm.com        // make sure that any downstream cache does not respond with a
44911284Sandreas.hansson@arm.com        // writable (and dirty) copy even if it has one, unless it was
45011284Sandreas.hansson@arm.com        // explicitly asked for one
45111284Sandreas.hansson@arm.com        pkt->setHasSharers();
4524667SN/A    }
4534902SN/A
4544902SN/A    return true;
4554665SN/A}
4564665SN/A
45711742Snikos.nikoleris@arm.comMSHR::TargetList
45811742Snikos.nikoleris@arm.comMSHR::extractServiceableTargets(PacketPtr pkt)
45911742Snikos.nikoleris@arm.com{
46011742Snikos.nikoleris@arm.com    TargetList ready_targets;
46111742Snikos.nikoleris@arm.com    // If the downstream MSHR got an invalidation request then we only
46211742Snikos.nikoleris@arm.com    // service the first of the FromCPU targets and any other
46311742Snikos.nikoleris@arm.com    // non-FromCPU target. This way the remaining FromCPU targets
46411742Snikos.nikoleris@arm.com    // issue a new request and get a fresh copy of the block and we
46511742Snikos.nikoleris@arm.com    // avoid memory consistency violations.
46611742Snikos.nikoleris@arm.com    if (pkt->cmd == MemCmd::ReadRespWithInvalidate) {
46711742Snikos.nikoleris@arm.com        auto it = targets.begin();
46811866Ssascha.bischoff@arm.com        assert((it->source == Target::FromCPU) ||
46911866Ssascha.bischoff@arm.com               (it->source == Target::FromPrefetcher));
47011742Snikos.nikoleris@arm.com        ready_targets.push_back(*it);
47111742Snikos.nikoleris@arm.com        it = targets.erase(it);
47211742Snikos.nikoleris@arm.com        while (it != targets.end()) {
47311742Snikos.nikoleris@arm.com            if (it->source == Target::FromCPU) {
47411742Snikos.nikoleris@arm.com                it++;
47511742Snikos.nikoleris@arm.com            } else {
47611742Snikos.nikoleris@arm.com                assert(it->source == Target::FromSnoop);
47711742Snikos.nikoleris@arm.com                ready_targets.push_back(*it);
47811742Snikos.nikoleris@arm.com                it = targets.erase(it);
47911742Snikos.nikoleris@arm.com            }
48011742Snikos.nikoleris@arm.com        }
48111742Snikos.nikoleris@arm.com        ready_targets.populateFlags();
48211742Snikos.nikoleris@arm.com    } else {
48311742Snikos.nikoleris@arm.com        std::swap(ready_targets, targets);
48411742Snikos.nikoleris@arm.com    }
48511742Snikos.nikoleris@arm.com    targets.populateFlags();
48611742Snikos.nikoleris@arm.com
48711742Snikos.nikoleris@arm.com    return ready_targets;
48811742Snikos.nikoleris@arm.com}
4894665SN/A
4904665SN/Abool
4914665SN/AMSHR::promoteDeferredTargets()
4924665SN/A{
49311742Snikos.nikoleris@arm.com    if (targets.empty())  {
49411742Snikos.nikoleris@arm.com        if (deferredTargets.empty()) {
49511742Snikos.nikoleris@arm.com            return false;
49611742Snikos.nikoleris@arm.com        }
49711742Snikos.nikoleris@arm.com
49811742Snikos.nikoleris@arm.com        std::swap(targets, deferredTargets);
49911742Snikos.nikoleris@arm.com    } else {
50011742Snikos.nikoleris@arm.com        // If the targets list is not empty then we have one targets
50111742Snikos.nikoleris@arm.com        // from the deferredTargets list to the targets list. A new
50211742Snikos.nikoleris@arm.com        // request will then service the targets list.
50311742Snikos.nikoleris@arm.com        targets.splice(targets.end(), deferredTargets);
50411742Snikos.nikoleris@arm.com        targets.populateFlags();
5054665SN/A    }
5064665SN/A
5074903SN/A    // clear deferredTargets flags
5089725Sandreas.hansson@arm.com    deferredTargets.resetFlags();
5094903SN/A
5109725Sandreas.hansson@arm.com    order = targets.front().order;
5119725Sandreas.hansson@arm.com    readyTime = std::max(curTick(), targets.front().readyTime);
5124665SN/A
5134665SN/A    return true;
5142810SN/A}
5152810SN/A
5162810SN/A
5172810SN/Avoid
51811284Sandreas.hansson@arm.comMSHR::promoteWritable()
5194668SN/A{
52011284Sandreas.hansson@arm.com    if (deferredTargets.needsWritable &&
52111177Sandreas.hansson@arm.com        !(hasPostInvalidate() || hasPostDowngrade())) {
52211284Sandreas.hansson@arm.com        // We got a writable response, but we have deferred targets
52311284Sandreas.hansson@arm.com        // which are waiting to request a writable copy (not because
5245270SN/A        // of a pending invalidate).  This can happen if the original
52511284Sandreas.hansson@arm.com        // request was for a read-only block, but we got a writable
52611284Sandreas.hansson@arm.com        // response anyway. Since we got the writable copy there's no
52711284Sandreas.hansson@arm.com        // need to defer the targets, so move them up to the regular
52811284Sandreas.hansson@arm.com        // target list.
52911284Sandreas.hansson@arm.com        assert(!targets.needsWritable);
53011284Sandreas.hansson@arm.com        targets.needsWritable = true;
5315318SN/A        // if any of the deferred targets were upper-level cache
5325318SN/A        // requests marked downstreamPending, need to clear that
5335318SN/A        assert(!downstreamPending);  // not pending here anymore
5349725Sandreas.hansson@arm.com        deferredTargets.clearDownstreamPending();
5355270SN/A        // this clears out deferredTargets too
5369725Sandreas.hansson@arm.com        targets.splice(targets.end(), deferredTargets);
5379725Sandreas.hansson@arm.com        deferredTargets.resetFlags();
5385270SN/A    }
5394668SN/A}
5404668SN/A
5414668SN/A
5425314SN/Abool
5435314SN/AMSHR::checkFunctional(PacketPtr pkt)
5445314SN/A{
5455314SN/A    // For printing, we treat the MSHR as a whole as single entity.
5465314SN/A    // For other requests, we iterate over the individual targets
5475314SN/A    // since that's where the actual data lies.
5485314SN/A    if (pkt->isPrint()) {
54911484Snikos.nikoleris@arm.com        pkt->checkFunctional(this, blkAddr, isSecure, blkSize, nullptr);
5505314SN/A        return false;
5515314SN/A    } else {
5529725Sandreas.hansson@arm.com        return (targets.checkFunctional(pkt) ||
5539725Sandreas.hansson@arm.com                deferredTargets.checkFunctional(pkt));
5545314SN/A    }
5555314SN/A}
5565314SN/A
55711375Sandreas.hansson@arm.combool
55811375Sandreas.hansson@arm.comMSHR::sendPacket(Cache &cache)
55911375Sandreas.hansson@arm.com{
56011375Sandreas.hansson@arm.com    return cache.sendMSHRQueuePacket(this);
56111375Sandreas.hansson@arm.com}
5625314SN/A
5634668SN/Avoid
5645314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
5652810SN/A{
56610725Sandreas.hansson@arm.com    ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
56710764Sandreas.hansson@arm.com             prefix, blkAddr, blkAddr + blkSize - 1,
56810028SGiacomo.Gabrielli@arm.com             isSecure ? "s" : "ns",
5695730SSteve.Reinhardt@amd.com             isForward ? "Forward" : "",
57011741Snikos.nikoleris@arm.com             allocOnFill() ? "AllocOnFill" : "",
57111284Sandreas.hansson@arm.com             needsWritable() ? "Wrtbl" : "",
5725314SN/A             _isUncacheable ? "Unc" : "",
5735314SN/A             inService ? "InSvc" : "",
5745314SN/A             downstreamPending ? "DwnPend" : "",
57511610Snikos.nikoleris@arm.com             postInvalidate ? "PostInv" : "",
57611610Snikos.nikoleris@arm.com             postDowngrade ? "PostDowngr" : "");
5772810SN/A
57811610Snikos.nikoleris@arm.com    if (!targets.empty()) {
57911610Snikos.nikoleris@arm.com        ccprintf(os, "%s  Targets:\n", prefix);
58011610Snikos.nikoleris@arm.com        targets.print(os, verbosity, prefix + "    ");
58111610Snikos.nikoleris@arm.com    }
5829725Sandreas.hansson@arm.com    if (!deferredTargets.empty()) {
5835314SN/A        ccprintf(os, "%s  Deferred Targets:\n", prefix);
5849725Sandreas.hansson@arm.com        deferredTargets.print(os, verbosity, prefix + "      ");
5852810SN/A    }
5862810SN/A}
5872810SN/A
5889663Suri.wiener@arm.comstd::string
5899663Suri.wiener@arm.comMSHR::print() const
5909663Suri.wiener@arm.com{
5919663Suri.wiener@arm.com    ostringstream str;
5929663Suri.wiener@arm.com    print(str);
5939663Suri.wiener@arm.com    return str.str();
5949663Suri.wiener@arm.com}
595