mshr.cc revision 11741
12810SN/A/* 211375Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015-2016 ARM Limited 39663Suri.wiener@arm.com * All rights reserved. 49663Suri.wiener@arm.com * 59663Suri.wiener@arm.com * The license below extends only to copyright in the software and shall 69663Suri.wiener@arm.com * not be construed as granting a license to any other intellectual 79663Suri.wiener@arm.com * property including but not limited to intellectual property relating 89663Suri.wiener@arm.com * to a hardware implementation of the functionality of the software 99663Suri.wiener@arm.com * licensed hereunder. You may use the software subject to the license 109663Suri.wiener@arm.com * terms below provided that you ensure that this notice is replicated 119663Suri.wiener@arm.com * unmodified and in its entirety in all distributions of the software, 129663Suri.wiener@arm.com * modified or unmodified, in source code or in binary form. 139663Suri.wiener@arm.com * 142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc. 162810SN/A * All rights reserved. 172810SN/A * 182810SN/A * Redistribution and use in source and binary forms, with or without 192810SN/A * modification, are permitted provided that the following conditions are 202810SN/A * met: redistributions of source code must retain the above copyright 212810SN/A * notice, this list of conditions and the following disclaimer; 222810SN/A * redistributions in binary form must reproduce the above copyright 232810SN/A * notice, this list of conditions and the following disclaimer in the 242810SN/A * documentation and/or other materials provided with the distribution; 252810SN/A * neither the name of the copyright holders nor the names of its 262810SN/A * contributors may be used to endorse or promote products derived from 272810SN/A * this software without specific prior written permission. 282810SN/A * 292810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810SN/A * 412810SN/A * Authors: Erik Hallnor 422810SN/A * Dave Greene 432810SN/A */ 442810SN/A 452810SN/A/** 462810SN/A * @file 472810SN/A * Miss Status and Handling Register (MSHR) definitions. 482810SN/A */ 492810SN/A 5011486Snikos.nikoleris@arm.com#include "mem/cache/mshr.hh" 5111486Snikos.nikoleris@arm.com 526216Snate@binkert.org#include <algorithm> 536216Snate@binkert.org#include <cassert> 542810SN/A#include <string> 552810SN/A#include <vector> 562810SN/A 576216Snate@binkert.org#include "base/misc.hh" 586216Snate@binkert.org#include "base/types.hh" 598232Snate@binkert.org#include "debug/Cache.hh" 606216Snate@binkert.org#include "mem/cache/cache.hh" 616216Snate@binkert.org#include "sim/core.hh" 622810SN/A 632810SN/Ausing namespace std; 642810SN/A 6511375Sandreas.hansson@arm.comMSHR::MSHR() : downstreamPending(false), 6611284Sandreas.hansson@arm.com pendingModified(false), 6710503SCurtis.Dunham@arm.com postInvalidate(false), postDowngrade(false), 6811741Snikos.nikoleris@arm.com isForward(false) 692810SN/A{ 702810SN/A} 712810SN/A 724903SN/AMSHR::TargetList::TargetList() 7311741Snikos.nikoleris@arm.com : needsWritable(false), hasUpgrade(false), allocOnFill(false) 744903SN/A{} 754903SN/A 764903SN/A 7711740Snikos.nikoleris@arm.comvoid 7811741Snikos.nikoleris@arm.comMSHR::TargetList::updateFlags(PacketPtr pkt, Target::Source source, 7911741Snikos.nikoleris@arm.com bool alloc_on_fill) 804903SN/A{ 815875Ssteve.reinhardt@amd.com if (source != Target::FromSnoop) { 8211284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 8311284Sandreas.hansson@arm.com needsWritable = true; 844903SN/A } 854903SN/A 867669Ssteve.reinhardt@amd.com // StoreCondReq is effectively an upgrade if it's in an MSHR 877669Ssteve.reinhardt@amd.com // since it would have been failed already if we didn't have a 887669Ssteve.reinhardt@amd.com // read-only copy 897669Ssteve.reinhardt@amd.com if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) { 904903SN/A hasUpgrade = true; 914903SN/A } 9211741Snikos.nikoleris@arm.com 9311741Snikos.nikoleris@arm.com // potentially re-evaluate whether we should allocate on a fill or 9411741Snikos.nikoleris@arm.com // not 9511741Snikos.nikoleris@arm.com allocOnFill = allocOnFill || alloc_on_fill; 965318SN/A } 9711740Snikos.nikoleris@arm.com} 984908SN/A 9911740Snikos.nikoleris@arm.comvoid 10011740Snikos.nikoleris@arm.comMSHR::TargetList::populateFlags() 10111740Snikos.nikoleris@arm.com{ 10211740Snikos.nikoleris@arm.com resetFlags(); 10311740Snikos.nikoleris@arm.com for (auto& t: *this) { 10411741Snikos.nikoleris@arm.com updateFlags(t.pkt, t.source, t.allocOnFill); 10511740Snikos.nikoleris@arm.com } 10611740Snikos.nikoleris@arm.com} 10711740Snikos.nikoleris@arm.com 10811740Snikos.nikoleris@arm.cominline void 10911740Snikos.nikoleris@arm.comMSHR::TargetList::add(PacketPtr pkt, Tick readyTime, 11011741Snikos.nikoleris@arm.com Counter order, Target::Source source, bool markPending, 11111741Snikos.nikoleris@arm.com bool alloc_on_fill) 11211740Snikos.nikoleris@arm.com{ 11311741Snikos.nikoleris@arm.com updateFlags(pkt, source, alloc_on_fill); 1145318SN/A if (markPending) { 1159543Ssascha.bischoff@arm.com // Iterate over the SenderState stack and see if we find 1169543Ssascha.bischoff@arm.com // an MSHR entry. If we do, set the downstreamPending 1179543Ssascha.bischoff@arm.com // flag. Otherwise, do nothing. 1189543Ssascha.bischoff@arm.com MSHR *mshr = pkt->findNextSenderState<MSHR>(); 11911484Snikos.nikoleris@arm.com if (mshr != nullptr) { 1204908SN/A assert(!mshr->downstreamPending); 1214908SN/A mshr->downstreamPending = true; 12211083Sandreas.hansson@arm.com } else { 12311083Sandreas.hansson@arm.com // No need to clear downstreamPending later 12411083Sandreas.hansson@arm.com markPending = false; 1254908SN/A } 1264903SN/A } 1274903SN/A 12811741Snikos.nikoleris@arm.com emplace_back(pkt, readyTime, order, source, markPending, alloc_on_fill); 1294903SN/A} 1304903SN/A 1314903SN/A 1327667Ssteve.reinhardt@amd.comstatic void 1337667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt) 1347667Ssteve.reinhardt@amd.com{ 13511286Sandreas.hansson@arm.com // remember if the current packet has data allocated 13611286Sandreas.hansson@arm.com bool has_data = pkt->hasData() || pkt->hasRespData(); 13711286Sandreas.hansson@arm.com 1387667Ssteve.reinhardt@amd.com if (pkt->cmd == MemCmd::UpgradeReq) { 1397667Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::ReadExReq; 1407667Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n"); 1417667Ssteve.reinhardt@amd.com } else if (pkt->cmd == MemCmd::SCUpgradeReq) { 1427667Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::SCUpgradeFailReq; 1437667Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n"); 1447669Ssteve.reinhardt@amd.com } else if (pkt->cmd == MemCmd::StoreCondReq) { 1457669Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::StoreCondFailReq; 1467669Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n"); 1477667Ssteve.reinhardt@amd.com } 14811286Sandreas.hansson@arm.com 14911286Sandreas.hansson@arm.com if (!has_data) { 15011286Sandreas.hansson@arm.com // there is no sensible way of setting the data field if the 15111286Sandreas.hansson@arm.com // new command actually would carry data 15211286Sandreas.hansson@arm.com assert(!pkt->hasData()); 15311286Sandreas.hansson@arm.com 15411286Sandreas.hansson@arm.com if (pkt->hasRespData()) { 15511286Sandreas.hansson@arm.com // we went from a packet that had no data (neither request, 15611286Sandreas.hansson@arm.com // nor response), to one that does, and therefore we need to 15711286Sandreas.hansson@arm.com // actually allocate space for the data payload 15811286Sandreas.hansson@arm.com pkt->allocate(); 15911286Sandreas.hansson@arm.com } 16011286Sandreas.hansson@arm.com } 1617667Ssteve.reinhardt@amd.com} 1627667Ssteve.reinhardt@amd.com 1637667Ssteve.reinhardt@amd.com 1644903SN/Avoid 1654903SN/AMSHR::TargetList::replaceUpgrades() 1664903SN/A{ 1674903SN/A if (!hasUpgrade) 1684903SN/A return; 1694903SN/A 17010766Sandreas.hansson@arm.com for (auto& t : *this) { 17110766Sandreas.hansson@arm.com replaceUpgrade(t.pkt); 1724903SN/A } 1734903SN/A 1744903SN/A hasUpgrade = false; 1754903SN/A} 1764903SN/A 1774903SN/A 1782810SN/Avoid 1794908SN/AMSHR::TargetList::clearDownstreamPending() 1804908SN/A{ 18110766Sandreas.hansson@arm.com for (auto& t : *this) { 18210766Sandreas.hansson@arm.com if (t.markedPending) { 1839543Ssascha.bischoff@arm.com // Iterate over the SenderState stack and see if we find 1849543Ssascha.bischoff@arm.com // an MSHR entry. If we find one, clear the 1859543Ssascha.bischoff@arm.com // downstreamPending flag by calling 1869543Ssascha.bischoff@arm.com // clearDownstreamPending(). This recursively clears the 1879543Ssascha.bischoff@arm.com // downstreamPending flag in all caches this packet has 1889543Ssascha.bischoff@arm.com // passed through. 18910766Sandreas.hansson@arm.com MSHR *mshr = t.pkt->findNextSenderState<MSHR>(); 19011484Snikos.nikoleris@arm.com if (mshr != nullptr) { 1915318SN/A mshr->clearDownstreamPending(); 1925318SN/A } 1934908SN/A } 1944908SN/A } 1954908SN/A} 1964908SN/A 1974908SN/A 1984920SN/Abool 1994920SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt) 2004920SN/A{ 20110766Sandreas.hansson@arm.com for (auto& t : *this) { 20210766Sandreas.hansson@arm.com if (pkt->checkFunctional(t.pkt)) { 2034920SN/A return true; 2044920SN/A } 2054920SN/A } 2064920SN/A 2074920SN/A return false; 2084920SN/A} 2094920SN/A 2104920SN/A 2114908SN/Avoid 21210766Sandreas.hansson@arm.comMSHR::TargetList::print(std::ostream &os, int verbosity, 21310766Sandreas.hansson@arm.com const std::string &prefix) const 2145314SN/A{ 21510766Sandreas.hansson@arm.com for (auto& t : *this) { 2165875Ssteve.reinhardt@amd.com const char *s; 21710766Sandreas.hansson@arm.com switch (t.source) { 2188988SAli.Saidi@ARM.com case Target::FromCPU: 2198988SAli.Saidi@ARM.com s = "FromCPU"; 2208988SAli.Saidi@ARM.com break; 2218988SAli.Saidi@ARM.com case Target::FromSnoop: 2228988SAli.Saidi@ARM.com s = "FromSnoop"; 2238988SAli.Saidi@ARM.com break; 2248988SAli.Saidi@ARM.com case Target::FromPrefetcher: 2258988SAli.Saidi@ARM.com s = "FromPrefetcher"; 2268988SAli.Saidi@ARM.com break; 2278988SAli.Saidi@ARM.com default: 2288988SAli.Saidi@ARM.com s = ""; 2298988SAli.Saidi@ARM.com break; 2305875Ssteve.reinhardt@amd.com } 2315875Ssteve.reinhardt@amd.com ccprintf(os, "%s%s: ", prefix, s); 23210766Sandreas.hansson@arm.com t.pkt->print(os, verbosity, ""); 2335314SN/A } 2345314SN/A} 2355314SN/A 2365314SN/A 2375314SN/Avoid 23810764Sandreas.hansson@arm.comMSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target, 23911197Sandreas.hansson@arm.com Tick when_ready, Counter _order, bool alloc_on_fill) 2402810SN/A{ 24110764Sandreas.hansson@arm.com blkAddr = blk_addr; 24210764Sandreas.hansson@arm.com blkSize = blk_size; 24310028SGiacomo.Gabrielli@arm.com isSecure = target->isSecure(); 24410764Sandreas.hansson@arm.com readyTime = when_ready; 2454666SN/A order = _order; 2464626SN/A assert(target); 2475730SSteve.Reinhardt@amd.com isForward = false; 2484626SN/A _isUncacheable = target->req->isUncacheable(); 2494626SN/A inService = false; 2504908SN/A downstreamPending = false; 2519725Sandreas.hansson@arm.com assert(targets.isReset()); 2524626SN/A // Don't know of a case where we would allocate a new MSHR for a 2535875Ssteve.reinhardt@amd.com // snoop (mem-side request), so set source according to request here 2545875Ssteve.reinhardt@amd.com Target::Source source = (target->cmd == MemCmd::HardPFReq) ? 2555875Ssteve.reinhardt@amd.com Target::FromPrefetcher : Target::FromCPU; 25611741Snikos.nikoleris@arm.com targets.add(target, when_ready, _order, source, true, alloc_on_fill); 2579725Sandreas.hansson@arm.com assert(deferredTargets.isReset()); 2582810SN/A} 2592810SN/A 2604908SN/A 2615318SN/Avoid 2625318SN/AMSHR::clearDownstreamPending() 2635318SN/A{ 2645318SN/A assert(downstreamPending); 2655318SN/A downstreamPending = false; 2665318SN/A // recursively clear flag on any MSHRs we will be forwarding 2675318SN/A // responses to 2689725Sandreas.hansson@arm.com targets.clearDownstreamPending(); 2695318SN/A} 2705318SN/A 27111375Sandreas.hansson@arm.comvoid 27211284Sandreas.hansson@arm.comMSHR::markInService(bool pending_modified_resp) 2734908SN/A{ 2744908SN/A assert(!inService); 27510424Sandreas.hansson@arm.com 2764908SN/A inService = true; 27711284Sandreas.hansson@arm.com pendingModified = targets.needsWritable || pending_modified_resp; 2787667Ssteve.reinhardt@amd.com postInvalidate = postDowngrade = false; 2797667Ssteve.reinhardt@amd.com 2804908SN/A if (!downstreamPending) { 2814908SN/A // let upstream caches know that the request has made it to a 2824908SN/A // level where it's going to get a response 2839725Sandreas.hansson@arm.com targets.clearDownstreamPending(); 2844908SN/A } 2854908SN/A} 2864908SN/A 2874908SN/A 2882810SN/Avoid 2892810SN/AMSHR::deallocate() 2902810SN/A{ 2919725Sandreas.hansson@arm.com assert(targets.empty()); 2929725Sandreas.hansson@arm.com targets.resetFlags(); 2939725Sandreas.hansson@arm.com assert(deferredTargets.isReset()); 2942810SN/A inService = false; 2952810SN/A} 2962810SN/A 2972810SN/A/* 2982810SN/A * Adds a target to an MSHR 2992810SN/A */ 3002810SN/Avoid 30111197Sandreas.hansson@arm.comMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order, 30211197Sandreas.hansson@arm.com bool alloc_on_fill) 3032810SN/A{ 30410768Sandreas.hansson@arm.com // assume we'd never issue a prefetch when we've got an 30510768Sandreas.hansson@arm.com // outstanding miss 30610768Sandreas.hansson@arm.com assert(pkt->cmd != MemCmd::HardPFReq); 30710768Sandreas.hansson@arm.com 30810768Sandreas.hansson@arm.com // uncacheable accesses always allocate a new MSHR, and cacheable 30910768Sandreas.hansson@arm.com // accesses ignore any uncacheable MSHRs, thus we should never 31010768Sandreas.hansson@arm.com // have targets addded if originally allocated uncacheable 31110768Sandreas.hansson@arm.com assert(!_isUncacheable); 31210768Sandreas.hansson@arm.com 3134903SN/A // if there's a request already in service for this MSHR, we will 3144903SN/A // have to defer the new target until after the response if any of 3154903SN/A // the following are true: 3164903SN/A // - there are other targets already deferred 3174903SN/A // - there's a pending invalidate to be applied after the response 3184903SN/A // comes back (but before this target is processed) 31911284Sandreas.hansson@arm.com // - this target requires a writable block and either we're not 32011284Sandreas.hansson@arm.com // getting a writable block back or we have already snooped 32111284Sandreas.hansson@arm.com // another read request that will downgrade our writable block 32211284Sandreas.hansson@arm.com // to non-writable (Shared or Owned) 3234903SN/A if (inService && 3249725Sandreas.hansson@arm.com (!deferredTargets.empty() || hasPostInvalidate() || 32511284Sandreas.hansson@arm.com (pkt->needsWritable() && 32611284Sandreas.hansson@arm.com (!isPendingModified() || hasPostDowngrade() || isForward)))) { 3274903SN/A // need to put on deferred list 3287667Ssteve.reinhardt@amd.com if (hasPostInvalidate()) 3297667Ssteve.reinhardt@amd.com replaceUpgrade(pkt); 33011741Snikos.nikoleris@arm.com deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true, 33111741Snikos.nikoleris@arm.com alloc_on_fill); 3324665SN/A } else { 3335318SN/A // No request outstanding, or still OK to append to 3345318SN/A // outstanding request: append to regular target list. Only 3355318SN/A // mark pending if current request hasn't been issued yet 3365318SN/A // (isn't in service). 33711741Snikos.nikoleris@arm.com targets.add(pkt, whenReady, _order, Target::FromCPU, !inService, 33811741Snikos.nikoleris@arm.com alloc_on_fill); 3392810SN/A } 3404665SN/A} 3414665SN/A 3424902SN/Abool 3434902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order) 3444665SN/A{ 34510725Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 3469663Suri.wiener@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 34711279Sandreas.hansson@arm.com 34811284Sandreas.hansson@arm.com // when we snoop packets the needsWritable and isInvalidate flags 34911279Sandreas.hansson@arm.com // should always be the same, however, this assumes that we never 35011279Sandreas.hansson@arm.com // snoop writes as they are currently not marked as invalidations 35111284Sandreas.hansson@arm.com panic_if(pkt->needsWritable() != pkt->isInvalidate(), 35211284Sandreas.hansson@arm.com "%s got snoop %s to addr %#llx where needsWritable, " 35311279Sandreas.hansson@arm.com "does not match isInvalidate", name(), pkt->cmdString(), 35411279Sandreas.hansson@arm.com pkt->getAddr()); 35511279Sandreas.hansson@arm.com 3564910SN/A if (!inService || (pkt->isExpressSnoop() && downstreamPending)) { 3574903SN/A // Request has not been issued yet, or it's been issued 3584903SN/A // locally but is buffered unissued at some downstream cache 3594903SN/A // which is forwarding us this snoop. Either way, the packet 3604903SN/A // we're snooping logically precedes this MSHR's request, so 3614903SN/A // the snoop has no impact on the MSHR, but must be processed 3624903SN/A // in the standard way by the cache. The only exception is 3634903SN/A // that if we're an L2+ cache buffering an UpgradeReq from a 3644903SN/A // higher-level cache, and the snoop is invalidating, then our 3654903SN/A // buffered upgrades must be converted to read exclusives, 3664903SN/A // since the upper-level cache no longer has a valid copy. 3674903SN/A // That is, even though the upper-level cache got out on its 3684903SN/A // local bus first, some other invalidating transaction 3694903SN/A // reached the global bus before the upgrade did. 37011284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 3719725Sandreas.hansson@arm.com targets.replaceUpgrades(); 3729725Sandreas.hansson@arm.com deferredTargets.replaceUpgrades(); 3734903SN/A } 3744903SN/A 3754902SN/A return false; 3764902SN/A } 3774665SN/A 3784903SN/A // From here on down, the request issued by this MSHR logically 3794903SN/A // precedes the request we're snooping. 38011284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 3814903SN/A // snooped request still precedes the re-request we'll have to 3824903SN/A // issue for deferred targets, if any... 3839725Sandreas.hansson@arm.com deferredTargets.replaceUpgrades(); 3844903SN/A } 3854903SN/A 3867667Ssteve.reinhardt@amd.com if (hasPostInvalidate()) { 3874665SN/A // a prior snoop has already appended an invalidation, so 3884903SN/A // logically we don't have the block anymore; no need for 3894903SN/A // further snooping. 3904902SN/A return true; 3914665SN/A } 3924665SN/A 39311284Sandreas.hansson@arm.com if (isPendingModified() || pkt->isInvalidate()) { 3947667Ssteve.reinhardt@amd.com // We need to save and replay the packet in two cases: 39511284Sandreas.hansson@arm.com // 1. We're awaiting a writable copy (Modified or Exclusive), 39611284Sandreas.hansson@arm.com // so this MSHR is the orgering point, and we need to respond 39711284Sandreas.hansson@arm.com // after we receive data. 3987667Ssteve.reinhardt@amd.com // 2. It's an invalidation (e.g., UpgradeReq), and we need 3997667Ssteve.reinhardt@amd.com // to forward the snoop up the hierarchy after the current 4007667Ssteve.reinhardt@amd.com // transaction completes. 40110571Sandreas.hansson@arm.com 40211271Sandreas.hansson@arm.com // Start by determining if we will eventually respond or not, 40311271Sandreas.hansson@arm.com // matching the conditions checked in Cache::handleSnoop 40411284Sandreas.hansson@arm.com bool will_respond = isPendingModified() && pkt->needsResponse() && 40511271Sandreas.hansson@arm.com pkt->cmd != MemCmd::InvalidateReq; 40611271Sandreas.hansson@arm.com 40711271Sandreas.hansson@arm.com // The packet we are snooping may be deleted by the time we 40811271Sandreas.hansson@arm.com // actually process the target, and we consequently need to 40911271Sandreas.hansson@arm.com // save a copy here. Clear flags and also allocate new data as 41011271Sandreas.hansson@arm.com // the original packet data storage may have been deleted by 41111271Sandreas.hansson@arm.com // the time we get to process this packet. In the cases where 41211271Sandreas.hansson@arm.com // we are not responding after handling the snoop we also need 41311271Sandreas.hansson@arm.com // to create a copy of the request to be on the safe side. In 41411271Sandreas.hansson@arm.com // the latter case the cache is responsible for deleting both 41511271Sandreas.hansson@arm.com // the packet and the request as part of handling the deferred 41611271Sandreas.hansson@arm.com // snoop. 41711271Sandreas.hansson@arm.com PacketPtr cp_pkt = will_respond ? new Packet(pkt, true, true) : 41811271Sandreas.hansson@arm.com new Packet(new Request(*pkt->req), pkt->cmd); 4194670SN/A 42011490Sandreas.hansson@arm.com if (will_respond) { 42111284Sandreas.hansson@arm.com // we are the ordering point, and will consequently 42211284Sandreas.hansson@arm.com // respond, and depending on whether the packet 42311284Sandreas.hansson@arm.com // needsWritable or not we either pass a Shared line or a 42411284Sandreas.hansson@arm.com // Modified line 42511284Sandreas.hansson@arm.com pkt->setCacheResponding(); 42611284Sandreas.hansson@arm.com 42711284Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 42811284Sandreas.hansson@arm.com // in the Modified state, even if the response is passed 42911284Sandreas.hansson@arm.com // as Shared (and thus non-writable) 43011284Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 43111284Sandreas.hansson@arm.com 43210821Sandreas.hansson@arm.com // in the case of an uncacheable request there is no need 43311284Sandreas.hansson@arm.com // to set the responderHadWritable flag, but since the 43411284Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 4354670SN/A } 43610826Sstephan.diestelhorst@ARM.com targets.add(cp_pkt, curTick(), _order, Target::FromSnoop, 43711741Snikos.nikoleris@arm.com downstreamPending && targets.needsWritable, false); 4384670SN/A 43911284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 4404670SN/A // This transaction will take away our pending copy 4417667Ssteve.reinhardt@amd.com postInvalidate = true; 4424670SN/A } 4437667Ssteve.reinhardt@amd.com } 4447667Ssteve.reinhardt@amd.com 44511284Sandreas.hansson@arm.com if (!pkt->needsWritable() && !pkt->req->isUncacheable()) { 4467667Ssteve.reinhardt@amd.com // This transaction will get a read-shared copy, downgrading 44711284Sandreas.hansson@arm.com // our copy if we had a writable one 4487667Ssteve.reinhardt@amd.com postDowngrade = true; 44911284Sandreas.hansson@arm.com // make sure that any downstream cache does not respond with a 45011284Sandreas.hansson@arm.com // writable (and dirty) copy even if it has one, unless it was 45111284Sandreas.hansson@arm.com // explicitly asked for one 45211284Sandreas.hansson@arm.com pkt->setHasSharers(); 4534667SN/A } 4544902SN/A 4554902SN/A return true; 4564665SN/A} 4574665SN/A 4584665SN/A 4594665SN/Abool 4604665SN/AMSHR::promoteDeferredTargets() 4614665SN/A{ 4629725Sandreas.hansson@arm.com assert(targets.empty()); 4639725Sandreas.hansson@arm.com if (deferredTargets.empty()) { 4644665SN/A return false; 4654665SN/A } 4664665SN/A 4674903SN/A // swap targets & deferredTargets lists 4689725Sandreas.hansson@arm.com std::swap(targets, deferredTargets); 4694903SN/A 4704903SN/A // clear deferredTargets flags 4719725Sandreas.hansson@arm.com deferredTargets.resetFlags(); 4724903SN/A 4739725Sandreas.hansson@arm.com order = targets.front().order; 4749725Sandreas.hansson@arm.com readyTime = std::max(curTick(), targets.front().readyTime); 4754665SN/A 4764665SN/A return true; 4772810SN/A} 4782810SN/A 4792810SN/A 4802810SN/Avoid 48111284Sandreas.hansson@arm.comMSHR::promoteWritable() 4824668SN/A{ 48311284Sandreas.hansson@arm.com if (deferredTargets.needsWritable && 48411177Sandreas.hansson@arm.com !(hasPostInvalidate() || hasPostDowngrade())) { 48511284Sandreas.hansson@arm.com // We got a writable response, but we have deferred targets 48611284Sandreas.hansson@arm.com // which are waiting to request a writable copy (not because 4875270SN/A // of a pending invalidate). This can happen if the original 48811284Sandreas.hansson@arm.com // request was for a read-only block, but we got a writable 48911284Sandreas.hansson@arm.com // response anyway. Since we got the writable copy there's no 49011284Sandreas.hansson@arm.com // need to defer the targets, so move them up to the regular 49111284Sandreas.hansson@arm.com // target list. 49211284Sandreas.hansson@arm.com assert(!targets.needsWritable); 49311284Sandreas.hansson@arm.com targets.needsWritable = true; 4945318SN/A // if any of the deferred targets were upper-level cache 4955318SN/A // requests marked downstreamPending, need to clear that 4965318SN/A assert(!downstreamPending); // not pending here anymore 4979725Sandreas.hansson@arm.com deferredTargets.clearDownstreamPending(); 4985270SN/A // this clears out deferredTargets too 4999725Sandreas.hansson@arm.com targets.splice(targets.end(), deferredTargets); 5009725Sandreas.hansson@arm.com deferredTargets.resetFlags(); 5015270SN/A } 5024668SN/A} 5034668SN/A 5044668SN/A 5055314SN/Abool 5065314SN/AMSHR::checkFunctional(PacketPtr pkt) 5075314SN/A{ 5085314SN/A // For printing, we treat the MSHR as a whole as single entity. 5095314SN/A // For other requests, we iterate over the individual targets 5105314SN/A // since that's where the actual data lies. 5115314SN/A if (pkt->isPrint()) { 51211484Snikos.nikoleris@arm.com pkt->checkFunctional(this, blkAddr, isSecure, blkSize, nullptr); 5135314SN/A return false; 5145314SN/A } else { 5159725Sandreas.hansson@arm.com return (targets.checkFunctional(pkt) || 5169725Sandreas.hansson@arm.com deferredTargets.checkFunctional(pkt)); 5175314SN/A } 5185314SN/A} 5195314SN/A 52011375Sandreas.hansson@arm.combool 52111375Sandreas.hansson@arm.comMSHR::sendPacket(Cache &cache) 52211375Sandreas.hansson@arm.com{ 52311375Sandreas.hansson@arm.com return cache.sendMSHRQueuePacket(this); 52411375Sandreas.hansson@arm.com} 5255314SN/A 5264668SN/Avoid 5275314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const 5282810SN/A{ 52910725Sandreas.hansson@arm.com ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n", 53010764Sandreas.hansson@arm.com prefix, blkAddr, blkAddr + blkSize - 1, 53110028SGiacomo.Gabrielli@arm.com isSecure ? "s" : "ns", 5325730SSteve.Reinhardt@amd.com isForward ? "Forward" : "", 53311741Snikos.nikoleris@arm.com allocOnFill() ? "AllocOnFill" : "", 53411284Sandreas.hansson@arm.com needsWritable() ? "Wrtbl" : "", 5355314SN/A _isUncacheable ? "Unc" : "", 5365314SN/A inService ? "InSvc" : "", 5375314SN/A downstreamPending ? "DwnPend" : "", 53811610Snikos.nikoleris@arm.com postInvalidate ? "PostInv" : "", 53911610Snikos.nikoleris@arm.com postDowngrade ? "PostDowngr" : ""); 5402810SN/A 54111610Snikos.nikoleris@arm.com if (!targets.empty()) { 54211610Snikos.nikoleris@arm.com ccprintf(os, "%s Targets:\n", prefix); 54311610Snikos.nikoleris@arm.com targets.print(os, verbosity, prefix + " "); 54411610Snikos.nikoleris@arm.com } 5459725Sandreas.hansson@arm.com if (!deferredTargets.empty()) { 5465314SN/A ccprintf(os, "%s Deferred Targets:\n", prefix); 5479725Sandreas.hansson@arm.com deferredTargets.print(os, verbosity, prefix + " "); 5482810SN/A } 5492810SN/A} 5502810SN/A 5519663Suri.wiener@arm.comstd::string 5529663Suri.wiener@arm.comMSHR::print() const 5539663Suri.wiener@arm.com{ 5549663Suri.wiener@arm.com ostringstream str; 5559663Suri.wiener@arm.com print(str); 5569663Suri.wiener@arm.com return str.str(); 5579663Suri.wiener@arm.com} 558