mshr.cc revision 11740
12810SN/A/*
211375Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015-2016 ARM Limited
39663Suri.wiener@arm.com * All rights reserved.
49663Suri.wiener@arm.com *
59663Suri.wiener@arm.com * The license below extends only to copyright in the software and shall
69663Suri.wiener@arm.com * not be construed as granting a license to any other intellectual
79663Suri.wiener@arm.com * property including but not limited to intellectual property relating
89663Suri.wiener@arm.com * to a hardware implementation of the functionality of the software
99663Suri.wiener@arm.com * licensed hereunder.  You may use the software subject to the license
109663Suri.wiener@arm.com * terms below provided that you ensure that this notice is replicated
119663Suri.wiener@arm.com * unmodified and in its entirety in all distributions of the software,
129663Suri.wiener@arm.com * modified or unmodified, in source code or in binary form.
139663Suri.wiener@arm.com *
142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
157636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
162810SN/A * All rights reserved.
172810SN/A *
182810SN/A * Redistribution and use in source and binary forms, with or without
192810SN/A * modification, are permitted provided that the following conditions are
202810SN/A * met: redistributions of source code must retain the above copyright
212810SN/A * notice, this list of conditions and the following disclaimer;
222810SN/A * redistributions in binary form must reproduce the above copyright
232810SN/A * notice, this list of conditions and the following disclaimer in the
242810SN/A * documentation and/or other materials provided with the distribution;
252810SN/A * neither the name of the copyright holders nor the names of its
262810SN/A * contributors may be used to endorse or promote products derived from
272810SN/A * this software without specific prior written permission.
282810SN/A *
292810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402810SN/A *
412810SN/A * Authors: Erik Hallnor
422810SN/A *          Dave Greene
432810SN/A */
442810SN/A
452810SN/A/**
462810SN/A * @file
472810SN/A * Miss Status and Handling Register (MSHR) definitions.
482810SN/A */
492810SN/A
5011486Snikos.nikoleris@arm.com#include "mem/cache/mshr.hh"
5111486Snikos.nikoleris@arm.com
526216Snate@binkert.org#include <algorithm>
536216Snate@binkert.org#include <cassert>
542810SN/A#include <string>
552810SN/A#include <vector>
562810SN/A
576216Snate@binkert.org#include "base/misc.hh"
586216Snate@binkert.org#include "base/types.hh"
598232Snate@binkert.org#include "debug/Cache.hh"
606216Snate@binkert.org#include "mem/cache/cache.hh"
616216Snate@binkert.org#include "sim/core.hh"
622810SN/A
632810SN/Ausing namespace std;
642810SN/A
6511375Sandreas.hansson@arm.comMSHR::MSHR() : downstreamPending(false),
6611284Sandreas.hansson@arm.com               pendingModified(false),
6710503SCurtis.Dunham@arm.com               postInvalidate(false), postDowngrade(false),
6811375Sandreas.hansson@arm.com               isForward(false), allocOnFill(false)
692810SN/A{
702810SN/A}
712810SN/A
724903SN/AMSHR::TargetList::TargetList()
7311284Sandreas.hansson@arm.com    : needsWritable(false), hasUpgrade(false)
744903SN/A{}
754903SN/A
764903SN/A
7711740Snikos.nikoleris@arm.comvoid
7811740Snikos.nikoleris@arm.comMSHR::TargetList::updateFlags(PacketPtr pkt, Target::Source source)
794903SN/A{
805875Ssteve.reinhardt@amd.com    if (source != Target::FromSnoop) {
8111284Sandreas.hansson@arm.com        if (pkt->needsWritable()) {
8211284Sandreas.hansson@arm.com            needsWritable = true;
834903SN/A        }
844903SN/A
857669Ssteve.reinhardt@amd.com        // StoreCondReq is effectively an upgrade if it's in an MSHR
867669Ssteve.reinhardt@amd.com        // since it would have been failed already if we didn't have a
877669Ssteve.reinhardt@amd.com        // read-only copy
887669Ssteve.reinhardt@amd.com        if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
894903SN/A            hasUpgrade = true;
904903SN/A        }
915318SN/A    }
9211740Snikos.nikoleris@arm.com}
934908SN/A
9411740Snikos.nikoleris@arm.comvoid
9511740Snikos.nikoleris@arm.comMSHR::TargetList::populateFlags()
9611740Snikos.nikoleris@arm.com{
9711740Snikos.nikoleris@arm.com    resetFlags();
9811740Snikos.nikoleris@arm.com    for (auto& t: *this) {
9911740Snikos.nikoleris@arm.com        updateFlags(t.pkt, t.source);
10011740Snikos.nikoleris@arm.com    }
10111740Snikos.nikoleris@arm.com}
10211740Snikos.nikoleris@arm.com
10311740Snikos.nikoleris@arm.cominline void
10411740Snikos.nikoleris@arm.comMSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
10511740Snikos.nikoleris@arm.com                      Counter order, Target::Source source, bool markPending)
10611740Snikos.nikoleris@arm.com{
10711740Snikos.nikoleris@arm.com    updateFlags(pkt, source);
1085318SN/A    if (markPending) {
1099543Ssascha.bischoff@arm.com        // Iterate over the SenderState stack and see if we find
1109543Ssascha.bischoff@arm.com        // an MSHR entry. If we do, set the downstreamPending
1119543Ssascha.bischoff@arm.com        // flag. Otherwise, do nothing.
1129543Ssascha.bischoff@arm.com        MSHR *mshr = pkt->findNextSenderState<MSHR>();
11311484Snikos.nikoleris@arm.com        if (mshr != nullptr) {
1144908SN/A            assert(!mshr->downstreamPending);
1154908SN/A            mshr->downstreamPending = true;
11611083Sandreas.hansson@arm.com        } else {
11711083Sandreas.hansson@arm.com            // No need to clear downstreamPending later
11811083Sandreas.hansson@arm.com            markPending = false;
1194908SN/A        }
1204903SN/A    }
1214903SN/A
12210922Sandreas.hansson@arm.com    emplace_back(pkt, readyTime, order, source, markPending);
1234903SN/A}
1244903SN/A
1254903SN/A
1267667Ssteve.reinhardt@amd.comstatic void
1277667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt)
1287667Ssteve.reinhardt@amd.com{
12911286Sandreas.hansson@arm.com    // remember if the current packet has data allocated
13011286Sandreas.hansson@arm.com    bool has_data = pkt->hasData() || pkt->hasRespData();
13111286Sandreas.hansson@arm.com
1327667Ssteve.reinhardt@amd.com    if (pkt->cmd == MemCmd::UpgradeReq) {
1337667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::ReadExReq;
1347667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
1357667Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
1367667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::SCUpgradeFailReq;
1377667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
1387669Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::StoreCondReq) {
1397669Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::StoreCondFailReq;
1407669Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
1417667Ssteve.reinhardt@amd.com    }
14211286Sandreas.hansson@arm.com
14311286Sandreas.hansson@arm.com    if (!has_data) {
14411286Sandreas.hansson@arm.com        // there is no sensible way of setting the data field if the
14511286Sandreas.hansson@arm.com        // new command actually would carry data
14611286Sandreas.hansson@arm.com        assert(!pkt->hasData());
14711286Sandreas.hansson@arm.com
14811286Sandreas.hansson@arm.com        if (pkt->hasRespData()) {
14911286Sandreas.hansson@arm.com            // we went from a packet that had no data (neither request,
15011286Sandreas.hansson@arm.com            // nor response), to one that does, and therefore we need to
15111286Sandreas.hansson@arm.com            // actually allocate space for the data payload
15211286Sandreas.hansson@arm.com            pkt->allocate();
15311286Sandreas.hansson@arm.com        }
15411286Sandreas.hansson@arm.com    }
1557667Ssteve.reinhardt@amd.com}
1567667Ssteve.reinhardt@amd.com
1577667Ssteve.reinhardt@amd.com
1584903SN/Avoid
1594903SN/AMSHR::TargetList::replaceUpgrades()
1604903SN/A{
1614903SN/A    if (!hasUpgrade)
1624903SN/A        return;
1634903SN/A
16410766Sandreas.hansson@arm.com    for (auto& t : *this) {
16510766Sandreas.hansson@arm.com        replaceUpgrade(t.pkt);
1664903SN/A    }
1674903SN/A
1684903SN/A    hasUpgrade = false;
1694903SN/A}
1704903SN/A
1714903SN/A
1722810SN/Avoid
1734908SN/AMSHR::TargetList::clearDownstreamPending()
1744908SN/A{
17510766Sandreas.hansson@arm.com    for (auto& t : *this) {
17610766Sandreas.hansson@arm.com        if (t.markedPending) {
1779543Ssascha.bischoff@arm.com            // Iterate over the SenderState stack and see if we find
1789543Ssascha.bischoff@arm.com            // an MSHR entry. If we find one, clear the
1799543Ssascha.bischoff@arm.com            // downstreamPending flag by calling
1809543Ssascha.bischoff@arm.com            // clearDownstreamPending(). This recursively clears the
1819543Ssascha.bischoff@arm.com            // downstreamPending flag in all caches this packet has
1829543Ssascha.bischoff@arm.com            // passed through.
18310766Sandreas.hansson@arm.com            MSHR *mshr = t.pkt->findNextSenderState<MSHR>();
18411484Snikos.nikoleris@arm.com            if (mshr != nullptr) {
1855318SN/A                mshr->clearDownstreamPending();
1865318SN/A            }
1874908SN/A        }
1884908SN/A    }
1894908SN/A}
1904908SN/A
1914908SN/A
1924920SN/Abool
1934920SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt)
1944920SN/A{
19510766Sandreas.hansson@arm.com    for (auto& t : *this) {
19610766Sandreas.hansson@arm.com        if (pkt->checkFunctional(t.pkt)) {
1974920SN/A            return true;
1984920SN/A        }
1994920SN/A    }
2004920SN/A
2014920SN/A    return false;
2024920SN/A}
2034920SN/A
2044920SN/A
2054908SN/Avoid
20610766Sandreas.hansson@arm.comMSHR::TargetList::print(std::ostream &os, int verbosity,
20710766Sandreas.hansson@arm.com                        const std::string &prefix) const
2085314SN/A{
20910766Sandreas.hansson@arm.com    for (auto& t : *this) {
2105875Ssteve.reinhardt@amd.com        const char *s;
21110766Sandreas.hansson@arm.com        switch (t.source) {
2128988SAli.Saidi@ARM.com          case Target::FromCPU:
2138988SAli.Saidi@ARM.com            s = "FromCPU";
2148988SAli.Saidi@ARM.com            break;
2158988SAli.Saidi@ARM.com          case Target::FromSnoop:
2168988SAli.Saidi@ARM.com            s = "FromSnoop";
2178988SAli.Saidi@ARM.com            break;
2188988SAli.Saidi@ARM.com          case Target::FromPrefetcher:
2198988SAli.Saidi@ARM.com            s = "FromPrefetcher";
2208988SAli.Saidi@ARM.com            break;
2218988SAli.Saidi@ARM.com          default:
2228988SAli.Saidi@ARM.com            s = "";
2238988SAli.Saidi@ARM.com            break;
2245875Ssteve.reinhardt@amd.com        }
2255875Ssteve.reinhardt@amd.com        ccprintf(os, "%s%s: ", prefix, s);
22610766Sandreas.hansson@arm.com        t.pkt->print(os, verbosity, "");
2275314SN/A    }
2285314SN/A}
2295314SN/A
2305314SN/A
2315314SN/Avoid
23210764Sandreas.hansson@arm.comMSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
23311197Sandreas.hansson@arm.com               Tick when_ready, Counter _order, bool alloc_on_fill)
2342810SN/A{
23510764Sandreas.hansson@arm.com    blkAddr = blk_addr;
23610764Sandreas.hansson@arm.com    blkSize = blk_size;
23710028SGiacomo.Gabrielli@arm.com    isSecure = target->isSecure();
23810764Sandreas.hansson@arm.com    readyTime = when_ready;
2394666SN/A    order = _order;
2404626SN/A    assert(target);
2415730SSteve.Reinhardt@amd.com    isForward = false;
24211197Sandreas.hansson@arm.com    allocOnFill = alloc_on_fill;
2434626SN/A    _isUncacheable = target->req->isUncacheable();
2444626SN/A    inService = false;
2454908SN/A    downstreamPending = false;
2469725Sandreas.hansson@arm.com    assert(targets.isReset());
2474626SN/A    // Don't know of a case where we would allocate a new MSHR for a
2485875Ssteve.reinhardt@amd.com    // snoop (mem-side request), so set source according to request here
2495875Ssteve.reinhardt@amd.com    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
2505875Ssteve.reinhardt@amd.com        Target::FromPrefetcher : Target::FromCPU;
25110764Sandreas.hansson@arm.com    targets.add(target, when_ready, _order, source, true);
2529725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
2532810SN/A}
2542810SN/A
2554908SN/A
2565318SN/Avoid
2575318SN/AMSHR::clearDownstreamPending()
2585318SN/A{
2595318SN/A    assert(downstreamPending);
2605318SN/A    downstreamPending = false;
2615318SN/A    // recursively clear flag on any MSHRs we will be forwarding
2625318SN/A    // responses to
2639725Sandreas.hansson@arm.com    targets.clearDownstreamPending();
2645318SN/A}
2655318SN/A
26611375Sandreas.hansson@arm.comvoid
26711284Sandreas.hansson@arm.comMSHR::markInService(bool pending_modified_resp)
2684908SN/A{
2694908SN/A    assert(!inService);
27010424Sandreas.hansson@arm.com
2714908SN/A    inService = true;
27211284Sandreas.hansson@arm.com    pendingModified = targets.needsWritable || pending_modified_resp;
2737667Ssteve.reinhardt@amd.com    postInvalidate = postDowngrade = false;
2747667Ssteve.reinhardt@amd.com
2754908SN/A    if (!downstreamPending) {
2764908SN/A        // let upstream caches know that the request has made it to a
2774908SN/A        // level where it's going to get a response
2789725Sandreas.hansson@arm.com        targets.clearDownstreamPending();
2794908SN/A    }
2804908SN/A}
2814908SN/A
2824908SN/A
2832810SN/Avoid
2842810SN/AMSHR::deallocate()
2852810SN/A{
2869725Sandreas.hansson@arm.com    assert(targets.empty());
2879725Sandreas.hansson@arm.com    targets.resetFlags();
2889725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
2892810SN/A    inService = false;
2902810SN/A}
2912810SN/A
2922810SN/A/*
2932810SN/A * Adds a target to an MSHR
2942810SN/A */
2952810SN/Avoid
29611197Sandreas.hansson@arm.comMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order,
29711197Sandreas.hansson@arm.com                     bool alloc_on_fill)
2982810SN/A{
29910768Sandreas.hansson@arm.com    // assume we'd never issue a prefetch when we've got an
30010768Sandreas.hansson@arm.com    // outstanding miss
30110768Sandreas.hansson@arm.com    assert(pkt->cmd != MemCmd::HardPFReq);
30210768Sandreas.hansson@arm.com
30310768Sandreas.hansson@arm.com    // uncacheable accesses always allocate a new MSHR, and cacheable
30410768Sandreas.hansson@arm.com    // accesses ignore any uncacheable MSHRs, thus we should never
30510768Sandreas.hansson@arm.com    // have targets addded if originally allocated uncacheable
30610768Sandreas.hansson@arm.com    assert(!_isUncacheable);
30710768Sandreas.hansson@arm.com
30811197Sandreas.hansson@arm.com    // potentially re-evaluate whether we should allocate on a fill or
30911197Sandreas.hansson@arm.com    // not
31011197Sandreas.hansson@arm.com    allocOnFill = allocOnFill || alloc_on_fill;
31111197Sandreas.hansson@arm.com
3124903SN/A    // if there's a request already in service for this MSHR, we will
3134903SN/A    // have to defer the new target until after the response if any of
3144903SN/A    // the following are true:
3154903SN/A    // - there are other targets already deferred
3164903SN/A    // - there's a pending invalidate to be applied after the response
3174903SN/A    //   comes back (but before this target is processed)
31811284Sandreas.hansson@arm.com    // - this target requires a writable block and either we're not
31911284Sandreas.hansson@arm.com    //   getting a writable block back or we have already snooped
32011284Sandreas.hansson@arm.com    //   another read request that will downgrade our writable block
32111284Sandreas.hansson@arm.com    //   to non-writable (Shared or Owned)
3224903SN/A    if (inService &&
3239725Sandreas.hansson@arm.com        (!deferredTargets.empty() || hasPostInvalidate() ||
32411284Sandreas.hansson@arm.com         (pkt->needsWritable() &&
32511284Sandreas.hansson@arm.com          (!isPendingModified() || hasPostDowngrade() || isForward)))) {
3264903SN/A        // need to put on deferred list
3277667Ssteve.reinhardt@amd.com        if (hasPostInvalidate())
3287667Ssteve.reinhardt@amd.com            replaceUpgrade(pkt);
3299725Sandreas.hansson@arm.com        deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true);
3304665SN/A    } else {
3315318SN/A        // No request outstanding, or still OK to append to
3325318SN/A        // outstanding request: append to regular target list.  Only
3335318SN/A        // mark pending if current request hasn't been issued yet
3345318SN/A        // (isn't in service).
3359725Sandreas.hansson@arm.com        targets.add(pkt, whenReady, _order, Target::FromCPU, !inService);
3362810SN/A    }
3374665SN/A}
3384665SN/A
3394902SN/Abool
3404902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order)
3414665SN/A{
34210725Sandreas.hansson@arm.com    DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
3439663Suri.wiener@arm.com            pkt->cmdString(), pkt->getAddr(), pkt->getSize());
34411279Sandreas.hansson@arm.com
34511284Sandreas.hansson@arm.com    // when we snoop packets the needsWritable and isInvalidate flags
34611279Sandreas.hansson@arm.com    // should always be the same, however, this assumes that we never
34711279Sandreas.hansson@arm.com    // snoop writes as they are currently not marked as invalidations
34811284Sandreas.hansson@arm.com    panic_if(pkt->needsWritable() != pkt->isInvalidate(),
34911284Sandreas.hansson@arm.com             "%s got snoop %s to addr %#llx where needsWritable, "
35011279Sandreas.hansson@arm.com             "does not match isInvalidate", name(), pkt->cmdString(),
35111279Sandreas.hansson@arm.com             pkt->getAddr());
35211279Sandreas.hansson@arm.com
3534910SN/A    if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
3544903SN/A        // Request has not been issued yet, or it's been issued
3554903SN/A        // locally but is buffered unissued at some downstream cache
3564903SN/A        // which is forwarding us this snoop.  Either way, the packet
3574903SN/A        // we're snooping logically precedes this MSHR's request, so
3584903SN/A        // the snoop has no impact on the MSHR, but must be processed
3594903SN/A        // in the standard way by the cache.  The only exception is
3604903SN/A        // that if we're an L2+ cache buffering an UpgradeReq from a
3614903SN/A        // higher-level cache, and the snoop is invalidating, then our
3624903SN/A        // buffered upgrades must be converted to read exclusives,
3634903SN/A        // since the upper-level cache no longer has a valid copy.
3644903SN/A        // That is, even though the upper-level cache got out on its
3654903SN/A        // local bus first, some other invalidating transaction
3664903SN/A        // reached the global bus before the upgrade did.
36711284Sandreas.hansson@arm.com        if (pkt->needsWritable()) {
3689725Sandreas.hansson@arm.com            targets.replaceUpgrades();
3699725Sandreas.hansson@arm.com            deferredTargets.replaceUpgrades();
3704903SN/A        }
3714903SN/A
3724902SN/A        return false;
3734902SN/A    }
3744665SN/A
3754903SN/A    // From here on down, the request issued by this MSHR logically
3764903SN/A    // precedes the request we're snooping.
37711284Sandreas.hansson@arm.com    if (pkt->needsWritable()) {
3784903SN/A        // snooped request still precedes the re-request we'll have to
3794903SN/A        // issue for deferred targets, if any...
3809725Sandreas.hansson@arm.com        deferredTargets.replaceUpgrades();
3814903SN/A    }
3824903SN/A
3837667Ssteve.reinhardt@amd.com    if (hasPostInvalidate()) {
3844665SN/A        // a prior snoop has already appended an invalidation, so
3854903SN/A        // logically we don't have the block anymore; no need for
3864903SN/A        // further snooping.
3874902SN/A        return true;
3884665SN/A    }
3894665SN/A
39011284Sandreas.hansson@arm.com    if (isPendingModified() || pkt->isInvalidate()) {
3917667Ssteve.reinhardt@amd.com        // We need to save and replay the packet in two cases:
39211284Sandreas.hansson@arm.com        // 1. We're awaiting a writable copy (Modified or Exclusive),
39311284Sandreas.hansson@arm.com        //    so this MSHR is the orgering point, and we need to respond
39411284Sandreas.hansson@arm.com        //    after we receive data.
3957667Ssteve.reinhardt@amd.com        // 2. It's an invalidation (e.g., UpgradeReq), and we need
3967667Ssteve.reinhardt@amd.com        //    to forward the snoop up the hierarchy after the current
3977667Ssteve.reinhardt@amd.com        //    transaction completes.
39810571Sandreas.hansson@arm.com
39911271Sandreas.hansson@arm.com        // Start by determining if we will eventually respond or not,
40011271Sandreas.hansson@arm.com        // matching the conditions checked in Cache::handleSnoop
40111284Sandreas.hansson@arm.com        bool will_respond = isPendingModified() && pkt->needsResponse() &&
40211271Sandreas.hansson@arm.com            pkt->cmd != MemCmd::InvalidateReq;
40311271Sandreas.hansson@arm.com
40411271Sandreas.hansson@arm.com        // The packet we are snooping may be deleted by the time we
40511271Sandreas.hansson@arm.com        // actually process the target, and we consequently need to
40611271Sandreas.hansson@arm.com        // save a copy here. Clear flags and also allocate new data as
40711271Sandreas.hansson@arm.com        // the original packet data storage may have been deleted by
40811271Sandreas.hansson@arm.com        // the time we get to process this packet. In the cases where
40911271Sandreas.hansson@arm.com        // we are not responding after handling the snoop we also need
41011271Sandreas.hansson@arm.com        // to create a copy of the request to be on the safe side. In
41111271Sandreas.hansson@arm.com        // the latter case the cache is responsible for deleting both
41211271Sandreas.hansson@arm.com        // the packet and the request as part of handling the deferred
41311271Sandreas.hansson@arm.com        // snoop.
41411271Sandreas.hansson@arm.com        PacketPtr cp_pkt = will_respond ? new Packet(pkt, true, true) :
41511271Sandreas.hansson@arm.com            new Packet(new Request(*pkt->req), pkt->cmd);
4164670SN/A
41711490Sandreas.hansson@arm.com        if (will_respond) {
41811284Sandreas.hansson@arm.com            // we are the ordering point, and will consequently
41911284Sandreas.hansson@arm.com            // respond, and depending on whether the packet
42011284Sandreas.hansson@arm.com            // needsWritable or not we either pass a Shared line or a
42111284Sandreas.hansson@arm.com            // Modified line
42211284Sandreas.hansson@arm.com            pkt->setCacheResponding();
42311284Sandreas.hansson@arm.com
42411284Sandreas.hansson@arm.com            // inform the cache hierarchy that this cache had the line
42511284Sandreas.hansson@arm.com            // in the Modified state, even if the response is passed
42611284Sandreas.hansson@arm.com            // as Shared (and thus non-writable)
42711284Sandreas.hansson@arm.com            pkt->setResponderHadWritable();
42811284Sandreas.hansson@arm.com
42910821Sandreas.hansson@arm.com            // in the case of an uncacheable request there is no need
43011284Sandreas.hansson@arm.com            // to set the responderHadWritable flag, but since the
43111284Sandreas.hansson@arm.com            // recipient does not care there is no harm in doing so
4324670SN/A        }
43310826Sstephan.diestelhorst@ARM.com        targets.add(cp_pkt, curTick(), _order, Target::FromSnoop,
43411284Sandreas.hansson@arm.com                    downstreamPending && targets.needsWritable);
4354670SN/A
43611284Sandreas.hansson@arm.com        if (pkt->needsWritable()) {
4374670SN/A            // This transaction will take away our pending copy
4387667Ssteve.reinhardt@amd.com            postInvalidate = true;
4394670SN/A        }
4407667Ssteve.reinhardt@amd.com    }
4417667Ssteve.reinhardt@amd.com
44211284Sandreas.hansson@arm.com    if (!pkt->needsWritable() && !pkt->req->isUncacheable()) {
4437667Ssteve.reinhardt@amd.com        // This transaction will get a read-shared copy, downgrading
44411284Sandreas.hansson@arm.com        // our copy if we had a writable one
4457667Ssteve.reinhardt@amd.com        postDowngrade = true;
44611284Sandreas.hansson@arm.com        // make sure that any downstream cache does not respond with a
44711284Sandreas.hansson@arm.com        // writable (and dirty) copy even if it has one, unless it was
44811284Sandreas.hansson@arm.com        // explicitly asked for one
44911284Sandreas.hansson@arm.com        pkt->setHasSharers();
4504667SN/A    }
4514902SN/A
4524902SN/A    return true;
4534665SN/A}
4544665SN/A
4554665SN/A
4564665SN/Abool
4574665SN/AMSHR::promoteDeferredTargets()
4584665SN/A{
4599725Sandreas.hansson@arm.com    assert(targets.empty());
4609725Sandreas.hansson@arm.com    if (deferredTargets.empty()) {
4614665SN/A        return false;
4624665SN/A    }
4634665SN/A
4644903SN/A    // swap targets & deferredTargets lists
4659725Sandreas.hansson@arm.com    std::swap(targets, deferredTargets);
4664903SN/A
4674903SN/A    // clear deferredTargets flags
4689725Sandreas.hansson@arm.com    deferredTargets.resetFlags();
4694903SN/A
4709725Sandreas.hansson@arm.com    order = targets.front().order;
4719725Sandreas.hansson@arm.com    readyTime = std::max(curTick(), targets.front().readyTime);
4724665SN/A
4734665SN/A    return true;
4742810SN/A}
4752810SN/A
4762810SN/A
4772810SN/Avoid
47811284Sandreas.hansson@arm.comMSHR::promoteWritable()
4794668SN/A{
48011284Sandreas.hansson@arm.com    if (deferredTargets.needsWritable &&
48111177Sandreas.hansson@arm.com        !(hasPostInvalidate() || hasPostDowngrade())) {
48211284Sandreas.hansson@arm.com        // We got a writable response, but we have deferred targets
48311284Sandreas.hansson@arm.com        // which are waiting to request a writable copy (not because
4845270SN/A        // of a pending invalidate).  This can happen if the original
48511284Sandreas.hansson@arm.com        // request was for a read-only block, but we got a writable
48611284Sandreas.hansson@arm.com        // response anyway. Since we got the writable copy there's no
48711284Sandreas.hansson@arm.com        // need to defer the targets, so move them up to the regular
48811284Sandreas.hansson@arm.com        // target list.
48911284Sandreas.hansson@arm.com        assert(!targets.needsWritable);
49011284Sandreas.hansson@arm.com        targets.needsWritable = true;
4915318SN/A        // if any of the deferred targets were upper-level cache
4925318SN/A        // requests marked downstreamPending, need to clear that
4935318SN/A        assert(!downstreamPending);  // not pending here anymore
4949725Sandreas.hansson@arm.com        deferredTargets.clearDownstreamPending();
4955270SN/A        // this clears out deferredTargets too
4969725Sandreas.hansson@arm.com        targets.splice(targets.end(), deferredTargets);
4979725Sandreas.hansson@arm.com        deferredTargets.resetFlags();
4985270SN/A    }
4994668SN/A}
5004668SN/A
5014668SN/A
5025314SN/Abool
5035314SN/AMSHR::checkFunctional(PacketPtr pkt)
5045314SN/A{
5055314SN/A    // For printing, we treat the MSHR as a whole as single entity.
5065314SN/A    // For other requests, we iterate over the individual targets
5075314SN/A    // since that's where the actual data lies.
5085314SN/A    if (pkt->isPrint()) {
50911484Snikos.nikoleris@arm.com        pkt->checkFunctional(this, blkAddr, isSecure, blkSize, nullptr);
5105314SN/A        return false;
5115314SN/A    } else {
5129725Sandreas.hansson@arm.com        return (targets.checkFunctional(pkt) ||
5139725Sandreas.hansson@arm.com                deferredTargets.checkFunctional(pkt));
5145314SN/A    }
5155314SN/A}
5165314SN/A
51711375Sandreas.hansson@arm.combool
51811375Sandreas.hansson@arm.comMSHR::sendPacket(Cache &cache)
51911375Sandreas.hansson@arm.com{
52011375Sandreas.hansson@arm.com    return cache.sendMSHRQueuePacket(this);
52111375Sandreas.hansson@arm.com}
5225314SN/A
5234668SN/Avoid
5245314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
5252810SN/A{
52610725Sandreas.hansson@arm.com    ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
52710764Sandreas.hansson@arm.com             prefix, blkAddr, blkAddr + blkSize - 1,
52810028SGiacomo.Gabrielli@arm.com             isSecure ? "s" : "ns",
5295730SSteve.Reinhardt@amd.com             isForward ? "Forward" : "",
53011197Sandreas.hansson@arm.com             allocOnFill ? "AllocOnFill" : "",
53111284Sandreas.hansson@arm.com             needsWritable() ? "Wrtbl" : "",
5325314SN/A             _isUncacheable ? "Unc" : "",
5335314SN/A             inService ? "InSvc" : "",
5345314SN/A             downstreamPending ? "DwnPend" : "",
53511610Snikos.nikoleris@arm.com             postInvalidate ? "PostInv" : "",
53611610Snikos.nikoleris@arm.com             postDowngrade ? "PostDowngr" : "");
5372810SN/A
53811610Snikos.nikoleris@arm.com    if (!targets.empty()) {
53911610Snikos.nikoleris@arm.com        ccprintf(os, "%s  Targets:\n", prefix);
54011610Snikos.nikoleris@arm.com        targets.print(os, verbosity, prefix + "    ");
54111610Snikos.nikoleris@arm.com    }
5429725Sandreas.hansson@arm.com    if (!deferredTargets.empty()) {
5435314SN/A        ccprintf(os, "%s  Deferred Targets:\n", prefix);
5449725Sandreas.hansson@arm.com        deferredTargets.print(os, verbosity, prefix + "      ");
5452810SN/A    }
5462810SN/A}
5472810SN/A
5489663Suri.wiener@arm.comstd::string
5499663Suri.wiener@arm.comMSHR::print() const
5509663Suri.wiener@arm.com{
5519663Suri.wiener@arm.com    ostringstream str;
5529663Suri.wiener@arm.com    print(str);
5539663Suri.wiener@arm.com    return str.str();
5549663Suri.wiener@arm.com}
555