mshr.cc revision 11610
12810SN/A/* 211375Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015-2016 ARM Limited 39663Suri.wiener@arm.com * All rights reserved. 49663Suri.wiener@arm.com * 59663Suri.wiener@arm.com * The license below extends only to copyright in the software and shall 69663Suri.wiener@arm.com * not be construed as granting a license to any other intellectual 79663Suri.wiener@arm.com * property including but not limited to intellectual property relating 89663Suri.wiener@arm.com * to a hardware implementation of the functionality of the software 99663Suri.wiener@arm.com * licensed hereunder. You may use the software subject to the license 109663Suri.wiener@arm.com * terms below provided that you ensure that this notice is replicated 119663Suri.wiener@arm.com * unmodified and in its entirety in all distributions of the software, 129663Suri.wiener@arm.com * modified or unmodified, in source code or in binary form. 139663Suri.wiener@arm.com * 142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc. 162810SN/A * All rights reserved. 172810SN/A * 182810SN/A * Redistribution and use in source and binary forms, with or without 192810SN/A * modification, are permitted provided that the following conditions are 202810SN/A * met: redistributions of source code must retain the above copyright 212810SN/A * notice, this list of conditions and the following disclaimer; 222810SN/A * redistributions in binary form must reproduce the above copyright 232810SN/A * notice, this list of conditions and the following disclaimer in the 242810SN/A * documentation and/or other materials provided with the distribution; 252810SN/A * neither the name of the copyright holders nor the names of its 262810SN/A * contributors may be used to endorse or promote products derived from 272810SN/A * this software without specific prior written permission. 282810SN/A * 292810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810SN/A * 412810SN/A * Authors: Erik Hallnor 422810SN/A * Dave Greene 432810SN/A */ 442810SN/A 452810SN/A/** 462810SN/A * @file 472810SN/A * Miss Status and Handling Register (MSHR) definitions. 482810SN/A */ 492810SN/A 5011486Snikos.nikoleris@arm.com#include "mem/cache/mshr.hh" 5111486Snikos.nikoleris@arm.com 526216Snate@binkert.org#include <algorithm> 536216Snate@binkert.org#include <cassert> 542810SN/A#include <string> 552810SN/A#include <vector> 562810SN/A 576216Snate@binkert.org#include "base/misc.hh" 586216Snate@binkert.org#include "base/types.hh" 598232Snate@binkert.org#include "debug/Cache.hh" 606216Snate@binkert.org#include "mem/cache/cache.hh" 616216Snate@binkert.org#include "sim/core.hh" 622810SN/A 632810SN/Ausing namespace std; 642810SN/A 6511375Sandreas.hansson@arm.comMSHR::MSHR() : downstreamPending(false), 6611284Sandreas.hansson@arm.com pendingModified(false), 6710503SCurtis.Dunham@arm.com postInvalidate(false), postDowngrade(false), 6811375Sandreas.hansson@arm.com isForward(false), allocOnFill(false) 692810SN/A{ 702810SN/A} 712810SN/A 724903SN/AMSHR::TargetList::TargetList() 7311284Sandreas.hansson@arm.com : needsWritable(false), hasUpgrade(false) 744903SN/A{} 754903SN/A 764903SN/A 774903SN/Ainline void 784908SN/AMSHR::TargetList::add(PacketPtr pkt, Tick readyTime, 795875Ssteve.reinhardt@amd.com Counter order, Target::Source source, bool markPending) 804903SN/A{ 815875Ssteve.reinhardt@amd.com if (source != Target::FromSnoop) { 8211284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 8311284Sandreas.hansson@arm.com needsWritable = true; 844903SN/A } 854903SN/A 867669Ssteve.reinhardt@amd.com // StoreCondReq is effectively an upgrade if it's in an MSHR 877669Ssteve.reinhardt@amd.com // since it would have been failed already if we didn't have a 887669Ssteve.reinhardt@amd.com // read-only copy 897669Ssteve.reinhardt@amd.com if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) { 904903SN/A hasUpgrade = true; 914903SN/A } 925318SN/A } 934908SN/A 945318SN/A if (markPending) { 959543Ssascha.bischoff@arm.com // Iterate over the SenderState stack and see if we find 969543Ssascha.bischoff@arm.com // an MSHR entry. If we do, set the downstreamPending 979543Ssascha.bischoff@arm.com // flag. Otherwise, do nothing. 989543Ssascha.bischoff@arm.com MSHR *mshr = pkt->findNextSenderState<MSHR>(); 9911484Snikos.nikoleris@arm.com if (mshr != nullptr) { 1004908SN/A assert(!mshr->downstreamPending); 1014908SN/A mshr->downstreamPending = true; 10211083Sandreas.hansson@arm.com } else { 10311083Sandreas.hansson@arm.com // No need to clear downstreamPending later 10411083Sandreas.hansson@arm.com markPending = false; 1054908SN/A } 1064903SN/A } 1074903SN/A 10810922Sandreas.hansson@arm.com emplace_back(pkt, readyTime, order, source, markPending); 1094903SN/A} 1104903SN/A 1114903SN/A 1127667Ssteve.reinhardt@amd.comstatic void 1137667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt) 1147667Ssteve.reinhardt@amd.com{ 11511286Sandreas.hansson@arm.com // remember if the current packet has data allocated 11611286Sandreas.hansson@arm.com bool has_data = pkt->hasData() || pkt->hasRespData(); 11711286Sandreas.hansson@arm.com 1187667Ssteve.reinhardt@amd.com if (pkt->cmd == MemCmd::UpgradeReq) { 1197667Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::ReadExReq; 1207667Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n"); 1217667Ssteve.reinhardt@amd.com } else if (pkt->cmd == MemCmd::SCUpgradeReq) { 1227667Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::SCUpgradeFailReq; 1237667Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n"); 1247669Ssteve.reinhardt@amd.com } else if (pkt->cmd == MemCmd::StoreCondReq) { 1257669Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::StoreCondFailReq; 1267669Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n"); 1277667Ssteve.reinhardt@amd.com } 12811286Sandreas.hansson@arm.com 12911286Sandreas.hansson@arm.com if (!has_data) { 13011286Sandreas.hansson@arm.com // there is no sensible way of setting the data field if the 13111286Sandreas.hansson@arm.com // new command actually would carry data 13211286Sandreas.hansson@arm.com assert(!pkt->hasData()); 13311286Sandreas.hansson@arm.com 13411286Sandreas.hansson@arm.com if (pkt->hasRespData()) { 13511286Sandreas.hansson@arm.com // we went from a packet that had no data (neither request, 13611286Sandreas.hansson@arm.com // nor response), to one that does, and therefore we need to 13711286Sandreas.hansson@arm.com // actually allocate space for the data payload 13811286Sandreas.hansson@arm.com pkt->allocate(); 13911286Sandreas.hansson@arm.com } 14011286Sandreas.hansson@arm.com } 1417667Ssteve.reinhardt@amd.com} 1427667Ssteve.reinhardt@amd.com 1437667Ssteve.reinhardt@amd.com 1444903SN/Avoid 1454903SN/AMSHR::TargetList::replaceUpgrades() 1464903SN/A{ 1474903SN/A if (!hasUpgrade) 1484903SN/A return; 1494903SN/A 15010766Sandreas.hansson@arm.com for (auto& t : *this) { 15110766Sandreas.hansson@arm.com replaceUpgrade(t.pkt); 1524903SN/A } 1534903SN/A 1544903SN/A hasUpgrade = false; 1554903SN/A} 1564903SN/A 1574903SN/A 1582810SN/Avoid 1594908SN/AMSHR::TargetList::clearDownstreamPending() 1604908SN/A{ 16110766Sandreas.hansson@arm.com for (auto& t : *this) { 16210766Sandreas.hansson@arm.com if (t.markedPending) { 1639543Ssascha.bischoff@arm.com // Iterate over the SenderState stack and see if we find 1649543Ssascha.bischoff@arm.com // an MSHR entry. If we find one, clear the 1659543Ssascha.bischoff@arm.com // downstreamPending flag by calling 1669543Ssascha.bischoff@arm.com // clearDownstreamPending(). This recursively clears the 1679543Ssascha.bischoff@arm.com // downstreamPending flag in all caches this packet has 1689543Ssascha.bischoff@arm.com // passed through. 16910766Sandreas.hansson@arm.com MSHR *mshr = t.pkt->findNextSenderState<MSHR>(); 17011484Snikos.nikoleris@arm.com if (mshr != nullptr) { 1715318SN/A mshr->clearDownstreamPending(); 1725318SN/A } 1734908SN/A } 1744908SN/A } 1754908SN/A} 1764908SN/A 1774908SN/A 1784920SN/Abool 1794920SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt) 1804920SN/A{ 18110766Sandreas.hansson@arm.com for (auto& t : *this) { 18210766Sandreas.hansson@arm.com if (pkt->checkFunctional(t.pkt)) { 1834920SN/A return true; 1844920SN/A } 1854920SN/A } 1864920SN/A 1874920SN/A return false; 1884920SN/A} 1894920SN/A 1904920SN/A 1914908SN/Avoid 19210766Sandreas.hansson@arm.comMSHR::TargetList::print(std::ostream &os, int verbosity, 19310766Sandreas.hansson@arm.com const std::string &prefix) const 1945314SN/A{ 19510766Sandreas.hansson@arm.com for (auto& t : *this) { 1965875Ssteve.reinhardt@amd.com const char *s; 19710766Sandreas.hansson@arm.com switch (t.source) { 1988988SAli.Saidi@ARM.com case Target::FromCPU: 1998988SAli.Saidi@ARM.com s = "FromCPU"; 2008988SAli.Saidi@ARM.com break; 2018988SAli.Saidi@ARM.com case Target::FromSnoop: 2028988SAli.Saidi@ARM.com s = "FromSnoop"; 2038988SAli.Saidi@ARM.com break; 2048988SAli.Saidi@ARM.com case Target::FromPrefetcher: 2058988SAli.Saidi@ARM.com s = "FromPrefetcher"; 2068988SAli.Saidi@ARM.com break; 2078988SAli.Saidi@ARM.com default: 2088988SAli.Saidi@ARM.com s = ""; 2098988SAli.Saidi@ARM.com break; 2105875Ssteve.reinhardt@amd.com } 2115875Ssteve.reinhardt@amd.com ccprintf(os, "%s%s: ", prefix, s); 21210766Sandreas.hansson@arm.com t.pkt->print(os, verbosity, ""); 2135314SN/A } 2145314SN/A} 2155314SN/A 2165314SN/A 2175314SN/Avoid 21810764Sandreas.hansson@arm.comMSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target, 21911197Sandreas.hansson@arm.com Tick when_ready, Counter _order, bool alloc_on_fill) 2202810SN/A{ 22110764Sandreas.hansson@arm.com blkAddr = blk_addr; 22210764Sandreas.hansson@arm.com blkSize = blk_size; 22310028SGiacomo.Gabrielli@arm.com isSecure = target->isSecure(); 22410764Sandreas.hansson@arm.com readyTime = when_ready; 2254666SN/A order = _order; 2264626SN/A assert(target); 2275730SSteve.Reinhardt@amd.com isForward = false; 22811197Sandreas.hansson@arm.com allocOnFill = alloc_on_fill; 2294626SN/A _isUncacheable = target->req->isUncacheable(); 2304626SN/A inService = false; 2314908SN/A downstreamPending = false; 2329725Sandreas.hansson@arm.com assert(targets.isReset()); 2334626SN/A // Don't know of a case where we would allocate a new MSHR for a 2345875Ssteve.reinhardt@amd.com // snoop (mem-side request), so set source according to request here 2355875Ssteve.reinhardt@amd.com Target::Source source = (target->cmd == MemCmd::HardPFReq) ? 2365875Ssteve.reinhardt@amd.com Target::FromPrefetcher : Target::FromCPU; 23710764Sandreas.hansson@arm.com targets.add(target, when_ready, _order, source, true); 2389725Sandreas.hansson@arm.com assert(deferredTargets.isReset()); 2392810SN/A} 2402810SN/A 2414908SN/A 2425318SN/Avoid 2435318SN/AMSHR::clearDownstreamPending() 2445318SN/A{ 2455318SN/A assert(downstreamPending); 2465318SN/A downstreamPending = false; 2475318SN/A // recursively clear flag on any MSHRs we will be forwarding 2485318SN/A // responses to 2499725Sandreas.hansson@arm.com targets.clearDownstreamPending(); 2505318SN/A} 2515318SN/A 25211375Sandreas.hansson@arm.comvoid 25311284Sandreas.hansson@arm.comMSHR::markInService(bool pending_modified_resp) 2544908SN/A{ 2554908SN/A assert(!inService); 25610424Sandreas.hansson@arm.com 2574908SN/A inService = true; 25811284Sandreas.hansson@arm.com pendingModified = targets.needsWritable || pending_modified_resp; 2597667Ssteve.reinhardt@amd.com postInvalidate = postDowngrade = false; 2607667Ssteve.reinhardt@amd.com 2614908SN/A if (!downstreamPending) { 2624908SN/A // let upstream caches know that the request has made it to a 2634908SN/A // level where it's going to get a response 2649725Sandreas.hansson@arm.com targets.clearDownstreamPending(); 2654908SN/A } 2664908SN/A} 2674908SN/A 2684908SN/A 2692810SN/Avoid 2702810SN/AMSHR::deallocate() 2712810SN/A{ 2729725Sandreas.hansson@arm.com assert(targets.empty()); 2739725Sandreas.hansson@arm.com targets.resetFlags(); 2749725Sandreas.hansson@arm.com assert(deferredTargets.isReset()); 2752810SN/A inService = false; 2762810SN/A} 2772810SN/A 2782810SN/A/* 2792810SN/A * Adds a target to an MSHR 2802810SN/A */ 2812810SN/Avoid 28211197Sandreas.hansson@arm.comMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order, 28311197Sandreas.hansson@arm.com bool alloc_on_fill) 2842810SN/A{ 28510768Sandreas.hansson@arm.com // assume we'd never issue a prefetch when we've got an 28610768Sandreas.hansson@arm.com // outstanding miss 28710768Sandreas.hansson@arm.com assert(pkt->cmd != MemCmd::HardPFReq); 28810768Sandreas.hansson@arm.com 28910768Sandreas.hansson@arm.com // uncacheable accesses always allocate a new MSHR, and cacheable 29010768Sandreas.hansson@arm.com // accesses ignore any uncacheable MSHRs, thus we should never 29110768Sandreas.hansson@arm.com // have targets addded if originally allocated uncacheable 29210768Sandreas.hansson@arm.com assert(!_isUncacheable); 29310768Sandreas.hansson@arm.com 29411197Sandreas.hansson@arm.com // potentially re-evaluate whether we should allocate on a fill or 29511197Sandreas.hansson@arm.com // not 29611197Sandreas.hansson@arm.com allocOnFill = allocOnFill || alloc_on_fill; 29711197Sandreas.hansson@arm.com 2984903SN/A // if there's a request already in service for this MSHR, we will 2994903SN/A // have to defer the new target until after the response if any of 3004903SN/A // the following are true: 3014903SN/A // - there are other targets already deferred 3024903SN/A // - there's a pending invalidate to be applied after the response 3034903SN/A // comes back (but before this target is processed) 30411284Sandreas.hansson@arm.com // - this target requires a writable block and either we're not 30511284Sandreas.hansson@arm.com // getting a writable block back or we have already snooped 30611284Sandreas.hansson@arm.com // another read request that will downgrade our writable block 30711284Sandreas.hansson@arm.com // to non-writable (Shared or Owned) 3084903SN/A if (inService && 3099725Sandreas.hansson@arm.com (!deferredTargets.empty() || hasPostInvalidate() || 31011284Sandreas.hansson@arm.com (pkt->needsWritable() && 31111284Sandreas.hansson@arm.com (!isPendingModified() || hasPostDowngrade() || isForward)))) { 3124903SN/A // need to put on deferred list 3137667Ssteve.reinhardt@amd.com if (hasPostInvalidate()) 3147667Ssteve.reinhardt@amd.com replaceUpgrade(pkt); 3159725Sandreas.hansson@arm.com deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true); 3164665SN/A } else { 3175318SN/A // No request outstanding, or still OK to append to 3185318SN/A // outstanding request: append to regular target list. Only 3195318SN/A // mark pending if current request hasn't been issued yet 3205318SN/A // (isn't in service). 3219725Sandreas.hansson@arm.com targets.add(pkt, whenReady, _order, Target::FromCPU, !inService); 3222810SN/A } 3234665SN/A} 3244665SN/A 3254902SN/Abool 3264902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order) 3274665SN/A{ 32810725Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 3299663Suri.wiener@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 33011279Sandreas.hansson@arm.com 33111284Sandreas.hansson@arm.com // when we snoop packets the needsWritable and isInvalidate flags 33211279Sandreas.hansson@arm.com // should always be the same, however, this assumes that we never 33311279Sandreas.hansson@arm.com // snoop writes as they are currently not marked as invalidations 33411284Sandreas.hansson@arm.com panic_if(pkt->needsWritable() != pkt->isInvalidate(), 33511284Sandreas.hansson@arm.com "%s got snoop %s to addr %#llx where needsWritable, " 33611279Sandreas.hansson@arm.com "does not match isInvalidate", name(), pkt->cmdString(), 33711279Sandreas.hansson@arm.com pkt->getAddr()); 33811279Sandreas.hansson@arm.com 3394910SN/A if (!inService || (pkt->isExpressSnoop() && downstreamPending)) { 3404903SN/A // Request has not been issued yet, or it's been issued 3414903SN/A // locally but is buffered unissued at some downstream cache 3424903SN/A // which is forwarding us this snoop. Either way, the packet 3434903SN/A // we're snooping logically precedes this MSHR's request, so 3444903SN/A // the snoop has no impact on the MSHR, but must be processed 3454903SN/A // in the standard way by the cache. The only exception is 3464903SN/A // that if we're an L2+ cache buffering an UpgradeReq from a 3474903SN/A // higher-level cache, and the snoop is invalidating, then our 3484903SN/A // buffered upgrades must be converted to read exclusives, 3494903SN/A // since the upper-level cache no longer has a valid copy. 3504903SN/A // That is, even though the upper-level cache got out on its 3514903SN/A // local bus first, some other invalidating transaction 3524903SN/A // reached the global bus before the upgrade did. 35311284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 3549725Sandreas.hansson@arm.com targets.replaceUpgrades(); 3559725Sandreas.hansson@arm.com deferredTargets.replaceUpgrades(); 3564903SN/A } 3574903SN/A 3584902SN/A return false; 3594902SN/A } 3604665SN/A 3614903SN/A // From here on down, the request issued by this MSHR logically 3624903SN/A // precedes the request we're snooping. 36311284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 3644903SN/A // snooped request still precedes the re-request we'll have to 3654903SN/A // issue for deferred targets, if any... 3669725Sandreas.hansson@arm.com deferredTargets.replaceUpgrades(); 3674903SN/A } 3684903SN/A 3697667Ssteve.reinhardt@amd.com if (hasPostInvalidate()) { 3704665SN/A // a prior snoop has already appended an invalidation, so 3714903SN/A // logically we don't have the block anymore; no need for 3724903SN/A // further snooping. 3734902SN/A return true; 3744665SN/A } 3754665SN/A 37611284Sandreas.hansson@arm.com if (isPendingModified() || pkt->isInvalidate()) { 3777667Ssteve.reinhardt@amd.com // We need to save and replay the packet in two cases: 37811284Sandreas.hansson@arm.com // 1. We're awaiting a writable copy (Modified or Exclusive), 37911284Sandreas.hansson@arm.com // so this MSHR is the orgering point, and we need to respond 38011284Sandreas.hansson@arm.com // after we receive data. 3817667Ssteve.reinhardt@amd.com // 2. It's an invalidation (e.g., UpgradeReq), and we need 3827667Ssteve.reinhardt@amd.com // to forward the snoop up the hierarchy after the current 3837667Ssteve.reinhardt@amd.com // transaction completes. 38410571Sandreas.hansson@arm.com 38511271Sandreas.hansson@arm.com // Start by determining if we will eventually respond or not, 38611271Sandreas.hansson@arm.com // matching the conditions checked in Cache::handleSnoop 38711284Sandreas.hansson@arm.com bool will_respond = isPendingModified() && pkt->needsResponse() && 38811271Sandreas.hansson@arm.com pkt->cmd != MemCmd::InvalidateReq; 38911271Sandreas.hansson@arm.com 39011271Sandreas.hansson@arm.com // The packet we are snooping may be deleted by the time we 39111271Sandreas.hansson@arm.com // actually process the target, and we consequently need to 39211271Sandreas.hansson@arm.com // save a copy here. Clear flags and also allocate new data as 39311271Sandreas.hansson@arm.com // the original packet data storage may have been deleted by 39411271Sandreas.hansson@arm.com // the time we get to process this packet. In the cases where 39511271Sandreas.hansson@arm.com // we are not responding after handling the snoop we also need 39611271Sandreas.hansson@arm.com // to create a copy of the request to be on the safe side. In 39711271Sandreas.hansson@arm.com // the latter case the cache is responsible for deleting both 39811271Sandreas.hansson@arm.com // the packet and the request as part of handling the deferred 39911271Sandreas.hansson@arm.com // snoop. 40011271Sandreas.hansson@arm.com PacketPtr cp_pkt = will_respond ? new Packet(pkt, true, true) : 40111271Sandreas.hansson@arm.com new Packet(new Request(*pkt->req), pkt->cmd); 4024670SN/A 40311490Sandreas.hansson@arm.com if (will_respond) { 40411284Sandreas.hansson@arm.com // we are the ordering point, and will consequently 40511284Sandreas.hansson@arm.com // respond, and depending on whether the packet 40611284Sandreas.hansson@arm.com // needsWritable or not we either pass a Shared line or a 40711284Sandreas.hansson@arm.com // Modified line 40811284Sandreas.hansson@arm.com pkt->setCacheResponding(); 40911284Sandreas.hansson@arm.com 41011284Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 41111284Sandreas.hansson@arm.com // in the Modified state, even if the response is passed 41211284Sandreas.hansson@arm.com // as Shared (and thus non-writable) 41311284Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 41411284Sandreas.hansson@arm.com 41510821Sandreas.hansson@arm.com // in the case of an uncacheable request there is no need 41611284Sandreas.hansson@arm.com // to set the responderHadWritable flag, but since the 41711284Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 4184670SN/A } 41910826Sstephan.diestelhorst@ARM.com targets.add(cp_pkt, curTick(), _order, Target::FromSnoop, 42011284Sandreas.hansson@arm.com downstreamPending && targets.needsWritable); 4214670SN/A 42211284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 4234670SN/A // This transaction will take away our pending copy 4247667Ssteve.reinhardt@amd.com postInvalidate = true; 4254670SN/A } 4267667Ssteve.reinhardt@amd.com } 4277667Ssteve.reinhardt@amd.com 42811284Sandreas.hansson@arm.com if (!pkt->needsWritable() && !pkt->req->isUncacheable()) { 4297667Ssteve.reinhardt@amd.com // This transaction will get a read-shared copy, downgrading 43011284Sandreas.hansson@arm.com // our copy if we had a writable one 4317667Ssteve.reinhardt@amd.com postDowngrade = true; 43211284Sandreas.hansson@arm.com // make sure that any downstream cache does not respond with a 43311284Sandreas.hansson@arm.com // writable (and dirty) copy even if it has one, unless it was 43411284Sandreas.hansson@arm.com // explicitly asked for one 43511284Sandreas.hansson@arm.com pkt->setHasSharers(); 4364667SN/A } 4374902SN/A 4384902SN/A return true; 4394665SN/A} 4404665SN/A 4414665SN/A 4424665SN/Abool 4434665SN/AMSHR::promoteDeferredTargets() 4444665SN/A{ 4459725Sandreas.hansson@arm.com assert(targets.empty()); 4469725Sandreas.hansson@arm.com if (deferredTargets.empty()) { 4474665SN/A return false; 4484665SN/A } 4494665SN/A 4504903SN/A // swap targets & deferredTargets lists 4519725Sandreas.hansson@arm.com std::swap(targets, deferredTargets); 4524903SN/A 4534903SN/A // clear deferredTargets flags 4549725Sandreas.hansson@arm.com deferredTargets.resetFlags(); 4554903SN/A 4569725Sandreas.hansson@arm.com order = targets.front().order; 4579725Sandreas.hansson@arm.com readyTime = std::max(curTick(), targets.front().readyTime); 4584665SN/A 4594665SN/A return true; 4602810SN/A} 4612810SN/A 4622810SN/A 4632810SN/Avoid 46411284Sandreas.hansson@arm.comMSHR::promoteWritable() 4654668SN/A{ 46611284Sandreas.hansson@arm.com if (deferredTargets.needsWritable && 46711177Sandreas.hansson@arm.com !(hasPostInvalidate() || hasPostDowngrade())) { 46811284Sandreas.hansson@arm.com // We got a writable response, but we have deferred targets 46911284Sandreas.hansson@arm.com // which are waiting to request a writable copy (not because 4705270SN/A // of a pending invalidate). This can happen if the original 47111284Sandreas.hansson@arm.com // request was for a read-only block, but we got a writable 47211284Sandreas.hansson@arm.com // response anyway. Since we got the writable copy there's no 47311284Sandreas.hansson@arm.com // need to defer the targets, so move them up to the regular 47411284Sandreas.hansson@arm.com // target list. 47511284Sandreas.hansson@arm.com assert(!targets.needsWritable); 47611284Sandreas.hansson@arm.com targets.needsWritable = true; 4775318SN/A // if any of the deferred targets were upper-level cache 4785318SN/A // requests marked downstreamPending, need to clear that 4795318SN/A assert(!downstreamPending); // not pending here anymore 4809725Sandreas.hansson@arm.com deferredTargets.clearDownstreamPending(); 4815270SN/A // this clears out deferredTargets too 4829725Sandreas.hansson@arm.com targets.splice(targets.end(), deferredTargets); 4839725Sandreas.hansson@arm.com deferredTargets.resetFlags(); 4845270SN/A } 4854668SN/A} 4864668SN/A 4874668SN/A 4885314SN/Abool 4895314SN/AMSHR::checkFunctional(PacketPtr pkt) 4905314SN/A{ 4915314SN/A // For printing, we treat the MSHR as a whole as single entity. 4925314SN/A // For other requests, we iterate over the individual targets 4935314SN/A // since that's where the actual data lies. 4945314SN/A if (pkt->isPrint()) { 49511484Snikos.nikoleris@arm.com pkt->checkFunctional(this, blkAddr, isSecure, blkSize, nullptr); 4965314SN/A return false; 4975314SN/A } else { 4989725Sandreas.hansson@arm.com return (targets.checkFunctional(pkt) || 4999725Sandreas.hansson@arm.com deferredTargets.checkFunctional(pkt)); 5005314SN/A } 5015314SN/A} 5025314SN/A 50311375Sandreas.hansson@arm.combool 50411375Sandreas.hansson@arm.comMSHR::sendPacket(Cache &cache) 50511375Sandreas.hansson@arm.com{ 50611375Sandreas.hansson@arm.com return cache.sendMSHRQueuePacket(this); 50711375Sandreas.hansson@arm.com} 5085314SN/A 5094668SN/Avoid 5105314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const 5112810SN/A{ 51210725Sandreas.hansson@arm.com ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n", 51310764Sandreas.hansson@arm.com prefix, blkAddr, blkAddr + blkSize - 1, 51410028SGiacomo.Gabrielli@arm.com isSecure ? "s" : "ns", 5155730SSteve.Reinhardt@amd.com isForward ? "Forward" : "", 51611197Sandreas.hansson@arm.com allocOnFill ? "AllocOnFill" : "", 51711284Sandreas.hansson@arm.com needsWritable() ? "Wrtbl" : "", 5185314SN/A _isUncacheable ? "Unc" : "", 5195314SN/A inService ? "InSvc" : "", 5205314SN/A downstreamPending ? "DwnPend" : "", 52111610Snikos.nikoleris@arm.com postInvalidate ? "PostInv" : "", 52211610Snikos.nikoleris@arm.com postDowngrade ? "PostDowngr" : ""); 5232810SN/A 52411610Snikos.nikoleris@arm.com if (!targets.empty()) { 52511610Snikos.nikoleris@arm.com ccprintf(os, "%s Targets:\n", prefix); 52611610Snikos.nikoleris@arm.com targets.print(os, verbosity, prefix + " "); 52711610Snikos.nikoleris@arm.com } 5289725Sandreas.hansson@arm.com if (!deferredTargets.empty()) { 5295314SN/A ccprintf(os, "%s Deferred Targets:\n", prefix); 5309725Sandreas.hansson@arm.com deferredTargets.print(os, verbosity, prefix + " "); 5312810SN/A } 5322810SN/A} 5332810SN/A 5349663Suri.wiener@arm.comstd::string 5359663Suri.wiener@arm.comMSHR::print() const 5369663Suri.wiener@arm.com{ 5379663Suri.wiener@arm.com ostringstream str; 5389663Suri.wiener@arm.com print(str); 5399663Suri.wiener@arm.com return str.str(); 5409663Suri.wiener@arm.com} 541