mshr.cc revision 11375
12810SN/A/*
211375Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015-2016 ARM Limited
39663Suri.wiener@arm.com * All rights reserved.
49663Suri.wiener@arm.com *
59663Suri.wiener@arm.com * The license below extends only to copyright in the software and shall
69663Suri.wiener@arm.com * not be construed as granting a license to any other intellectual
79663Suri.wiener@arm.com * property including but not limited to intellectual property relating
89663Suri.wiener@arm.com * to a hardware implementation of the functionality of the software
99663Suri.wiener@arm.com * licensed hereunder.  You may use the software subject to the license
109663Suri.wiener@arm.com * terms below provided that you ensure that this notice is replicated
119663Suri.wiener@arm.com * unmodified and in its entirety in all distributions of the software,
129663Suri.wiener@arm.com * modified or unmodified, in source code or in binary form.
139663Suri.wiener@arm.com *
142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
157636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
162810SN/A * All rights reserved.
172810SN/A *
182810SN/A * Redistribution and use in source and binary forms, with or without
192810SN/A * modification, are permitted provided that the following conditions are
202810SN/A * met: redistributions of source code must retain the above copyright
212810SN/A * notice, this list of conditions and the following disclaimer;
222810SN/A * redistributions in binary form must reproduce the above copyright
232810SN/A * notice, this list of conditions and the following disclaimer in the
242810SN/A * documentation and/or other materials provided with the distribution;
252810SN/A * neither the name of the copyright holders nor the names of its
262810SN/A * contributors may be used to endorse or promote products derived from
272810SN/A * this software without specific prior written permission.
282810SN/A *
292810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402810SN/A *
412810SN/A * Authors: Erik Hallnor
422810SN/A *          Dave Greene
432810SN/A */
442810SN/A
452810SN/A/**
462810SN/A * @file
472810SN/A * Miss Status and Handling Register (MSHR) definitions.
482810SN/A */
492810SN/A
506216Snate@binkert.org#include <algorithm>
516216Snate@binkert.org#include <cassert>
522810SN/A#include <string>
532810SN/A#include <vector>
542810SN/A
556216Snate@binkert.org#include "base/misc.hh"
566216Snate@binkert.org#include "base/types.hh"
578232Snate@binkert.org#include "debug/Cache.hh"
586216Snate@binkert.org#include "mem/cache/cache.hh"
595338Sstever@gmail.com#include "mem/cache/mshr.hh"
606216Snate@binkert.org#include "sim/core.hh"
612810SN/A
622810SN/Ausing namespace std;
632810SN/A
6411375Sandreas.hansson@arm.comMSHR::MSHR() : downstreamPending(false),
6511284Sandreas.hansson@arm.com               pendingModified(false),
6610503SCurtis.Dunham@arm.com               postInvalidate(false), postDowngrade(false),
6711375Sandreas.hansson@arm.com               isForward(false), allocOnFill(false)
682810SN/A{
692810SN/A}
702810SN/A
714903SN/AMSHR::TargetList::TargetList()
7211284Sandreas.hansson@arm.com    : needsWritable(false), hasUpgrade(false)
734903SN/A{}
744903SN/A
754903SN/A
764903SN/Ainline void
774908SN/AMSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
785875Ssteve.reinhardt@amd.com                      Counter order, Target::Source source, bool markPending)
794903SN/A{
805875Ssteve.reinhardt@amd.com    if (source != Target::FromSnoop) {
8111284Sandreas.hansson@arm.com        if (pkt->needsWritable()) {
8211284Sandreas.hansson@arm.com            needsWritable = true;
834903SN/A        }
844903SN/A
857669Ssteve.reinhardt@amd.com        // StoreCondReq is effectively an upgrade if it's in an MSHR
867669Ssteve.reinhardt@amd.com        // since it would have been failed already if we didn't have a
877669Ssteve.reinhardt@amd.com        // read-only copy
887669Ssteve.reinhardt@amd.com        if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
894903SN/A            hasUpgrade = true;
904903SN/A        }
915318SN/A    }
924908SN/A
935318SN/A    if (markPending) {
949543Ssascha.bischoff@arm.com        // Iterate over the SenderState stack and see if we find
959543Ssascha.bischoff@arm.com        // an MSHR entry. If we do, set the downstreamPending
969543Ssascha.bischoff@arm.com        // flag. Otherwise, do nothing.
979543Ssascha.bischoff@arm.com        MSHR *mshr = pkt->findNextSenderState<MSHR>();
984908SN/A        if (mshr != NULL) {
994908SN/A            assert(!mshr->downstreamPending);
1004908SN/A            mshr->downstreamPending = true;
10111083Sandreas.hansson@arm.com        } else {
10211083Sandreas.hansson@arm.com            // No need to clear downstreamPending later
10311083Sandreas.hansson@arm.com            markPending = false;
1044908SN/A        }
1054903SN/A    }
1064903SN/A
10710922Sandreas.hansson@arm.com    emplace_back(pkt, readyTime, order, source, markPending);
1084903SN/A}
1094903SN/A
1104903SN/A
1117667Ssteve.reinhardt@amd.comstatic void
1127667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt)
1137667Ssteve.reinhardt@amd.com{
11411286Sandreas.hansson@arm.com    // remember if the current packet has data allocated
11511286Sandreas.hansson@arm.com    bool has_data = pkt->hasData() || pkt->hasRespData();
11611286Sandreas.hansson@arm.com
1177667Ssteve.reinhardt@amd.com    if (pkt->cmd == MemCmd::UpgradeReq) {
1187667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::ReadExReq;
1197667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
1207667Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
1217667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::SCUpgradeFailReq;
1227667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
1237669Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::StoreCondReq) {
1247669Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::StoreCondFailReq;
1257669Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
1267667Ssteve.reinhardt@amd.com    }
12711286Sandreas.hansson@arm.com
12811286Sandreas.hansson@arm.com    if (!has_data) {
12911286Sandreas.hansson@arm.com        // there is no sensible way of setting the data field if the
13011286Sandreas.hansson@arm.com        // new command actually would carry data
13111286Sandreas.hansson@arm.com        assert(!pkt->hasData());
13211286Sandreas.hansson@arm.com
13311286Sandreas.hansson@arm.com        if (pkt->hasRespData()) {
13411286Sandreas.hansson@arm.com            // we went from a packet that had no data (neither request,
13511286Sandreas.hansson@arm.com            // nor response), to one that does, and therefore we need to
13611286Sandreas.hansson@arm.com            // actually allocate space for the data payload
13711286Sandreas.hansson@arm.com            pkt->allocate();
13811286Sandreas.hansson@arm.com        }
13911286Sandreas.hansson@arm.com    }
1407667Ssteve.reinhardt@amd.com}
1417667Ssteve.reinhardt@amd.com
1427667Ssteve.reinhardt@amd.com
1434903SN/Avoid
1444903SN/AMSHR::TargetList::replaceUpgrades()
1454903SN/A{
1464903SN/A    if (!hasUpgrade)
1474903SN/A        return;
1484903SN/A
14910766Sandreas.hansson@arm.com    for (auto& t : *this) {
15010766Sandreas.hansson@arm.com        replaceUpgrade(t.pkt);
1514903SN/A    }
1524903SN/A
1534903SN/A    hasUpgrade = false;
1544903SN/A}
1554903SN/A
1564903SN/A
1572810SN/Avoid
1584908SN/AMSHR::TargetList::clearDownstreamPending()
1594908SN/A{
16010766Sandreas.hansson@arm.com    for (auto& t : *this) {
16110766Sandreas.hansson@arm.com        if (t.markedPending) {
1629543Ssascha.bischoff@arm.com            // Iterate over the SenderState stack and see if we find
1639543Ssascha.bischoff@arm.com            // an MSHR entry. If we find one, clear the
1649543Ssascha.bischoff@arm.com            // downstreamPending flag by calling
1659543Ssascha.bischoff@arm.com            // clearDownstreamPending(). This recursively clears the
1669543Ssascha.bischoff@arm.com            // downstreamPending flag in all caches this packet has
1679543Ssascha.bischoff@arm.com            // passed through.
16810766Sandreas.hansson@arm.com            MSHR *mshr = t.pkt->findNextSenderState<MSHR>();
1695318SN/A            if (mshr != NULL) {
1705318SN/A                mshr->clearDownstreamPending();
1715318SN/A            }
1724908SN/A        }
1734908SN/A    }
1744908SN/A}
1754908SN/A
1764908SN/A
1774920SN/Abool
1784920SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt)
1794920SN/A{
18010766Sandreas.hansson@arm.com    for (auto& t : *this) {
18110766Sandreas.hansson@arm.com        if (pkt->checkFunctional(t.pkt)) {
1824920SN/A            return true;
1834920SN/A        }
1844920SN/A    }
1854920SN/A
1864920SN/A    return false;
1874920SN/A}
1884920SN/A
1894920SN/A
1904908SN/Avoid
19110766Sandreas.hansson@arm.comMSHR::TargetList::print(std::ostream &os, int verbosity,
19210766Sandreas.hansson@arm.com                        const std::string &prefix) const
1935314SN/A{
19410766Sandreas.hansson@arm.com    for (auto& t : *this) {
1955875Ssteve.reinhardt@amd.com        const char *s;
19610766Sandreas.hansson@arm.com        switch (t.source) {
1978988SAli.Saidi@ARM.com          case Target::FromCPU:
1988988SAli.Saidi@ARM.com            s = "FromCPU";
1998988SAli.Saidi@ARM.com            break;
2008988SAli.Saidi@ARM.com          case Target::FromSnoop:
2018988SAli.Saidi@ARM.com            s = "FromSnoop";
2028988SAli.Saidi@ARM.com            break;
2038988SAli.Saidi@ARM.com          case Target::FromPrefetcher:
2048988SAli.Saidi@ARM.com            s = "FromPrefetcher";
2058988SAli.Saidi@ARM.com            break;
2068988SAli.Saidi@ARM.com          default:
2078988SAli.Saidi@ARM.com            s = "";
2088988SAli.Saidi@ARM.com            break;
2095875Ssteve.reinhardt@amd.com        }
2105875Ssteve.reinhardt@amd.com        ccprintf(os, "%s%s: ", prefix, s);
21110766Sandreas.hansson@arm.com        t.pkt->print(os, verbosity, "");
2125314SN/A    }
2135314SN/A}
2145314SN/A
2155314SN/A
2165314SN/Avoid
21710764Sandreas.hansson@arm.comMSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
21811197Sandreas.hansson@arm.com               Tick when_ready, Counter _order, bool alloc_on_fill)
2192810SN/A{
22010764Sandreas.hansson@arm.com    blkAddr = blk_addr;
22110764Sandreas.hansson@arm.com    blkSize = blk_size;
22210028SGiacomo.Gabrielli@arm.com    isSecure = target->isSecure();
22310764Sandreas.hansson@arm.com    readyTime = when_ready;
2244666SN/A    order = _order;
2254626SN/A    assert(target);
2265730SSteve.Reinhardt@amd.com    isForward = false;
22711197Sandreas.hansson@arm.com    allocOnFill = alloc_on_fill;
2284626SN/A    _isUncacheable = target->req->isUncacheable();
2294626SN/A    inService = false;
2304908SN/A    downstreamPending = false;
2319725Sandreas.hansson@arm.com    assert(targets.isReset());
2324626SN/A    // Don't know of a case where we would allocate a new MSHR for a
2335875Ssteve.reinhardt@amd.com    // snoop (mem-side request), so set source according to request here
2345875Ssteve.reinhardt@amd.com    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
2355875Ssteve.reinhardt@amd.com        Target::FromPrefetcher : Target::FromCPU;
23610764Sandreas.hansson@arm.com    targets.add(target, when_ready, _order, source, true);
2379725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
2382810SN/A}
2392810SN/A
2404908SN/A
2415318SN/Avoid
2425318SN/AMSHR::clearDownstreamPending()
2435318SN/A{
2445318SN/A    assert(downstreamPending);
2455318SN/A    downstreamPending = false;
2465318SN/A    // recursively clear flag on any MSHRs we will be forwarding
2475318SN/A    // responses to
2489725Sandreas.hansson@arm.com    targets.clearDownstreamPending();
2495318SN/A}
2505318SN/A
25111375Sandreas.hansson@arm.comvoid
25211284Sandreas.hansson@arm.comMSHR::markInService(bool pending_modified_resp)
2534908SN/A{
2544908SN/A    assert(!inService);
25510424Sandreas.hansson@arm.com
2564908SN/A    inService = true;
25711284Sandreas.hansson@arm.com    pendingModified = targets.needsWritable || pending_modified_resp;
2587667Ssteve.reinhardt@amd.com    postInvalidate = postDowngrade = false;
2597667Ssteve.reinhardt@amd.com
2604908SN/A    if (!downstreamPending) {
2614908SN/A        // let upstream caches know that the request has made it to a
2624908SN/A        // level where it's going to get a response
2639725Sandreas.hansson@arm.com        targets.clearDownstreamPending();
2644908SN/A    }
2654908SN/A}
2664908SN/A
2674908SN/A
2682810SN/Avoid
2692810SN/AMSHR::deallocate()
2702810SN/A{
2719725Sandreas.hansson@arm.com    assert(targets.empty());
2729725Sandreas.hansson@arm.com    targets.resetFlags();
2739725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
2742810SN/A    inService = false;
2752810SN/A}
2762810SN/A
2772810SN/A/*
2782810SN/A * Adds a target to an MSHR
2792810SN/A */
2802810SN/Avoid
28111197Sandreas.hansson@arm.comMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order,
28211197Sandreas.hansson@arm.com                     bool alloc_on_fill)
2832810SN/A{
28410768Sandreas.hansson@arm.com    // assume we'd never issue a prefetch when we've got an
28510768Sandreas.hansson@arm.com    // outstanding miss
28610768Sandreas.hansson@arm.com    assert(pkt->cmd != MemCmd::HardPFReq);
28710768Sandreas.hansson@arm.com
28810768Sandreas.hansson@arm.com    // uncacheable accesses always allocate a new MSHR, and cacheable
28910768Sandreas.hansson@arm.com    // accesses ignore any uncacheable MSHRs, thus we should never
29010768Sandreas.hansson@arm.com    // have targets addded if originally allocated uncacheable
29110768Sandreas.hansson@arm.com    assert(!_isUncacheable);
29210768Sandreas.hansson@arm.com
29311197Sandreas.hansson@arm.com    // potentially re-evaluate whether we should allocate on a fill or
29411197Sandreas.hansson@arm.com    // not
29511197Sandreas.hansson@arm.com    allocOnFill = allocOnFill || alloc_on_fill;
29611197Sandreas.hansson@arm.com
2974903SN/A    // if there's a request already in service for this MSHR, we will
2984903SN/A    // have to defer the new target until after the response if any of
2994903SN/A    // the following are true:
3004903SN/A    // - there are other targets already deferred
3014903SN/A    // - there's a pending invalidate to be applied after the response
3024903SN/A    //   comes back (but before this target is processed)
30311284Sandreas.hansson@arm.com    // - this target requires a writable block and either we're not
30411284Sandreas.hansson@arm.com    //   getting a writable block back or we have already snooped
30511284Sandreas.hansson@arm.com    //   another read request that will downgrade our writable block
30611284Sandreas.hansson@arm.com    //   to non-writable (Shared or Owned)
3074903SN/A    if (inService &&
3089725Sandreas.hansson@arm.com        (!deferredTargets.empty() || hasPostInvalidate() ||
30911284Sandreas.hansson@arm.com         (pkt->needsWritable() &&
31011284Sandreas.hansson@arm.com          (!isPendingModified() || hasPostDowngrade() || isForward)))) {
3114903SN/A        // need to put on deferred list
3127667Ssteve.reinhardt@amd.com        if (hasPostInvalidate())
3137667Ssteve.reinhardt@amd.com            replaceUpgrade(pkt);
3149725Sandreas.hansson@arm.com        deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true);
3154665SN/A    } else {
3165318SN/A        // No request outstanding, or still OK to append to
3175318SN/A        // outstanding request: append to regular target list.  Only
3185318SN/A        // mark pending if current request hasn't been issued yet
3195318SN/A        // (isn't in service).
3209725Sandreas.hansson@arm.com        targets.add(pkt, whenReady, _order, Target::FromCPU, !inService);
3212810SN/A    }
3224665SN/A}
3234665SN/A
3244902SN/Abool
3254902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order)
3264665SN/A{
32710725Sandreas.hansson@arm.com    DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
3289663Suri.wiener@arm.com            pkt->cmdString(), pkt->getAddr(), pkt->getSize());
32911279Sandreas.hansson@arm.com
33011284Sandreas.hansson@arm.com    // when we snoop packets the needsWritable and isInvalidate flags
33111279Sandreas.hansson@arm.com    // should always be the same, however, this assumes that we never
33211279Sandreas.hansson@arm.com    // snoop writes as they are currently not marked as invalidations
33311284Sandreas.hansson@arm.com    panic_if(pkt->needsWritable() != pkt->isInvalidate(),
33411284Sandreas.hansson@arm.com             "%s got snoop %s to addr %#llx where needsWritable, "
33511279Sandreas.hansson@arm.com             "does not match isInvalidate", name(), pkt->cmdString(),
33611279Sandreas.hansson@arm.com             pkt->getAddr());
33711279Sandreas.hansson@arm.com
3384910SN/A    if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
3394903SN/A        // Request has not been issued yet, or it's been issued
3404903SN/A        // locally but is buffered unissued at some downstream cache
3414903SN/A        // which is forwarding us this snoop.  Either way, the packet
3424903SN/A        // we're snooping logically precedes this MSHR's request, so
3434903SN/A        // the snoop has no impact on the MSHR, but must be processed
3444903SN/A        // in the standard way by the cache.  The only exception is
3454903SN/A        // that if we're an L2+ cache buffering an UpgradeReq from a
3464903SN/A        // higher-level cache, and the snoop is invalidating, then our
3474903SN/A        // buffered upgrades must be converted to read exclusives,
3484903SN/A        // since the upper-level cache no longer has a valid copy.
3494903SN/A        // That is, even though the upper-level cache got out on its
3504903SN/A        // local bus first, some other invalidating transaction
3514903SN/A        // reached the global bus before the upgrade did.
35211284Sandreas.hansson@arm.com        if (pkt->needsWritable()) {
3539725Sandreas.hansson@arm.com            targets.replaceUpgrades();
3549725Sandreas.hansson@arm.com            deferredTargets.replaceUpgrades();
3554903SN/A        }
3564903SN/A
3574902SN/A        return false;
3584902SN/A    }
3594665SN/A
3604903SN/A    // From here on down, the request issued by this MSHR logically
3614903SN/A    // precedes the request we're snooping.
36211284Sandreas.hansson@arm.com    if (pkt->needsWritable()) {
3634903SN/A        // snooped request still precedes the re-request we'll have to
3644903SN/A        // issue for deferred targets, if any...
3659725Sandreas.hansson@arm.com        deferredTargets.replaceUpgrades();
3664903SN/A    }
3674903SN/A
3687667Ssteve.reinhardt@amd.com    if (hasPostInvalidate()) {
3694665SN/A        // a prior snoop has already appended an invalidation, so
3704903SN/A        // logically we don't have the block anymore; no need for
3714903SN/A        // further snooping.
3724902SN/A        return true;
3734665SN/A    }
3744665SN/A
37511284Sandreas.hansson@arm.com    if (isPendingModified() || pkt->isInvalidate()) {
3767667Ssteve.reinhardt@amd.com        // We need to save and replay the packet in two cases:
37711284Sandreas.hansson@arm.com        // 1. We're awaiting a writable copy (Modified or Exclusive),
37811284Sandreas.hansson@arm.com        //    so this MSHR is the orgering point, and we need to respond
37911284Sandreas.hansson@arm.com        //    after we receive data.
3807667Ssteve.reinhardt@amd.com        // 2. It's an invalidation (e.g., UpgradeReq), and we need
3817667Ssteve.reinhardt@amd.com        //    to forward the snoop up the hierarchy after the current
3827667Ssteve.reinhardt@amd.com        //    transaction completes.
38310571Sandreas.hansson@arm.com
38411271Sandreas.hansson@arm.com        // Start by determining if we will eventually respond or not,
38511271Sandreas.hansson@arm.com        // matching the conditions checked in Cache::handleSnoop
38611284Sandreas.hansson@arm.com        bool will_respond = isPendingModified() && pkt->needsResponse() &&
38711271Sandreas.hansson@arm.com            pkt->cmd != MemCmd::InvalidateReq;
38811271Sandreas.hansson@arm.com
38911271Sandreas.hansson@arm.com        // The packet we are snooping may be deleted by the time we
39011271Sandreas.hansson@arm.com        // actually process the target, and we consequently need to
39111271Sandreas.hansson@arm.com        // save a copy here. Clear flags and also allocate new data as
39211271Sandreas.hansson@arm.com        // the original packet data storage may have been deleted by
39311271Sandreas.hansson@arm.com        // the time we get to process this packet. In the cases where
39411271Sandreas.hansson@arm.com        // we are not responding after handling the snoop we also need
39511271Sandreas.hansson@arm.com        // to create a copy of the request to be on the safe side. In
39611271Sandreas.hansson@arm.com        // the latter case the cache is responsible for deleting both
39711271Sandreas.hansson@arm.com        // the packet and the request as part of handling the deferred
39811271Sandreas.hansson@arm.com        // snoop.
39911271Sandreas.hansson@arm.com        PacketPtr cp_pkt = will_respond ? new Packet(pkt, true, true) :
40011271Sandreas.hansson@arm.com            new Packet(new Request(*pkt->req), pkt->cmd);
4014670SN/A
40211284Sandreas.hansson@arm.com        if (isPendingModified()) {
40311284Sandreas.hansson@arm.com            // we are the ordering point, and will consequently
40411284Sandreas.hansson@arm.com            // respond, and depending on whether the packet
40511284Sandreas.hansson@arm.com            // needsWritable or not we either pass a Shared line or a
40611284Sandreas.hansson@arm.com            // Modified line
40711284Sandreas.hansson@arm.com            pkt->setCacheResponding();
40811284Sandreas.hansson@arm.com
40911284Sandreas.hansson@arm.com            // inform the cache hierarchy that this cache had the line
41011284Sandreas.hansson@arm.com            // in the Modified state, even if the response is passed
41111284Sandreas.hansson@arm.com            // as Shared (and thus non-writable)
41211284Sandreas.hansson@arm.com            pkt->setResponderHadWritable();
41311284Sandreas.hansson@arm.com
41410821Sandreas.hansson@arm.com            // in the case of an uncacheable request there is no need
41511284Sandreas.hansson@arm.com            // to set the responderHadWritable flag, but since the
41611284Sandreas.hansson@arm.com            // recipient does not care there is no harm in doing so
4174670SN/A        }
41810826Sstephan.diestelhorst@ARM.com        targets.add(cp_pkt, curTick(), _order, Target::FromSnoop,
41911284Sandreas.hansson@arm.com                    downstreamPending && targets.needsWritable);
4204670SN/A
42111284Sandreas.hansson@arm.com        if (pkt->needsWritable()) {
4224670SN/A            // This transaction will take away our pending copy
4237667Ssteve.reinhardt@amd.com            postInvalidate = true;
4244670SN/A        }
4257667Ssteve.reinhardt@amd.com    }
4267667Ssteve.reinhardt@amd.com
42711284Sandreas.hansson@arm.com    if (!pkt->needsWritable() && !pkt->req->isUncacheable()) {
4287667Ssteve.reinhardt@amd.com        // This transaction will get a read-shared copy, downgrading
42911284Sandreas.hansson@arm.com        // our copy if we had a writable one
4307667Ssteve.reinhardt@amd.com        postDowngrade = true;
43111284Sandreas.hansson@arm.com        // make sure that any downstream cache does not respond with a
43211284Sandreas.hansson@arm.com        // writable (and dirty) copy even if it has one, unless it was
43311284Sandreas.hansson@arm.com        // explicitly asked for one
43411284Sandreas.hansson@arm.com        pkt->setHasSharers();
4354667SN/A    }
4364902SN/A
4374902SN/A    return true;
4384665SN/A}
4394665SN/A
4404665SN/A
4414665SN/Abool
4424665SN/AMSHR::promoteDeferredTargets()
4434665SN/A{
4449725Sandreas.hansson@arm.com    assert(targets.empty());
4459725Sandreas.hansson@arm.com    if (deferredTargets.empty()) {
4464665SN/A        return false;
4474665SN/A    }
4484665SN/A
4494903SN/A    // swap targets & deferredTargets lists
4509725Sandreas.hansson@arm.com    std::swap(targets, deferredTargets);
4514903SN/A
4524903SN/A    // clear deferredTargets flags
4539725Sandreas.hansson@arm.com    deferredTargets.resetFlags();
4544903SN/A
4559725Sandreas.hansson@arm.com    order = targets.front().order;
4569725Sandreas.hansson@arm.com    readyTime = std::max(curTick(), targets.front().readyTime);
4574665SN/A
4584665SN/A    return true;
4592810SN/A}
4602810SN/A
4612810SN/A
4622810SN/Avoid
46311284Sandreas.hansson@arm.comMSHR::promoteWritable()
4644668SN/A{
46511284Sandreas.hansson@arm.com    if (deferredTargets.needsWritable &&
46611177Sandreas.hansson@arm.com        !(hasPostInvalidate() || hasPostDowngrade())) {
46711284Sandreas.hansson@arm.com        // We got a writable response, but we have deferred targets
46811284Sandreas.hansson@arm.com        // which are waiting to request a writable copy (not because
4695270SN/A        // of a pending invalidate).  This can happen if the original
47011284Sandreas.hansson@arm.com        // request was for a read-only block, but we got a writable
47111284Sandreas.hansson@arm.com        // response anyway. Since we got the writable copy there's no
47211284Sandreas.hansson@arm.com        // need to defer the targets, so move them up to the regular
47311284Sandreas.hansson@arm.com        // target list.
47411284Sandreas.hansson@arm.com        assert(!targets.needsWritable);
47511284Sandreas.hansson@arm.com        targets.needsWritable = true;
4765318SN/A        // if any of the deferred targets were upper-level cache
4775318SN/A        // requests marked downstreamPending, need to clear that
4785318SN/A        assert(!downstreamPending);  // not pending here anymore
4799725Sandreas.hansson@arm.com        deferredTargets.clearDownstreamPending();
4805270SN/A        // this clears out deferredTargets too
4819725Sandreas.hansson@arm.com        targets.splice(targets.end(), deferredTargets);
4829725Sandreas.hansson@arm.com        deferredTargets.resetFlags();
4835270SN/A    }
4844668SN/A}
4854668SN/A
4864668SN/A
4875314SN/Abool
4885314SN/AMSHR::checkFunctional(PacketPtr pkt)
4895314SN/A{
4905314SN/A    // For printing, we treat the MSHR as a whole as single entity.
4915314SN/A    // For other requests, we iterate over the individual targets
4925314SN/A    // since that's where the actual data lies.
4935314SN/A    if (pkt->isPrint()) {
49410764Sandreas.hansson@arm.com        pkt->checkFunctional(this, blkAddr, isSecure, blkSize, NULL);
4955314SN/A        return false;
4965314SN/A    } else {
4979725Sandreas.hansson@arm.com        return (targets.checkFunctional(pkt) ||
4989725Sandreas.hansson@arm.com                deferredTargets.checkFunctional(pkt));
4995314SN/A    }
5005314SN/A}
5015314SN/A
50211375Sandreas.hansson@arm.combool
50311375Sandreas.hansson@arm.comMSHR::sendPacket(Cache &cache)
50411375Sandreas.hansson@arm.com{
50511375Sandreas.hansson@arm.com    return cache.sendMSHRQueuePacket(this);
50611375Sandreas.hansson@arm.com}
5075314SN/A
5084668SN/Avoid
5095314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
5102810SN/A{
51110725Sandreas.hansson@arm.com    ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
51210764Sandreas.hansson@arm.com             prefix, blkAddr, blkAddr + blkSize - 1,
51310028SGiacomo.Gabrielli@arm.com             isSecure ? "s" : "ns",
5145730SSteve.Reinhardt@amd.com             isForward ? "Forward" : "",
51511197Sandreas.hansson@arm.com             allocOnFill ? "AllocOnFill" : "",
51611284Sandreas.hansson@arm.com             needsWritable() ? "Wrtbl" : "",
5175314SN/A             _isUncacheable ? "Unc" : "",
5185314SN/A             inService ? "InSvc" : "",
5195314SN/A             downstreamPending ? "DwnPend" : "",
5207667Ssteve.reinhardt@amd.com             hasPostInvalidate() ? "PostInv" : "",
5217667Ssteve.reinhardt@amd.com             hasPostDowngrade() ? "PostDowngr" : "");
5222810SN/A
5235314SN/A    ccprintf(os, "%s  Targets:\n", prefix);
5249725Sandreas.hansson@arm.com    targets.print(os, verbosity, prefix + "    ");
5259725Sandreas.hansson@arm.com    if (!deferredTargets.empty()) {
5265314SN/A        ccprintf(os, "%s  Deferred Targets:\n", prefix);
5279725Sandreas.hansson@arm.com        deferredTargets.print(os, verbosity, prefix + "      ");
5282810SN/A    }
5292810SN/A}
5302810SN/A
5319663Suri.wiener@arm.comstd::string
5329663Suri.wiener@arm.comMSHR::print() const
5339663Suri.wiener@arm.com{
5349663Suri.wiener@arm.com    ostringstream str;
5359663Suri.wiener@arm.com    print(str);
5369663Suri.wiener@arm.com    return str.str();
5379663Suri.wiener@arm.com}
538