mshr.cc revision 11286
12810SN/A/*
210764Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015 ARM Limited
39663Suri.wiener@arm.com * All rights reserved.
49663Suri.wiener@arm.com *
59663Suri.wiener@arm.com * The license below extends only to copyright in the software and shall
69663Suri.wiener@arm.com * not be construed as granting a license to any other intellectual
79663Suri.wiener@arm.com * property including but not limited to intellectual property relating
89663Suri.wiener@arm.com * to a hardware implementation of the functionality of the software
99663Suri.wiener@arm.com * licensed hereunder.  You may use the software subject to the license
109663Suri.wiener@arm.com * terms below provided that you ensure that this notice is replicated
119663Suri.wiener@arm.com * unmodified and in its entirety in all distributions of the software,
129663Suri.wiener@arm.com * modified or unmodified, in source code or in binary form.
139663Suri.wiener@arm.com *
142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
157636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
162810SN/A * All rights reserved.
172810SN/A *
182810SN/A * Redistribution and use in source and binary forms, with or without
192810SN/A * modification, are permitted provided that the following conditions are
202810SN/A * met: redistributions of source code must retain the above copyright
212810SN/A * notice, this list of conditions and the following disclaimer;
222810SN/A * redistributions in binary form must reproduce the above copyright
232810SN/A * notice, this list of conditions and the following disclaimer in the
242810SN/A * documentation and/or other materials provided with the distribution;
252810SN/A * neither the name of the copyright holders nor the names of its
262810SN/A * contributors may be used to endorse or promote products derived from
272810SN/A * this software without specific prior written permission.
282810SN/A *
292810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402810SN/A *
412810SN/A * Authors: Erik Hallnor
422810SN/A *          Dave Greene
432810SN/A */
442810SN/A
452810SN/A/**
462810SN/A * @file
472810SN/A * Miss Status and Handling Register (MSHR) definitions.
482810SN/A */
492810SN/A
506216Snate@binkert.org#include <algorithm>
516216Snate@binkert.org#include <cassert>
522810SN/A#include <string>
532810SN/A#include <vector>
542810SN/A
556216Snate@binkert.org#include "base/misc.hh"
566216Snate@binkert.org#include "base/types.hh"
578232Snate@binkert.org#include "debug/Cache.hh"
586216Snate@binkert.org#include "mem/cache/cache.hh"
595338Sstever@gmail.com#include "mem/cache/mshr.hh"
606216Snate@binkert.org#include "sim/core.hh"
612810SN/A
622810SN/Ausing namespace std;
632810SN/A
649725Sandreas.hansson@arm.comMSHR::MSHR() : readyTime(0), _isUncacheable(false), downstreamPending(false),
6511284Sandreas.hansson@arm.com               pendingModified(false),
6610503SCurtis.Dunham@arm.com               postInvalidate(false), postDowngrade(false),
6710764Sandreas.hansson@arm.com               queue(NULL), order(0), blkAddr(0),
6810764Sandreas.hansson@arm.com               blkSize(0), isSecure(false), inService(false),
6911197Sandreas.hansson@arm.com               isForward(false), allocOnFill(false),
7011278Sandreas.hansson@arm.com               data(NULL)
712810SN/A{
722810SN/A}
732810SN/A
744903SN/A
754903SN/AMSHR::TargetList::TargetList()
7611284Sandreas.hansson@arm.com    : needsWritable(false), hasUpgrade(false)
774903SN/A{}
784903SN/A
794903SN/A
804903SN/Ainline void
814908SN/AMSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
825875Ssteve.reinhardt@amd.com                      Counter order, Target::Source source, bool markPending)
834903SN/A{
845875Ssteve.reinhardt@amd.com    if (source != Target::FromSnoop) {
8511284Sandreas.hansson@arm.com        if (pkt->needsWritable()) {
8611284Sandreas.hansson@arm.com            needsWritable = true;
874903SN/A        }
884903SN/A
897669Ssteve.reinhardt@amd.com        // StoreCondReq is effectively an upgrade if it's in an MSHR
907669Ssteve.reinhardt@amd.com        // since it would have been failed already if we didn't have a
917669Ssteve.reinhardt@amd.com        // read-only copy
927669Ssteve.reinhardt@amd.com        if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
934903SN/A            hasUpgrade = true;
944903SN/A        }
955318SN/A    }
964908SN/A
975318SN/A    if (markPending) {
989543Ssascha.bischoff@arm.com        // Iterate over the SenderState stack and see if we find
999543Ssascha.bischoff@arm.com        // an MSHR entry. If we do, set the downstreamPending
1009543Ssascha.bischoff@arm.com        // flag. Otherwise, do nothing.
1019543Ssascha.bischoff@arm.com        MSHR *mshr = pkt->findNextSenderState<MSHR>();
1024908SN/A        if (mshr != NULL) {
1034908SN/A            assert(!mshr->downstreamPending);
1044908SN/A            mshr->downstreamPending = true;
10511083Sandreas.hansson@arm.com        } else {
10611083Sandreas.hansson@arm.com            // No need to clear downstreamPending later
10711083Sandreas.hansson@arm.com            markPending = false;
1084908SN/A        }
1094903SN/A    }
1104903SN/A
11110922Sandreas.hansson@arm.com    emplace_back(pkt, readyTime, order, source, markPending);
1124903SN/A}
1134903SN/A
1144903SN/A
1157667Ssteve.reinhardt@amd.comstatic void
1167667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt)
1177667Ssteve.reinhardt@amd.com{
11811286Sandreas.hansson@arm.com    // remember if the current packet has data allocated
11911286Sandreas.hansson@arm.com    bool has_data = pkt->hasData() || pkt->hasRespData();
12011286Sandreas.hansson@arm.com
1217667Ssteve.reinhardt@amd.com    if (pkt->cmd == MemCmd::UpgradeReq) {
1227667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::ReadExReq;
1237667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
1247667Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
1257667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::SCUpgradeFailReq;
1267667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
1277669Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::StoreCondReq) {
1287669Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::StoreCondFailReq;
1297669Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
1307667Ssteve.reinhardt@amd.com    }
13111286Sandreas.hansson@arm.com
13211286Sandreas.hansson@arm.com    if (!has_data) {
13311286Sandreas.hansson@arm.com        // there is no sensible way of setting the data field if the
13411286Sandreas.hansson@arm.com        // new command actually would carry data
13511286Sandreas.hansson@arm.com        assert(!pkt->hasData());
13611286Sandreas.hansson@arm.com
13711286Sandreas.hansson@arm.com        if (pkt->hasRespData()) {
13811286Sandreas.hansson@arm.com            // we went from a packet that had no data (neither request,
13911286Sandreas.hansson@arm.com            // nor response), to one that does, and therefore we need to
14011286Sandreas.hansson@arm.com            // actually allocate space for the data payload
14111286Sandreas.hansson@arm.com            pkt->allocate();
14211286Sandreas.hansson@arm.com        }
14311286Sandreas.hansson@arm.com    }
1447667Ssteve.reinhardt@amd.com}
1457667Ssteve.reinhardt@amd.com
1467667Ssteve.reinhardt@amd.com
1474903SN/Avoid
1484903SN/AMSHR::TargetList::replaceUpgrades()
1494903SN/A{
1504903SN/A    if (!hasUpgrade)
1514903SN/A        return;
1524903SN/A
15310766Sandreas.hansson@arm.com    for (auto& t : *this) {
15410766Sandreas.hansson@arm.com        replaceUpgrade(t.pkt);
1554903SN/A    }
1564903SN/A
1574903SN/A    hasUpgrade = false;
1584903SN/A}
1594903SN/A
1604903SN/A
1612810SN/Avoid
1624908SN/AMSHR::TargetList::clearDownstreamPending()
1634908SN/A{
16410766Sandreas.hansson@arm.com    for (auto& t : *this) {
16510766Sandreas.hansson@arm.com        if (t.markedPending) {
1669543Ssascha.bischoff@arm.com            // Iterate over the SenderState stack and see if we find
1679543Ssascha.bischoff@arm.com            // an MSHR entry. If we find one, clear the
1689543Ssascha.bischoff@arm.com            // downstreamPending flag by calling
1699543Ssascha.bischoff@arm.com            // clearDownstreamPending(). This recursively clears the
1709543Ssascha.bischoff@arm.com            // downstreamPending flag in all caches this packet has
1719543Ssascha.bischoff@arm.com            // passed through.
17210766Sandreas.hansson@arm.com            MSHR *mshr = t.pkt->findNextSenderState<MSHR>();
1735318SN/A            if (mshr != NULL) {
1745318SN/A                mshr->clearDownstreamPending();
1755318SN/A            }
1764908SN/A        }
1774908SN/A    }
1784908SN/A}
1794908SN/A
1804908SN/A
1814920SN/Abool
1824920SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt)
1834920SN/A{
18410766Sandreas.hansson@arm.com    for (auto& t : *this) {
18510766Sandreas.hansson@arm.com        if (pkt->checkFunctional(t.pkt)) {
1864920SN/A            return true;
1874920SN/A        }
1884920SN/A    }
1894920SN/A
1904920SN/A    return false;
1914920SN/A}
1924920SN/A
1934920SN/A
1944908SN/Avoid
19510766Sandreas.hansson@arm.comMSHR::TargetList::print(std::ostream &os, int verbosity,
19610766Sandreas.hansson@arm.com                        const std::string &prefix) const
1975314SN/A{
19810766Sandreas.hansson@arm.com    for (auto& t : *this) {
1995875Ssteve.reinhardt@amd.com        const char *s;
20010766Sandreas.hansson@arm.com        switch (t.source) {
2018988SAli.Saidi@ARM.com          case Target::FromCPU:
2028988SAli.Saidi@ARM.com            s = "FromCPU";
2038988SAli.Saidi@ARM.com            break;
2048988SAli.Saidi@ARM.com          case Target::FromSnoop:
2058988SAli.Saidi@ARM.com            s = "FromSnoop";
2068988SAli.Saidi@ARM.com            break;
2078988SAli.Saidi@ARM.com          case Target::FromPrefetcher:
2088988SAli.Saidi@ARM.com            s = "FromPrefetcher";
2098988SAli.Saidi@ARM.com            break;
2108988SAli.Saidi@ARM.com          default:
2118988SAli.Saidi@ARM.com            s = "";
2128988SAli.Saidi@ARM.com            break;
2135875Ssteve.reinhardt@amd.com        }
2145875Ssteve.reinhardt@amd.com        ccprintf(os, "%s%s: ", prefix, s);
21510766Sandreas.hansson@arm.com        t.pkt->print(os, verbosity, "");
2165314SN/A    }
2175314SN/A}
2185314SN/A
2195314SN/A
2205314SN/Avoid
22110764Sandreas.hansson@arm.comMSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
22211197Sandreas.hansson@arm.com               Tick when_ready, Counter _order, bool alloc_on_fill)
2232810SN/A{
22410764Sandreas.hansson@arm.com    blkAddr = blk_addr;
22510764Sandreas.hansson@arm.com    blkSize = blk_size;
22610028SGiacomo.Gabrielli@arm.com    isSecure = target->isSecure();
22710764Sandreas.hansson@arm.com    readyTime = when_ready;
2284666SN/A    order = _order;
2294626SN/A    assert(target);
2305730SSteve.Reinhardt@amd.com    isForward = false;
23111197Sandreas.hansson@arm.com    allocOnFill = alloc_on_fill;
2324626SN/A    _isUncacheable = target->req->isUncacheable();
2334626SN/A    inService = false;
2344908SN/A    downstreamPending = false;
2359725Sandreas.hansson@arm.com    assert(targets.isReset());
2364626SN/A    // Don't know of a case where we would allocate a new MSHR for a
2375875Ssteve.reinhardt@amd.com    // snoop (mem-side request), so set source according to request here
2385875Ssteve.reinhardt@amd.com    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
2395875Ssteve.reinhardt@amd.com        Target::FromPrefetcher : Target::FromCPU;
24010764Sandreas.hansson@arm.com    targets.add(target, when_ready, _order, source, true);
2419725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
2424668SN/A    data = NULL;
2432810SN/A}
2442810SN/A
2454908SN/A
2465318SN/Avoid
2475318SN/AMSHR::clearDownstreamPending()
2485318SN/A{
2495318SN/A    assert(downstreamPending);
2505318SN/A    downstreamPending = false;
2515318SN/A    // recursively clear flag on any MSHRs we will be forwarding
2525318SN/A    // responses to
2539725Sandreas.hansson@arm.com    targets.clearDownstreamPending();
2545318SN/A}
2555318SN/A
2564908SN/Abool
25711284Sandreas.hansson@arm.comMSHR::markInService(bool pending_modified_resp)
2584908SN/A{
2594908SN/A    assert(!inService);
2605730SSteve.Reinhardt@amd.com    if (isForwardNoResponse()) {
2614908SN/A        // we just forwarded the request packet & don't expect a
2624908SN/A        // response, so get rid of it
2634908SN/A        assert(getNumTargets() == 1);
2644908SN/A        popTarget();
2654908SN/A        return true;
2664908SN/A    }
26710424Sandreas.hansson@arm.com
2684908SN/A    inService = true;
26911284Sandreas.hansson@arm.com    pendingModified = targets.needsWritable || pending_modified_resp;
2707667Ssteve.reinhardt@amd.com    postInvalidate = postDowngrade = false;
2717667Ssteve.reinhardt@amd.com
2724908SN/A    if (!downstreamPending) {
2734908SN/A        // let upstream caches know that the request has made it to a
2744908SN/A        // level where it's going to get a response
2759725Sandreas.hansson@arm.com        targets.clearDownstreamPending();
2764908SN/A    }
2774908SN/A    return false;
2784908SN/A}
2794908SN/A
2804908SN/A
2812810SN/Avoid
2822810SN/AMSHR::deallocate()
2832810SN/A{
2849725Sandreas.hansson@arm.com    assert(targets.empty());
2859725Sandreas.hansson@arm.com    targets.resetFlags();
2869725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
2872810SN/A    inService = false;
2882810SN/A}
2892810SN/A
2902810SN/A/*
2912810SN/A * Adds a target to an MSHR
2922810SN/A */
2932810SN/Avoid
29411197Sandreas.hansson@arm.comMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order,
29511197Sandreas.hansson@arm.com                     bool alloc_on_fill)
2962810SN/A{
29710768Sandreas.hansson@arm.com    // assume we'd never issue a prefetch when we've got an
29810768Sandreas.hansson@arm.com    // outstanding miss
29910768Sandreas.hansson@arm.com    assert(pkt->cmd != MemCmd::HardPFReq);
30010768Sandreas.hansson@arm.com
30110768Sandreas.hansson@arm.com    // uncacheable accesses always allocate a new MSHR, and cacheable
30210768Sandreas.hansson@arm.com    // accesses ignore any uncacheable MSHRs, thus we should never
30310768Sandreas.hansson@arm.com    // have targets addded if originally allocated uncacheable
30410768Sandreas.hansson@arm.com    assert(!_isUncacheable);
30510768Sandreas.hansson@arm.com
30611197Sandreas.hansson@arm.com    // potentially re-evaluate whether we should allocate on a fill or
30711197Sandreas.hansson@arm.com    // not
30811197Sandreas.hansson@arm.com    allocOnFill = allocOnFill || alloc_on_fill;
30911197Sandreas.hansson@arm.com
3104903SN/A    // if there's a request already in service for this MSHR, we will
3114903SN/A    // have to defer the new target until after the response if any of
3124903SN/A    // the following are true:
3134903SN/A    // - there are other targets already deferred
3144903SN/A    // - there's a pending invalidate to be applied after the response
3154903SN/A    //   comes back (but before this target is processed)
31611284Sandreas.hansson@arm.com    // - this target requires a writable block and either we're not
31711284Sandreas.hansson@arm.com    //   getting a writable block back or we have already snooped
31811284Sandreas.hansson@arm.com    //   another read request that will downgrade our writable block
31911284Sandreas.hansson@arm.com    //   to non-writable (Shared or Owned)
3204903SN/A    if (inService &&
3219725Sandreas.hansson@arm.com        (!deferredTargets.empty() || hasPostInvalidate() ||
32211284Sandreas.hansson@arm.com         (pkt->needsWritable() &&
32311284Sandreas.hansson@arm.com          (!isPendingModified() || hasPostDowngrade() || isForward)))) {
3244903SN/A        // need to put on deferred list
3257667Ssteve.reinhardt@amd.com        if (hasPostInvalidate())
3267667Ssteve.reinhardt@amd.com            replaceUpgrade(pkt);
3279725Sandreas.hansson@arm.com        deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true);
3284665SN/A    } else {
3295318SN/A        // No request outstanding, or still OK to append to
3305318SN/A        // outstanding request: append to regular target list.  Only
3315318SN/A        // mark pending if current request hasn't been issued yet
3325318SN/A        // (isn't in service).
3339725Sandreas.hansson@arm.com        targets.add(pkt, whenReady, _order, Target::FromCPU, !inService);
3342810SN/A    }
3354665SN/A}
3364665SN/A
3374902SN/Abool
3384902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order)
3394665SN/A{
34010725Sandreas.hansson@arm.com    DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
3419663Suri.wiener@arm.com            pkt->cmdString(), pkt->getAddr(), pkt->getSize());
34211279Sandreas.hansson@arm.com
34311284Sandreas.hansson@arm.com    // when we snoop packets the needsWritable and isInvalidate flags
34411279Sandreas.hansson@arm.com    // should always be the same, however, this assumes that we never
34511279Sandreas.hansson@arm.com    // snoop writes as they are currently not marked as invalidations
34611284Sandreas.hansson@arm.com    panic_if(pkt->needsWritable() != pkt->isInvalidate(),
34711284Sandreas.hansson@arm.com             "%s got snoop %s to addr %#llx where needsWritable, "
34811279Sandreas.hansson@arm.com             "does not match isInvalidate", name(), pkt->cmdString(),
34911279Sandreas.hansson@arm.com             pkt->getAddr());
35011279Sandreas.hansson@arm.com
3514910SN/A    if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
3524903SN/A        // Request has not been issued yet, or it's been issued
3534903SN/A        // locally but is buffered unissued at some downstream cache
3544903SN/A        // which is forwarding us this snoop.  Either way, the packet
3554903SN/A        // we're snooping logically precedes this MSHR's request, so
3564903SN/A        // the snoop has no impact on the MSHR, but must be processed
3574903SN/A        // in the standard way by the cache.  The only exception is
3584903SN/A        // that if we're an L2+ cache buffering an UpgradeReq from a
3594903SN/A        // higher-level cache, and the snoop is invalidating, then our
3604903SN/A        // buffered upgrades must be converted to read exclusives,
3614903SN/A        // since the upper-level cache no longer has a valid copy.
3624903SN/A        // That is, even though the upper-level cache got out on its
3634903SN/A        // local bus first, some other invalidating transaction
3644903SN/A        // reached the global bus before the upgrade did.
36511284Sandreas.hansson@arm.com        if (pkt->needsWritable()) {
3669725Sandreas.hansson@arm.com            targets.replaceUpgrades();
3679725Sandreas.hansson@arm.com            deferredTargets.replaceUpgrades();
3684903SN/A        }
3694903SN/A
3704902SN/A        return false;
3714902SN/A    }
3724665SN/A
3734903SN/A    // From here on down, the request issued by this MSHR logically
3744903SN/A    // precedes the request we're snooping.
37511284Sandreas.hansson@arm.com    if (pkt->needsWritable()) {
3764903SN/A        // snooped request still precedes the re-request we'll have to
3774903SN/A        // issue for deferred targets, if any...
3789725Sandreas.hansson@arm.com        deferredTargets.replaceUpgrades();
3794903SN/A    }
3804903SN/A
3817667Ssteve.reinhardt@amd.com    if (hasPostInvalidate()) {
3824665SN/A        // a prior snoop has already appended an invalidation, so
3834903SN/A        // logically we don't have the block anymore; no need for
3844903SN/A        // further snooping.
3854902SN/A        return true;
3864665SN/A    }
3874665SN/A
38811284Sandreas.hansson@arm.com    if (isPendingModified() || pkt->isInvalidate()) {
3897667Ssteve.reinhardt@amd.com        // We need to save and replay the packet in two cases:
39011284Sandreas.hansson@arm.com        // 1. We're awaiting a writable copy (Modified or Exclusive),
39111284Sandreas.hansson@arm.com        //    so this MSHR is the orgering point, and we need to respond
39211284Sandreas.hansson@arm.com        //    after we receive data.
3937667Ssteve.reinhardt@amd.com        // 2. It's an invalidation (e.g., UpgradeReq), and we need
3947667Ssteve.reinhardt@amd.com        //    to forward the snoop up the hierarchy after the current
3957667Ssteve.reinhardt@amd.com        //    transaction completes.
39610571Sandreas.hansson@arm.com
39711271Sandreas.hansson@arm.com        // Start by determining if we will eventually respond or not,
39811271Sandreas.hansson@arm.com        // matching the conditions checked in Cache::handleSnoop
39911284Sandreas.hansson@arm.com        bool will_respond = isPendingModified() && pkt->needsResponse() &&
40011271Sandreas.hansson@arm.com            pkt->cmd != MemCmd::InvalidateReq;
40111271Sandreas.hansson@arm.com
40211271Sandreas.hansson@arm.com        // The packet we are snooping may be deleted by the time we
40311271Sandreas.hansson@arm.com        // actually process the target, and we consequently need to
40411271Sandreas.hansson@arm.com        // save a copy here. Clear flags and also allocate new data as
40511271Sandreas.hansson@arm.com        // the original packet data storage may have been deleted by
40611271Sandreas.hansson@arm.com        // the time we get to process this packet. In the cases where
40711271Sandreas.hansson@arm.com        // we are not responding after handling the snoop we also need
40811271Sandreas.hansson@arm.com        // to create a copy of the request to be on the safe side. In
40911271Sandreas.hansson@arm.com        // the latter case the cache is responsible for deleting both
41011271Sandreas.hansson@arm.com        // the packet and the request as part of handling the deferred
41111271Sandreas.hansson@arm.com        // snoop.
41211271Sandreas.hansson@arm.com        PacketPtr cp_pkt = will_respond ? new Packet(pkt, true, true) :
41311271Sandreas.hansson@arm.com            new Packet(new Request(*pkt->req), pkt->cmd);
4144670SN/A
41511284Sandreas.hansson@arm.com        if (isPendingModified()) {
41611284Sandreas.hansson@arm.com            // we are the ordering point, and will consequently
41711284Sandreas.hansson@arm.com            // respond, and depending on whether the packet
41811284Sandreas.hansson@arm.com            // needsWritable or not we either pass a Shared line or a
41911284Sandreas.hansson@arm.com            // Modified line
42011284Sandreas.hansson@arm.com            pkt->setCacheResponding();
42111284Sandreas.hansson@arm.com
42211284Sandreas.hansson@arm.com            // inform the cache hierarchy that this cache had the line
42311284Sandreas.hansson@arm.com            // in the Modified state, even if the response is passed
42411284Sandreas.hansson@arm.com            // as Shared (and thus non-writable)
42511284Sandreas.hansson@arm.com            pkt->setResponderHadWritable();
42611284Sandreas.hansson@arm.com
42710821Sandreas.hansson@arm.com            // in the case of an uncacheable request there is no need
42811284Sandreas.hansson@arm.com            // to set the responderHadWritable flag, but since the
42911284Sandreas.hansson@arm.com            // recipient does not care there is no harm in doing so
4304670SN/A        }
43110826Sstephan.diestelhorst@ARM.com        targets.add(cp_pkt, curTick(), _order, Target::FromSnoop,
43211284Sandreas.hansson@arm.com                    downstreamPending && targets.needsWritable);
4334670SN/A
43411284Sandreas.hansson@arm.com        if (pkt->needsWritable()) {
4354670SN/A            // This transaction will take away our pending copy
4367667Ssteve.reinhardt@amd.com            postInvalidate = true;
4374670SN/A        }
4387667Ssteve.reinhardt@amd.com    }
4397667Ssteve.reinhardt@amd.com
44011284Sandreas.hansson@arm.com    if (!pkt->needsWritable() && !pkt->req->isUncacheable()) {
4417667Ssteve.reinhardt@amd.com        // This transaction will get a read-shared copy, downgrading
44211284Sandreas.hansson@arm.com        // our copy if we had a writable one
4437667Ssteve.reinhardt@amd.com        postDowngrade = true;
44411284Sandreas.hansson@arm.com        // make sure that any downstream cache does not respond with a
44511284Sandreas.hansson@arm.com        // writable (and dirty) copy even if it has one, unless it was
44611284Sandreas.hansson@arm.com        // explicitly asked for one
44711284Sandreas.hansson@arm.com        pkt->setHasSharers();
4484667SN/A    }
4494902SN/A
4504902SN/A    return true;
4514665SN/A}
4524665SN/A
4534665SN/A
4544665SN/Abool
4554665SN/AMSHR::promoteDeferredTargets()
4564665SN/A{
4579725Sandreas.hansson@arm.com    assert(targets.empty());
4589725Sandreas.hansson@arm.com    if (deferredTargets.empty()) {
4594665SN/A        return false;
4604665SN/A    }
4614665SN/A
4624903SN/A    // swap targets & deferredTargets lists
4639725Sandreas.hansson@arm.com    std::swap(targets, deferredTargets);
4644903SN/A
4654903SN/A    // clear deferredTargets flags
4669725Sandreas.hansson@arm.com    deferredTargets.resetFlags();
4674903SN/A
4689725Sandreas.hansson@arm.com    order = targets.front().order;
4699725Sandreas.hansson@arm.com    readyTime = std::max(curTick(), targets.front().readyTime);
4704665SN/A
4714665SN/A    return true;
4722810SN/A}
4732810SN/A
4742810SN/A
4752810SN/Avoid
47611284Sandreas.hansson@arm.comMSHR::promoteWritable()
4774668SN/A{
47811284Sandreas.hansson@arm.com    if (deferredTargets.needsWritable &&
47911177Sandreas.hansson@arm.com        !(hasPostInvalidate() || hasPostDowngrade())) {
48011284Sandreas.hansson@arm.com        // We got a writable response, but we have deferred targets
48111284Sandreas.hansson@arm.com        // which are waiting to request a writable copy (not because
4825270SN/A        // of a pending invalidate).  This can happen if the original
48311284Sandreas.hansson@arm.com        // request was for a read-only block, but we got a writable
48411284Sandreas.hansson@arm.com        // response anyway. Since we got the writable copy there's no
48511284Sandreas.hansson@arm.com        // need to defer the targets, so move them up to the regular
48611284Sandreas.hansson@arm.com        // target list.
48711284Sandreas.hansson@arm.com        assert(!targets.needsWritable);
48811284Sandreas.hansson@arm.com        targets.needsWritable = true;
4895318SN/A        // if any of the deferred targets were upper-level cache
4905318SN/A        // requests marked downstreamPending, need to clear that
4915318SN/A        assert(!downstreamPending);  // not pending here anymore
4929725Sandreas.hansson@arm.com        deferredTargets.clearDownstreamPending();
4935270SN/A        // this clears out deferredTargets too
4949725Sandreas.hansson@arm.com        targets.splice(targets.end(), deferredTargets);
4959725Sandreas.hansson@arm.com        deferredTargets.resetFlags();
4965270SN/A    }
4974668SN/A}
4984668SN/A
4994668SN/A
5005314SN/Abool
5015314SN/AMSHR::checkFunctional(PacketPtr pkt)
5025314SN/A{
5035314SN/A    // For printing, we treat the MSHR as a whole as single entity.
5045314SN/A    // For other requests, we iterate over the individual targets
5055314SN/A    // since that's where the actual data lies.
5065314SN/A    if (pkt->isPrint()) {
50710764Sandreas.hansson@arm.com        pkt->checkFunctional(this, blkAddr, isSecure, blkSize, NULL);
5085314SN/A        return false;
5095314SN/A    } else {
5109725Sandreas.hansson@arm.com        return (targets.checkFunctional(pkt) ||
5119725Sandreas.hansson@arm.com                deferredTargets.checkFunctional(pkt));
5125314SN/A    }
5135314SN/A}
5145314SN/A
5155314SN/A
5164668SN/Avoid
5175314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
5182810SN/A{
51910725Sandreas.hansson@arm.com    ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
52010764Sandreas.hansson@arm.com             prefix, blkAddr, blkAddr + blkSize - 1,
52110028SGiacomo.Gabrielli@arm.com             isSecure ? "s" : "ns",
5225730SSteve.Reinhardt@amd.com             isForward ? "Forward" : "",
52311197Sandreas.hansson@arm.com             allocOnFill ? "AllocOnFill" : "",
5245730SSteve.Reinhardt@amd.com             isForwardNoResponse() ? "ForwNoResp" : "",
52511284Sandreas.hansson@arm.com             needsWritable() ? "Wrtbl" : "",
5265314SN/A             _isUncacheable ? "Unc" : "",
5275314SN/A             inService ? "InSvc" : "",
5285314SN/A             downstreamPending ? "DwnPend" : "",
5297667Ssteve.reinhardt@amd.com             hasPostInvalidate() ? "PostInv" : "",
5307667Ssteve.reinhardt@amd.com             hasPostDowngrade() ? "PostDowngr" : "");
5312810SN/A
5325314SN/A    ccprintf(os, "%s  Targets:\n", prefix);
5339725Sandreas.hansson@arm.com    targets.print(os, verbosity, prefix + "    ");
5349725Sandreas.hansson@arm.com    if (!deferredTargets.empty()) {
5355314SN/A        ccprintf(os, "%s  Deferred Targets:\n", prefix);
5369725Sandreas.hansson@arm.com        deferredTargets.print(os, verbosity, prefix + "      ");
5372810SN/A    }
5382810SN/A}
5392810SN/A
5409663Suri.wiener@arm.comstd::string
5419663Suri.wiener@arm.comMSHR::print() const
5429663Suri.wiener@arm.com{
5439663Suri.wiener@arm.com    ostringstream str;
5449663Suri.wiener@arm.com    print(str);
5459663Suri.wiener@arm.com    return str.str();
5469663Suri.wiener@arm.com}
547