mshr.cc revision 11284
17405SAli.Saidi@ARM.com/*
27405SAli.Saidi@ARM.com * Copyright (c) 2012-2013, 2015 ARM Limited
37405SAli.Saidi@ARM.com * All rights reserved.
47405SAli.Saidi@ARM.com *
57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall
67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual
77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating
87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software
97405SAli.Saidi@ARM.com * licensed hereunder.  You may use the software subject to the license
107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated
117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software,
127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form.
137405SAli.Saidi@ARM.com *
147405SAli.Saidi@ARM.com * Copyright (c) 2002-2005 The Regents of The University of Michigan
157405SAli.Saidi@ARM.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
167405SAli.Saidi@ARM.com * All rights reserved.
177405SAli.Saidi@ARM.com *
187405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without
197405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are
207405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright
217405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer;
227405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright
237405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the
247405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution;
257405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its
267405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from
277405SAli.Saidi@ARM.com * this software without specific prior written permission.
287405SAli.Saidi@ARM.com *
297405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
307405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
317405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
327405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
337405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
347405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
357405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
367405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
377405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
387405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
397405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
407405SAli.Saidi@ARM.com *
417405SAli.Saidi@ARM.com * Authors: Erik Hallnor
428232Snate@binkert.org *          Dave Greene
438232Snate@binkert.org */
447678Sgblack@eecs.umich.edu
458059SAli.Saidi@ARM.com/**
467405SAli.Saidi@ARM.com * @file
477405SAli.Saidi@ARM.com * Miss Status and Handling Register (MSHR) definitions.
487405SAli.Saidi@ARM.com */
497405SAli.Saidi@ARM.com
507427Sgblack@eecs.umich.edu#include <algorithm>
517427Sgblack@eecs.umich.edu#include <cassert>
527427Sgblack@eecs.umich.edu#include <string>
537427Sgblack@eecs.umich.edu#include <vector>
547427Sgblack@eecs.umich.edu
557427Sgblack@eecs.umich.edu#include "base/misc.hh"
567427Sgblack@eecs.umich.edu#include "base/types.hh"
577427Sgblack@eecs.umich.edu#include "debug/Cache.hh"
587427Sgblack@eecs.umich.edu#include "mem/cache/cache.hh"
597427Sgblack@eecs.umich.edu#include "mem/cache/mshr.hh"
607427Sgblack@eecs.umich.edu#include "sim/core.hh"
617427Sgblack@eecs.umich.edu
627604SGene.Wu@arm.comusing namespace std;
637427Sgblack@eecs.umich.edu
647427Sgblack@eecs.umich.eduMSHR::MSHR() : readyTime(0), _isUncacheable(false), downstreamPending(false),
657427Sgblack@eecs.umich.edu               pendingModified(false),
667427Sgblack@eecs.umich.edu               postInvalidate(false), postDowngrade(false),
677427Sgblack@eecs.umich.edu               queue(NULL), order(0), blkAddr(0),
687427Sgblack@eecs.umich.edu               blkSize(0), isSecure(false), inService(false),
697427Sgblack@eecs.umich.edu               isForward(false), allocOnFill(false),
707427Sgblack@eecs.umich.edu               data(NULL)
717427Sgblack@eecs.umich.edu{
727427Sgblack@eecs.umich.edu}
737427Sgblack@eecs.umich.edu
747427Sgblack@eecs.umich.edu
757427Sgblack@eecs.umich.eduMSHR::TargetList::TargetList()
767427Sgblack@eecs.umich.edu    : needsWritable(false), hasUpgrade(false)
777427Sgblack@eecs.umich.edu{}
787427Sgblack@eecs.umich.edu
797427Sgblack@eecs.umich.edu
807427Sgblack@eecs.umich.eduinline void
817645Sali.saidi@arm.comMSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
827645Sali.saidi@arm.com                      Counter order, Target::Source source, bool markPending)
837645Sali.saidi@arm.com{
847645Sali.saidi@arm.com    if (source != Target::FromSnoop) {
857645Sali.saidi@arm.com        if (pkt->needsWritable()) {
867427Sgblack@eecs.umich.edu            needsWritable = true;
877427Sgblack@eecs.umich.edu        }
887427Sgblack@eecs.umich.edu
897427Sgblack@eecs.umich.edu        // StoreCondReq is effectively an upgrade if it's in an MSHR
907427Sgblack@eecs.umich.edu        // since it would have been failed already if we didn't have a
917427Sgblack@eecs.umich.edu        // read-only copy
927427Sgblack@eecs.umich.edu        if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
937427Sgblack@eecs.umich.edu            hasUpgrade = true;
947427Sgblack@eecs.umich.edu        }
957427Sgblack@eecs.umich.edu    }
967427Sgblack@eecs.umich.edu
977427Sgblack@eecs.umich.edu    if (markPending) {
987427Sgblack@eecs.umich.edu        // Iterate over the SenderState stack and see if we find
997427Sgblack@eecs.umich.edu        // an MSHR entry. If we do, set the downstreamPending
1007427Sgblack@eecs.umich.edu        // flag. Otherwise, do nothing.
1017427Sgblack@eecs.umich.edu        MSHR *mshr = pkt->findNextSenderState<MSHR>();
1027427Sgblack@eecs.umich.edu        if (mshr != NULL) {
1037427Sgblack@eecs.umich.edu            assert(!mshr->downstreamPending);
1047427Sgblack@eecs.umich.edu            mshr->downstreamPending = true;
1057427Sgblack@eecs.umich.edu        } else {
1067427Sgblack@eecs.umich.edu            // No need to clear downstreamPending later
1077427Sgblack@eecs.umich.edu            markPending = false;
1087427Sgblack@eecs.umich.edu        }
1097427Sgblack@eecs.umich.edu    }
1107427Sgblack@eecs.umich.edu
1117427Sgblack@eecs.umich.edu    emplace_back(pkt, readyTime, order, source, markPending);
1127427Sgblack@eecs.umich.edu}
1137427Sgblack@eecs.umich.edu
1147436Sdam.sunwoo@arm.com
1157436Sdam.sunwoo@arm.comstatic void
1167436Sdam.sunwoo@arm.comreplaceUpgrade(PacketPtr pkt)
1177436Sdam.sunwoo@arm.com{
1187436Sdam.sunwoo@arm.com    if (pkt->cmd == MemCmd::UpgradeReq) {
1197436Sdam.sunwoo@arm.com        pkt->cmd = MemCmd::ReadExReq;
1207436Sdam.sunwoo@arm.com        DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
1217436Sdam.sunwoo@arm.com    } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
1227436Sdam.sunwoo@arm.com        pkt->cmd = MemCmd::SCUpgradeFailReq;
1237436Sdam.sunwoo@arm.com        DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
1247436Sdam.sunwoo@arm.com    } else if (pkt->cmd == MemCmd::StoreCondReq) {
1257436Sdam.sunwoo@arm.com        pkt->cmd = MemCmd::StoreCondFailReq;
1267436Sdam.sunwoo@arm.com        DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
1277436Sdam.sunwoo@arm.com    }
1287436Sdam.sunwoo@arm.com}
1297436Sdam.sunwoo@arm.com
1307436Sdam.sunwoo@arm.com
1317436Sdam.sunwoo@arm.comvoid
1327436Sdam.sunwoo@arm.comMSHR::TargetList::replaceUpgrades()
1337436Sdam.sunwoo@arm.com{
1347436Sdam.sunwoo@arm.com    if (!hasUpgrade)
1357436Sdam.sunwoo@arm.com        return;
1367436Sdam.sunwoo@arm.com
1377436Sdam.sunwoo@arm.com    for (auto& t : *this) {
1387436Sdam.sunwoo@arm.com        replaceUpgrade(t.pkt);
1397436Sdam.sunwoo@arm.com    }
1407436Sdam.sunwoo@arm.com
1417436Sdam.sunwoo@arm.com    hasUpgrade = false;
1427436Sdam.sunwoo@arm.com}
1437436Sdam.sunwoo@arm.com
1447436Sdam.sunwoo@arm.com
1457436Sdam.sunwoo@arm.comvoid
1467644Sali.saidi@arm.comMSHR::TargetList::clearDownstreamPending()
1477644Sali.saidi@arm.com{
1488147SAli.Saidi@ARM.com    for (auto& t : *this) {
1498147SAli.Saidi@ARM.com        if (t.markedPending) {
1508147SAli.Saidi@ARM.com            // Iterate over the SenderState stack and see if we find
1518147SAli.Saidi@ARM.com            // an MSHR entry. If we find one, clear the
1528147SAli.Saidi@ARM.com            // downstreamPending flag by calling
1538147SAli.Saidi@ARM.com            // clearDownstreamPending(). This recursively clears the
1548147SAli.Saidi@ARM.com            // downstreamPending flag in all caches this packet has
1558147SAli.Saidi@ARM.com            // passed through.
1568147SAli.Saidi@ARM.com            MSHR *mshr = t.pkt->findNextSenderState<MSHR>();
1578147SAli.Saidi@ARM.com            if (mshr != NULL) {
1587427Sgblack@eecs.umich.edu                mshr->clearDownstreamPending();
1597427Sgblack@eecs.umich.edu            }
1607427Sgblack@eecs.umich.edu        }
1617405SAli.Saidi@ARM.com    }
1627405SAli.Saidi@ARM.com}
1637405SAli.Saidi@ARM.com
1647405SAli.Saidi@ARM.com
1657614Sminkyu.jeong@arm.combool
1667614Sminkyu.jeong@arm.comMSHR::TargetList::checkFunctional(PacketPtr pkt)
1677614Sminkyu.jeong@arm.com{
1687614Sminkyu.jeong@arm.com    for (auto& t : *this) {
1697614Sminkyu.jeong@arm.com        if (pkt->checkFunctional(t.pkt)) {
1707614Sminkyu.jeong@arm.com            return true;
1717614Sminkyu.jeong@arm.com        }
1727614Sminkyu.jeong@arm.com    }
1737614Sminkyu.jeong@arm.com
1747614Sminkyu.jeong@arm.com    return false;
1757614Sminkyu.jeong@arm.com}
1767405SAli.Saidi@ARM.com
1777405SAli.Saidi@ARM.com
1787405SAli.Saidi@ARM.comvoid
1797405SAli.Saidi@ARM.comMSHR::TargetList::print(std::ostream &os, int verbosity,
1807405SAli.Saidi@ARM.com                        const std::string &prefix) const
1817405SAli.Saidi@ARM.com{
1827405SAli.Saidi@ARM.com    for (auto& t : *this) {
1837405SAli.Saidi@ARM.com        const char *s;
1847720Sgblack@eecs.umich.edu        switch (t.source) {
1857720Sgblack@eecs.umich.edu          case Target::FromCPU:
1867720Sgblack@eecs.umich.edu            s = "FromCPU";
1877405SAli.Saidi@ARM.com            break;
1887405SAli.Saidi@ARM.com          case Target::FromSnoop:
1897757SAli.Saidi@ARM.com            s = "FromSnoop";
1907405SAli.Saidi@ARM.com            break;
1917405SAli.Saidi@ARM.com          case Target::FromPrefetcher:
1927757SAli.Saidi@ARM.com            s = "FromPrefetcher";
1937405SAli.Saidi@ARM.com            break;
1947405SAli.Saidi@ARM.com          default:
1957731SAli.Saidi@ARM.com            s = "";
1967405SAli.Saidi@ARM.com            break;
1977405SAli.Saidi@ARM.com        }
1987731SAli.Saidi@ARM.com        ccprintf(os, "%s%s: ", prefix, s);
1997405SAli.Saidi@ARM.com        t.pkt->print(os, verbosity, "");
2007405SAli.Saidi@ARM.com    }
2017405SAli.Saidi@ARM.com}
2027588SAli.Saidi@arm.com
2037588SAli.Saidi@arm.com
2047588SAli.Saidi@arm.comvoid
2057583SAli.Saidi@arm.comMSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
2067583SAli.Saidi@arm.com               Tick when_ready, Counter _order, bool alloc_on_fill)
2077583SAli.Saidi@arm.com{
2087583SAli.Saidi@arm.com    blkAddr = blk_addr;
2097583SAli.Saidi@arm.com    blkSize = blk_size;
2107583SAli.Saidi@arm.com    isSecure = target->isSecure();
2117583SAli.Saidi@arm.com    readyTime = when_ready;
2127583SAli.Saidi@arm.com    order = _order;
2137583SAli.Saidi@arm.com    assert(target);
2147583SAli.Saidi@arm.com    isForward = false;
2157583SAli.Saidi@arm.com    allocOnFill = alloc_on_fill;
2167583SAli.Saidi@arm.com    _isUncacheable = target->req->isUncacheable();
2177583SAli.Saidi@arm.com    inService = false;
2187783SGiacomo.Gabrielli@arm.com    downstreamPending = false;
2197783SGiacomo.Gabrielli@arm.com    assert(targets.isReset());
2207783SGiacomo.Gabrielli@arm.com    // Don't know of a case where we would allocate a new MSHR for a
2217783SGiacomo.Gabrielli@arm.com    // snoop (mem-side request), so set source according to request here
2227405SAli.Saidi@ARM.com    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
2237405SAli.Saidi@ARM.com        Target::FromPrefetcher : Target::FromCPU;
2247405SAli.Saidi@ARM.com    targets.add(target, when_ready, _order, source, true);
2257405SAli.Saidi@ARM.com    assert(deferredTargets.isReset());
2267405SAli.Saidi@ARM.com    data = NULL;
2277405SAli.Saidi@ARM.com}
2287405SAli.Saidi@ARM.com
2297405SAli.Saidi@ARM.com
2307614Sminkyu.jeong@arm.comvoid
2317614Sminkyu.jeong@arm.comMSHR::clearDownstreamPending()
2327614Sminkyu.jeong@arm.com{
2337614Sminkyu.jeong@arm.com    assert(downstreamPending);
2347614Sminkyu.jeong@arm.com    downstreamPending = false;
2357614Sminkyu.jeong@arm.com    // recursively clear flag on any MSHRs we will be forwarding
2367614Sminkyu.jeong@arm.com    // responses to
2377614Sminkyu.jeong@arm.com    targets.clearDownstreamPending();
2387614Sminkyu.jeong@arm.com}
2397614Sminkyu.jeong@arm.com
2407405SAli.Saidi@ARM.combool
2417405SAli.Saidi@ARM.comMSHR::markInService(bool pending_modified_resp)
2427405SAli.Saidi@ARM.com{
2437405SAli.Saidi@ARM.com    assert(!inService);
2447405SAli.Saidi@ARM.com    if (isForwardNoResponse()) {
2457749SAli.Saidi@ARM.com        // we just forwarded the request packet & don't expect a
2467405SAli.Saidi@ARM.com        // response, so get rid of it
2477405SAli.Saidi@ARM.com        assert(getNumTargets() == 1);
2487405SAli.Saidi@ARM.com        popTarget();
2497749SAli.Saidi@ARM.com        return true;
2507749SAli.Saidi@ARM.com    }
2517749SAli.Saidi@ARM.com
2527749SAli.Saidi@ARM.com    inService = true;
2537405SAli.Saidi@ARM.com    pendingModified = targets.needsWritable || pending_modified_resp;
2547749SAli.Saidi@ARM.com    postInvalidate = postDowngrade = false;
2557749SAli.Saidi@ARM.com
2567749SAli.Saidi@ARM.com    if (!downstreamPending) {
2577749SAli.Saidi@ARM.com        // let upstream caches know that the request has made it to a
2587749SAli.Saidi@ARM.com        // level where it's going to get a response
2597614Sminkyu.jeong@arm.com        targets.clearDownstreamPending();
2607614Sminkyu.jeong@arm.com    }
2617720Sgblack@eecs.umich.edu    return false;
2627720Sgblack@eecs.umich.edu}
2637720Sgblack@eecs.umich.edu
2647720Sgblack@eecs.umich.edu
2657408Sgblack@eecs.umich.eduvoid
2667405SAli.Saidi@ARM.comMSHR::deallocate()
2677405SAli.Saidi@ARM.com{
2687405SAli.Saidi@ARM.com    assert(targets.empty());
2697408Sgblack@eecs.umich.edu    targets.resetFlags();
2707408Sgblack@eecs.umich.edu    assert(deferredTargets.isReset());
2717408Sgblack@eecs.umich.edu    inService = false;
2727408Sgblack@eecs.umich.edu}
2738206SWilliam.Wang@arm.com
2748206SWilliam.Wang@arm.com/*
2758206SWilliam.Wang@arm.com * Adds a target to an MSHR
2768206SWilliam.Wang@arm.com */
2778206SWilliam.Wang@arm.comvoid
2788206SWilliam.Wang@arm.comMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order,
2798206SWilliam.Wang@arm.com                     bool alloc_on_fill)
2808206SWilliam.Wang@arm.com{
2818206SWilliam.Wang@arm.com    // assume we'd never issue a prefetch when we've got an
2828206SWilliam.Wang@arm.com    // outstanding miss
2838206SWilliam.Wang@arm.com    assert(pkt->cmd != MemCmd::HardPFReq);
2847408Sgblack@eecs.umich.edu
2857408Sgblack@eecs.umich.edu    // uncacheable accesses always allocate a new MSHR, and cacheable
2867408Sgblack@eecs.umich.edu    // accesses ignore any uncacheable MSHRs, thus we should never
2877731SAli.Saidi@ARM.com    // have targets addded if originally allocated uncacheable
2888206SWilliam.Wang@arm.com    assert(!_isUncacheable);
2897408Sgblack@eecs.umich.edu
2907408Sgblack@eecs.umich.edu    // potentially re-evaluate whether we should allocate on a fill or
2917408Sgblack@eecs.umich.edu    // not
2927408Sgblack@eecs.umich.edu    allocOnFill = allocOnFill || alloc_on_fill;
2937408Sgblack@eecs.umich.edu
2947408Sgblack@eecs.umich.edu    // if there's a request already in service for this MSHR, we will
2957408Sgblack@eecs.umich.edu    // have to defer the new target until after the response if any of
2967408Sgblack@eecs.umich.edu    // the following are true:
2977408Sgblack@eecs.umich.edu    // - there are other targets already deferred
2987408Sgblack@eecs.umich.edu    // - there's a pending invalidate to be applied after the response
2997408Sgblack@eecs.umich.edu    //   comes back (but before this target is processed)
3007408Sgblack@eecs.umich.edu    // - this target requires a writable block and either we're not
3017408Sgblack@eecs.umich.edu    //   getting a writable block back or we have already snooped
3027408Sgblack@eecs.umich.edu    //   another read request that will downgrade our writable block
3037408Sgblack@eecs.umich.edu    //   to non-writable (Shared or Owned)
3047408Sgblack@eecs.umich.edu    if (inService &&
3057408Sgblack@eecs.umich.edu        (!deferredTargets.empty() || hasPostInvalidate() ||
3067408Sgblack@eecs.umich.edu         (pkt->needsWritable() &&
3077408Sgblack@eecs.umich.edu          (!isPendingModified() || hasPostDowngrade() || isForward)))) {
3087408Sgblack@eecs.umich.edu        // need to put on deferred list
3097408Sgblack@eecs.umich.edu        if (hasPostInvalidate())
3107408Sgblack@eecs.umich.edu            replaceUpgrade(pkt);
3117408Sgblack@eecs.umich.edu        deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true);
3127408Sgblack@eecs.umich.edu    } else {
3137408Sgblack@eecs.umich.edu        // No request outstanding, or still OK to append to
3147783SGiacomo.Gabrielli@arm.com        // outstanding request: append to regular target list.  Only
3157783SGiacomo.Gabrielli@arm.com        // mark pending if current request hasn't been issued yet
3167783SGiacomo.Gabrielli@arm.com        // (isn't in service).
3177783SGiacomo.Gabrielli@arm.com        targets.add(pkt, whenReady, _order, Target::FromCPU, !inService);
3187783SGiacomo.Gabrielli@arm.com    }
3197783SGiacomo.Gabrielli@arm.com}
3207783SGiacomo.Gabrielli@arm.com
3217783SGiacomo.Gabrielli@arm.combool
3227783SGiacomo.Gabrielli@arm.comMSHR::handleSnoop(PacketPtr pkt, Counter _order)
3237783SGiacomo.Gabrielli@arm.com{
3247783SGiacomo.Gabrielli@arm.com    DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
3257783SGiacomo.Gabrielli@arm.com            pkt->cmdString(), pkt->getAddr(), pkt->getSize());
3267408Sgblack@eecs.umich.edu
3277408Sgblack@eecs.umich.edu    // when we snoop packets the needsWritable and isInvalidate flags
3288206SWilliam.Wang@arm.com    // should always be the same, however, this assumes that we never
3298206SWilliam.Wang@arm.com    // snoop writes as they are currently not marked as invalidations
3307408Sgblack@eecs.umich.edu    panic_if(pkt->needsWritable() != pkt->isInvalidate(),
3317408Sgblack@eecs.umich.edu             "%s got snoop %s to addr %#llx where needsWritable, "
3327408Sgblack@eecs.umich.edu             "does not match isInvalidate", name(), pkt->cmdString(),
3337408Sgblack@eecs.umich.edu             pkt->getAddr());
3347408Sgblack@eecs.umich.edu
3357408Sgblack@eecs.umich.edu    if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
3367408Sgblack@eecs.umich.edu        // Request has not been issued yet, or it's been issued
3377408Sgblack@eecs.umich.edu        // locally but is buffered unissued at some downstream cache
3387408Sgblack@eecs.umich.edu        // which is forwarding us this snoop.  Either way, the packet
3397408Sgblack@eecs.umich.edu        // we're snooping logically precedes this MSHR's request, so
3407408Sgblack@eecs.umich.edu        // the snoop has no impact on the MSHR, but must be processed
3417408Sgblack@eecs.umich.edu        // in the standard way by the cache.  The only exception is
3427749SAli.Saidi@ARM.com        // that if we're an L2+ cache buffering an UpgradeReq from a
3437749SAli.Saidi@ARM.com        // higher-level cache, and the snoop is invalidating, then our
3447408Sgblack@eecs.umich.edu        // buffered upgrades must be converted to read exclusives,
3457408Sgblack@eecs.umich.edu        // since the upper-level cache no longer has a valid copy.
3467408Sgblack@eecs.umich.edu        // That is, even though the upper-level cache got out on its
3477408Sgblack@eecs.umich.edu        // local bus first, some other invalidating transaction
3487408Sgblack@eecs.umich.edu        // reached the global bus before the upgrade did.
3497408Sgblack@eecs.umich.edu        if (pkt->needsWritable()) {
3507408Sgblack@eecs.umich.edu            targets.replaceUpgrades();
3517408Sgblack@eecs.umich.edu            deferredTargets.replaceUpgrades();
3527408Sgblack@eecs.umich.edu        }
3537408Sgblack@eecs.umich.edu
3547731SAli.Saidi@ARM.com        return false;
3557408Sgblack@eecs.umich.edu    }
3567408Sgblack@eecs.umich.edu
3577408Sgblack@eecs.umich.edu    // From here on down, the request issued by this MSHR logically
3587408Sgblack@eecs.umich.edu    // precedes the request we're snooping.
3597408Sgblack@eecs.umich.edu    if (pkt->needsWritable()) {
3607408Sgblack@eecs.umich.edu        // snooped request still precedes the re-request we'll have to
3617408Sgblack@eecs.umich.edu        // issue for deferred targets, if any...
3627408Sgblack@eecs.umich.edu        deferredTargets.replaceUpgrades();
3637408Sgblack@eecs.umich.edu    }
3647408Sgblack@eecs.umich.edu
3657408Sgblack@eecs.umich.edu    if (hasPostInvalidate()) {
3667731SAli.Saidi@ARM.com        // a prior snoop has already appended an invalidation, so
3677408Sgblack@eecs.umich.edu        // logically we don't have the block anymore; no need for
3687408Sgblack@eecs.umich.edu        // further snooping.
3697408Sgblack@eecs.umich.edu        return true;
3707408Sgblack@eecs.umich.edu    }
3717408Sgblack@eecs.umich.edu
3727408Sgblack@eecs.umich.edu    if (isPendingModified() || pkt->isInvalidate()) {
3737408Sgblack@eecs.umich.edu        // We need to save and replay the packet in two cases:
3747731SAli.Saidi@ARM.com        // 1. We're awaiting a writable copy (Modified or Exclusive),
3757408Sgblack@eecs.umich.edu        //    so this MSHR is the orgering point, and we need to respond
3767408Sgblack@eecs.umich.edu        //    after we receive data.
3777408Sgblack@eecs.umich.edu        // 2. It's an invalidation (e.g., UpgradeReq), and we need
3787408Sgblack@eecs.umich.edu        //    to forward the snoop up the hierarchy after the current
3797408Sgblack@eecs.umich.edu        //    transaction completes.
3807731SAli.Saidi@ARM.com
3817408Sgblack@eecs.umich.edu        // Start by determining if we will eventually respond or not,
3827408Sgblack@eecs.umich.edu        // matching the conditions checked in Cache::handleSnoop
3837408Sgblack@eecs.umich.edu        bool will_respond = isPendingModified() && pkt->needsResponse() &&
3847408Sgblack@eecs.umich.edu            pkt->cmd != MemCmd::InvalidateReq;
3857408Sgblack@eecs.umich.edu
3867408Sgblack@eecs.umich.edu        // The packet we are snooping may be deleted by the time we
3877408Sgblack@eecs.umich.edu        // actually process the target, and we consequently need to
3887408Sgblack@eecs.umich.edu        // save a copy here. Clear flags and also allocate new data as
3897408Sgblack@eecs.umich.edu        // the original packet data storage may have been deleted by
3907408Sgblack@eecs.umich.edu        // the time we get to process this packet. In the cases where
3917408Sgblack@eecs.umich.edu        // we are not responding after handling the snoop we also need
3927408Sgblack@eecs.umich.edu        // to create a copy of the request to be on the safe side. In
3937408Sgblack@eecs.umich.edu        // the latter case the cache is responsible for deleting both
3947408Sgblack@eecs.umich.edu        // the packet and the request as part of handling the deferred
3957408Sgblack@eecs.umich.edu        // snoop.
3967408Sgblack@eecs.umich.edu        PacketPtr cp_pkt = will_respond ? new Packet(pkt, true, true) :
3977405SAli.Saidi@ARM.com            new Packet(new Request(*pkt->req), pkt->cmd);
3987583SAli.Saidi@arm.com
3997583SAli.Saidi@arm.com        if (isPendingModified()) {
4007583SAli.Saidi@arm.com            // we are the ordering point, and will consequently
4017583SAli.Saidi@arm.com            // respond, and depending on whether the packet
4028059SAli.Saidi@ARM.com            // needsWritable or not we either pass a Shared line or a
4038059SAli.Saidi@ARM.com            // Modified line
4048059SAli.Saidi@ARM.com            pkt->setCacheResponding();
4058059SAli.Saidi@ARM.com
4068059SAli.Saidi@ARM.com            // inform the cache hierarchy that this cache had the line
4078059SAli.Saidi@ARM.com            // in the Modified state, even if the response is passed
4088059SAli.Saidi@ARM.com            // as Shared (and thus non-writable)
4098059SAli.Saidi@ARM.com            pkt->setResponderHadWritable();
4108059SAli.Saidi@ARM.com
4118059SAli.Saidi@ARM.com            // in the case of an uncacheable request there is no need
4128059SAli.Saidi@ARM.com            // to set the responderHadWritable flag, but since the
4138059SAli.Saidi@ARM.com            // recipient does not care there is no harm in doing so
4147583SAli.Saidi@arm.com        }
4157583SAli.Saidi@arm.com        targets.add(cp_pkt, curTick(), _order, Target::FromSnoop,
4167583SAli.Saidi@arm.com                    downstreamPending && targets.needsWritable);
4177583SAli.Saidi@arm.com
4187583SAli.Saidi@arm.com        if (pkt->needsWritable()) {
4197436Sdam.sunwoo@arm.com            // This transaction will take away our pending copy
4207436Sdam.sunwoo@arm.com            postInvalidate = true;
4217436Sdam.sunwoo@arm.com        }
4227436Sdam.sunwoo@arm.com    }
4237436Sdam.sunwoo@arm.com
4247436Sdam.sunwoo@arm.com    if (!pkt->needsWritable() && !pkt->req->isUncacheable()) {
4257436Sdam.sunwoo@arm.com        // This transaction will get a read-shared copy, downgrading
4267436Sdam.sunwoo@arm.com        // our copy if we had a writable one
4277436Sdam.sunwoo@arm.com        postDowngrade = true;
4287436Sdam.sunwoo@arm.com        // make sure that any downstream cache does not respond with a
4297436Sdam.sunwoo@arm.com        // writable (and dirty) copy even if it has one, unless it was
4307436Sdam.sunwoo@arm.com        // explicitly asked for one
4317436Sdam.sunwoo@arm.com        pkt->setHasSharers();
4327436Sdam.sunwoo@arm.com    }
4337436Sdam.sunwoo@arm.com
4347436Sdam.sunwoo@arm.com    return true;
4357436Sdam.sunwoo@arm.com}
4367436Sdam.sunwoo@arm.com
4377436Sdam.sunwoo@arm.com
4387436Sdam.sunwoo@arm.combool
4397436Sdam.sunwoo@arm.comMSHR::promoteDeferredTargets()
4407436Sdam.sunwoo@arm.com{
4417436Sdam.sunwoo@arm.com    assert(targets.empty());
4427436Sdam.sunwoo@arm.com    if (deferredTargets.empty()) {
4437436Sdam.sunwoo@arm.com        return false;
4447436Sdam.sunwoo@arm.com    }
4457436Sdam.sunwoo@arm.com
4467436Sdam.sunwoo@arm.com    // swap targets & deferredTargets lists
4477436Sdam.sunwoo@arm.com    std::swap(targets, deferredTargets);
4487436Sdam.sunwoo@arm.com
4497442Ssaidi@eecs.umich.edu    // clear deferredTargets flags
4507436Sdam.sunwoo@arm.com    deferredTargets.resetFlags();
4517436Sdam.sunwoo@arm.com
4528208SAli.Saidi@ARM.com    order = targets.front().order;
4537720Sgblack@eecs.umich.edu    readyTime = std::max(curTick(), targets.front().readyTime);
4547436Sdam.sunwoo@arm.com
4557436Sdam.sunwoo@arm.com    return true;
4567436Sdam.sunwoo@arm.com}
4577436Sdam.sunwoo@arm.com
4587436Sdam.sunwoo@arm.com
4597436Sdam.sunwoo@arm.comvoid
4607436Sdam.sunwoo@arm.comMSHR::promoteWritable()
4617436Sdam.sunwoo@arm.com{
4627436Sdam.sunwoo@arm.com    if (deferredTargets.needsWritable &&
4637436Sdam.sunwoo@arm.com        !(hasPostInvalidate() || hasPostDowngrade())) {
4647436Sdam.sunwoo@arm.com        // We got a writable response, but we have deferred targets
4657436Sdam.sunwoo@arm.com        // which are waiting to request a writable copy (not because
4667436Sdam.sunwoo@arm.com        // of a pending invalidate).  This can happen if the original
4677436Sdam.sunwoo@arm.com        // request was for a read-only block, but we got a writable
4687436Sdam.sunwoo@arm.com        // response anyway. Since we got the writable copy there's no
4697436Sdam.sunwoo@arm.com        // need to defer the targets, so move them up to the regular
4707436Sdam.sunwoo@arm.com        // target list.
4717436Sdam.sunwoo@arm.com        assert(!targets.needsWritable);
4727436Sdam.sunwoo@arm.com        targets.needsWritable = true;
4737436Sdam.sunwoo@arm.com        // if any of the deferred targets were upper-level cache
4747749SAli.Saidi@ARM.com        // requests marked downstreamPending, need to clear that
4757749SAli.Saidi@ARM.com        assert(!downstreamPending);  // not pending here anymore
4767749SAli.Saidi@ARM.com        deferredTargets.clearDownstreamPending();
4777749SAli.Saidi@ARM.com        // this clears out deferredTargets too
4787749SAli.Saidi@ARM.com        targets.splice(targets.end(), deferredTargets);
4797749SAli.Saidi@ARM.com        deferredTargets.resetFlags();
4807749SAli.Saidi@ARM.com    }
4818208SAli.Saidi@ARM.com}
4828208SAli.Saidi@ARM.com
4838208SAli.Saidi@ARM.com
4848208SAli.Saidi@ARM.combool
4858208SAli.Saidi@ARM.comMSHR::checkFunctional(PacketPtr pkt)
4868208SAli.Saidi@ARM.com{
4878208SAli.Saidi@ARM.com    // For printing, we treat the MSHR as a whole as single entity.
4887405SAli.Saidi@ARM.com    // For other requests, we iterate over the individual targets
4897405SAli.Saidi@ARM.com    // since that's where the actual data lies.
4907405SAli.Saidi@ARM.com    if (pkt->isPrint()) {
4917405SAli.Saidi@ARM.com        pkt->checkFunctional(this, blkAddr, isSecure, blkSize, NULL);
4927405SAli.Saidi@ARM.com        return false;
4937405SAli.Saidi@ARM.com    } else {
494        return (targets.checkFunctional(pkt) ||
495                deferredTargets.checkFunctional(pkt));
496    }
497}
498
499
500void
501MSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
502{
503    ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
504             prefix, blkAddr, blkAddr + blkSize - 1,
505             isSecure ? "s" : "ns",
506             isForward ? "Forward" : "",
507             allocOnFill ? "AllocOnFill" : "",
508             isForwardNoResponse() ? "ForwNoResp" : "",
509             needsWritable() ? "Wrtbl" : "",
510             _isUncacheable ? "Unc" : "",
511             inService ? "InSvc" : "",
512             downstreamPending ? "DwnPend" : "",
513             hasPostInvalidate() ? "PostInv" : "",
514             hasPostDowngrade() ? "PostDowngr" : "");
515
516    ccprintf(os, "%s  Targets:\n", prefix);
517    targets.print(os, verbosity, prefix + "    ");
518    if (!deferredTargets.empty()) {
519        ccprintf(os, "%s  Deferred Targets:\n", prefix);
520        deferredTargets.print(os, verbosity, prefix + "      ");
521    }
522}
523
524std::string
525MSHR::print() const
526{
527    ostringstream str;
528    print(str);
529    return str.str();
530}
531