mshr.cc revision 11278
12810SN/A/* 210764Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015 ARM Limited 39663Suri.wiener@arm.com * All rights reserved. 49663Suri.wiener@arm.com * 59663Suri.wiener@arm.com * The license below extends only to copyright in the software and shall 69663Suri.wiener@arm.com * not be construed as granting a license to any other intellectual 79663Suri.wiener@arm.com * property including but not limited to intellectual property relating 89663Suri.wiener@arm.com * to a hardware implementation of the functionality of the software 99663Suri.wiener@arm.com * licensed hereunder. You may use the software subject to the license 109663Suri.wiener@arm.com * terms below provided that you ensure that this notice is replicated 119663Suri.wiener@arm.com * unmodified and in its entirety in all distributions of the software, 129663Suri.wiener@arm.com * modified or unmodified, in source code or in binary form. 139663Suri.wiener@arm.com * 142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc. 162810SN/A * All rights reserved. 172810SN/A * 182810SN/A * Redistribution and use in source and binary forms, with or without 192810SN/A * modification, are permitted provided that the following conditions are 202810SN/A * met: redistributions of source code must retain the above copyright 212810SN/A * notice, this list of conditions and the following disclaimer; 222810SN/A * redistributions in binary form must reproduce the above copyright 232810SN/A * notice, this list of conditions and the following disclaimer in the 242810SN/A * documentation and/or other materials provided with the distribution; 252810SN/A * neither the name of the copyright holders nor the names of its 262810SN/A * contributors may be used to endorse or promote products derived from 272810SN/A * this software without specific prior written permission. 282810SN/A * 292810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810SN/A * 412810SN/A * Authors: Erik Hallnor 422810SN/A * Dave Greene 432810SN/A */ 442810SN/A 452810SN/A/** 462810SN/A * @file 472810SN/A * Miss Status and Handling Register (MSHR) definitions. 482810SN/A */ 492810SN/A 506216Snate@binkert.org#include <algorithm> 516216Snate@binkert.org#include <cassert> 522810SN/A#include <string> 532810SN/A#include <vector> 542810SN/A 556216Snate@binkert.org#include "base/misc.hh" 566216Snate@binkert.org#include "base/types.hh" 578232Snate@binkert.org#include "debug/Cache.hh" 586216Snate@binkert.org#include "mem/cache/cache.hh" 595338Sstever@gmail.com#include "mem/cache/mshr.hh" 606216Snate@binkert.org#include "sim/core.hh" 612810SN/A 622810SN/Ausing namespace std; 632810SN/A 649725Sandreas.hansson@arm.comMSHR::MSHR() : readyTime(0), _isUncacheable(false), downstreamPending(false), 6510582SCurtis.Dunham@arm.com pendingDirty(false), 6610503SCurtis.Dunham@arm.com postInvalidate(false), postDowngrade(false), 6710764Sandreas.hansson@arm.com queue(NULL), order(0), blkAddr(0), 6810764Sandreas.hansson@arm.com blkSize(0), isSecure(false), inService(false), 6911197Sandreas.hansson@arm.com isForward(false), allocOnFill(false), 7011278Sandreas.hansson@arm.com data(NULL) 712810SN/A{ 722810SN/A} 732810SN/A 744903SN/A 754903SN/AMSHR::TargetList::TargetList() 764903SN/A : needsExclusive(false), hasUpgrade(false) 774903SN/A{} 784903SN/A 794903SN/A 804903SN/Ainline void 814908SN/AMSHR::TargetList::add(PacketPtr pkt, Tick readyTime, 825875Ssteve.reinhardt@amd.com Counter order, Target::Source source, bool markPending) 834903SN/A{ 845875Ssteve.reinhardt@amd.com if (source != Target::FromSnoop) { 854903SN/A if (pkt->needsExclusive()) { 864903SN/A needsExclusive = true; 874903SN/A } 884903SN/A 897669Ssteve.reinhardt@amd.com // StoreCondReq is effectively an upgrade if it's in an MSHR 907669Ssteve.reinhardt@amd.com // since it would have been failed already if we didn't have a 917669Ssteve.reinhardt@amd.com // read-only copy 927669Ssteve.reinhardt@amd.com if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) { 934903SN/A hasUpgrade = true; 944903SN/A } 955318SN/A } 964908SN/A 975318SN/A if (markPending) { 989543Ssascha.bischoff@arm.com // Iterate over the SenderState stack and see if we find 999543Ssascha.bischoff@arm.com // an MSHR entry. If we do, set the downstreamPending 1009543Ssascha.bischoff@arm.com // flag. Otherwise, do nothing. 1019543Ssascha.bischoff@arm.com MSHR *mshr = pkt->findNextSenderState<MSHR>(); 1024908SN/A if (mshr != NULL) { 1034908SN/A assert(!mshr->downstreamPending); 1044908SN/A mshr->downstreamPending = true; 10511083Sandreas.hansson@arm.com } else { 10611083Sandreas.hansson@arm.com // No need to clear downstreamPending later 10711083Sandreas.hansson@arm.com markPending = false; 1084908SN/A } 1094903SN/A } 1104903SN/A 11110922Sandreas.hansson@arm.com emplace_back(pkt, readyTime, order, source, markPending); 1124903SN/A} 1134903SN/A 1144903SN/A 1157667Ssteve.reinhardt@amd.comstatic void 1167667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt) 1177667Ssteve.reinhardt@amd.com{ 1187667Ssteve.reinhardt@amd.com if (pkt->cmd == MemCmd::UpgradeReq) { 1197667Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::ReadExReq; 1207667Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n"); 1217667Ssteve.reinhardt@amd.com } else if (pkt->cmd == MemCmd::SCUpgradeReq) { 1227667Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::SCUpgradeFailReq; 1237667Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n"); 1247669Ssteve.reinhardt@amd.com } else if (pkt->cmd == MemCmd::StoreCondReq) { 1257669Ssteve.reinhardt@amd.com pkt->cmd = MemCmd::StoreCondFailReq; 1267669Ssteve.reinhardt@amd.com DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n"); 1277667Ssteve.reinhardt@amd.com } 1287667Ssteve.reinhardt@amd.com} 1297667Ssteve.reinhardt@amd.com 1307667Ssteve.reinhardt@amd.com 1314903SN/Avoid 1324903SN/AMSHR::TargetList::replaceUpgrades() 1334903SN/A{ 1344903SN/A if (!hasUpgrade) 1354903SN/A return; 1364903SN/A 13710766Sandreas.hansson@arm.com for (auto& t : *this) { 13810766Sandreas.hansson@arm.com replaceUpgrade(t.pkt); 1394903SN/A } 1404903SN/A 1414903SN/A hasUpgrade = false; 1424903SN/A} 1434903SN/A 1444903SN/A 1452810SN/Avoid 1464908SN/AMSHR::TargetList::clearDownstreamPending() 1474908SN/A{ 14810766Sandreas.hansson@arm.com for (auto& t : *this) { 14910766Sandreas.hansson@arm.com if (t.markedPending) { 1509543Ssascha.bischoff@arm.com // Iterate over the SenderState stack and see if we find 1519543Ssascha.bischoff@arm.com // an MSHR entry. If we find one, clear the 1529543Ssascha.bischoff@arm.com // downstreamPending flag by calling 1539543Ssascha.bischoff@arm.com // clearDownstreamPending(). This recursively clears the 1549543Ssascha.bischoff@arm.com // downstreamPending flag in all caches this packet has 1559543Ssascha.bischoff@arm.com // passed through. 15610766Sandreas.hansson@arm.com MSHR *mshr = t.pkt->findNextSenderState<MSHR>(); 1575318SN/A if (mshr != NULL) { 1585318SN/A mshr->clearDownstreamPending(); 1595318SN/A } 1604908SN/A } 1614908SN/A } 1624908SN/A} 1634908SN/A 1644908SN/A 1654920SN/Abool 1664920SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt) 1674920SN/A{ 16810766Sandreas.hansson@arm.com for (auto& t : *this) { 16910766Sandreas.hansson@arm.com if (pkt->checkFunctional(t.pkt)) { 1704920SN/A return true; 1714920SN/A } 1724920SN/A } 1734920SN/A 1744920SN/A return false; 1754920SN/A} 1764920SN/A 1774920SN/A 1784908SN/Avoid 17910766Sandreas.hansson@arm.comMSHR::TargetList::print(std::ostream &os, int verbosity, 18010766Sandreas.hansson@arm.com const std::string &prefix) const 1815314SN/A{ 18210766Sandreas.hansson@arm.com for (auto& t : *this) { 1835875Ssteve.reinhardt@amd.com const char *s; 18410766Sandreas.hansson@arm.com switch (t.source) { 1858988SAli.Saidi@ARM.com case Target::FromCPU: 1868988SAli.Saidi@ARM.com s = "FromCPU"; 1878988SAli.Saidi@ARM.com break; 1888988SAli.Saidi@ARM.com case Target::FromSnoop: 1898988SAli.Saidi@ARM.com s = "FromSnoop"; 1908988SAli.Saidi@ARM.com break; 1918988SAli.Saidi@ARM.com case Target::FromPrefetcher: 1928988SAli.Saidi@ARM.com s = "FromPrefetcher"; 1938988SAli.Saidi@ARM.com break; 1948988SAli.Saidi@ARM.com default: 1958988SAli.Saidi@ARM.com s = ""; 1968988SAli.Saidi@ARM.com break; 1975875Ssteve.reinhardt@amd.com } 1985875Ssteve.reinhardt@amd.com ccprintf(os, "%s%s: ", prefix, s); 19910766Sandreas.hansson@arm.com t.pkt->print(os, verbosity, ""); 2005314SN/A } 2015314SN/A} 2025314SN/A 2035314SN/A 2045314SN/Avoid 20510764Sandreas.hansson@arm.comMSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target, 20611197Sandreas.hansson@arm.com Tick when_ready, Counter _order, bool alloc_on_fill) 2072810SN/A{ 20810764Sandreas.hansson@arm.com blkAddr = blk_addr; 20910764Sandreas.hansson@arm.com blkSize = blk_size; 21010028SGiacomo.Gabrielli@arm.com isSecure = target->isSecure(); 21110764Sandreas.hansson@arm.com readyTime = when_ready; 2124666SN/A order = _order; 2134626SN/A assert(target); 2145730SSteve.Reinhardt@amd.com isForward = false; 21511197Sandreas.hansson@arm.com allocOnFill = alloc_on_fill; 2164626SN/A _isUncacheable = target->req->isUncacheable(); 2174626SN/A inService = false; 2184908SN/A downstreamPending = false; 2199725Sandreas.hansson@arm.com assert(targets.isReset()); 2204626SN/A // Don't know of a case where we would allocate a new MSHR for a 2215875Ssteve.reinhardt@amd.com // snoop (mem-side request), so set source according to request here 2225875Ssteve.reinhardt@amd.com Target::Source source = (target->cmd == MemCmd::HardPFReq) ? 2235875Ssteve.reinhardt@amd.com Target::FromPrefetcher : Target::FromCPU; 22410764Sandreas.hansson@arm.com targets.add(target, when_ready, _order, source, true); 2259725Sandreas.hansson@arm.com assert(deferredTargets.isReset()); 2264668SN/A data = NULL; 2272810SN/A} 2282810SN/A 2294908SN/A 2305318SN/Avoid 2315318SN/AMSHR::clearDownstreamPending() 2325318SN/A{ 2335318SN/A assert(downstreamPending); 2345318SN/A downstreamPending = false; 2355318SN/A // recursively clear flag on any MSHRs we will be forwarding 2365318SN/A // responses to 2379725Sandreas.hansson@arm.com targets.clearDownstreamPending(); 2385318SN/A} 2395318SN/A 2404908SN/Abool 24110679Sandreas.hansson@arm.comMSHR::markInService(bool pending_dirty_resp) 2424908SN/A{ 2434908SN/A assert(!inService); 2445730SSteve.Reinhardt@amd.com if (isForwardNoResponse()) { 2454908SN/A // we just forwarded the request packet & don't expect a 2464908SN/A // response, so get rid of it 2474908SN/A assert(getNumTargets() == 1); 2484908SN/A popTarget(); 2494908SN/A return true; 2504908SN/A } 25110424Sandreas.hansson@arm.com 2524908SN/A inService = true; 25310679Sandreas.hansson@arm.com pendingDirty = targets.needsExclusive || pending_dirty_resp; 2547667Ssteve.reinhardt@amd.com postInvalidate = postDowngrade = false; 2557667Ssteve.reinhardt@amd.com 2564908SN/A if (!downstreamPending) { 2574908SN/A // let upstream caches know that the request has made it to a 2584908SN/A // level where it's going to get a response 2599725Sandreas.hansson@arm.com targets.clearDownstreamPending(); 2604908SN/A } 2614908SN/A return false; 2624908SN/A} 2634908SN/A 2644908SN/A 2652810SN/Avoid 2662810SN/AMSHR::deallocate() 2672810SN/A{ 2689725Sandreas.hansson@arm.com assert(targets.empty()); 2699725Sandreas.hansson@arm.com targets.resetFlags(); 2709725Sandreas.hansson@arm.com assert(deferredTargets.isReset()); 2712810SN/A inService = false; 2722810SN/A} 2732810SN/A 2742810SN/A/* 2752810SN/A * Adds a target to an MSHR 2762810SN/A */ 2772810SN/Avoid 27811197Sandreas.hansson@arm.comMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order, 27911197Sandreas.hansson@arm.com bool alloc_on_fill) 2802810SN/A{ 28110768Sandreas.hansson@arm.com // assume we'd never issue a prefetch when we've got an 28210768Sandreas.hansson@arm.com // outstanding miss 28310768Sandreas.hansson@arm.com assert(pkt->cmd != MemCmd::HardPFReq); 28410768Sandreas.hansson@arm.com 28510768Sandreas.hansson@arm.com // uncacheable accesses always allocate a new MSHR, and cacheable 28610768Sandreas.hansson@arm.com // accesses ignore any uncacheable MSHRs, thus we should never 28710768Sandreas.hansson@arm.com // have targets addded if originally allocated uncacheable 28810768Sandreas.hansson@arm.com assert(!_isUncacheable); 28910768Sandreas.hansson@arm.com 29011197Sandreas.hansson@arm.com // potentially re-evaluate whether we should allocate on a fill or 29111197Sandreas.hansson@arm.com // not 29211197Sandreas.hansson@arm.com allocOnFill = allocOnFill || alloc_on_fill; 29311197Sandreas.hansson@arm.com 2944903SN/A // if there's a request already in service for this MSHR, we will 2954903SN/A // have to defer the new target until after the response if any of 2964903SN/A // the following are true: 2974903SN/A // - there are other targets already deferred 2984903SN/A // - there's a pending invalidate to be applied after the response 2994903SN/A // comes back (but before this target is processed) 3007667Ssteve.reinhardt@amd.com // - this target requires an exclusive block and either we're not 3017667Ssteve.reinhardt@amd.com // getting an exclusive block back or we have already snooped 3027667Ssteve.reinhardt@amd.com // another read request that will downgrade our exclusive block 3037667Ssteve.reinhardt@amd.com // to shared 3044903SN/A if (inService && 3059725Sandreas.hansson@arm.com (!deferredTargets.empty() || hasPostInvalidate() || 3067667Ssteve.reinhardt@amd.com (pkt->needsExclusive() && 3077667Ssteve.reinhardt@amd.com (!isPendingDirty() || hasPostDowngrade() || isForward)))) { 3084903SN/A // need to put on deferred list 3097667Ssteve.reinhardt@amd.com if (hasPostInvalidate()) 3107667Ssteve.reinhardt@amd.com replaceUpgrade(pkt); 3119725Sandreas.hansson@arm.com deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true); 3124665SN/A } else { 3135318SN/A // No request outstanding, or still OK to append to 3145318SN/A // outstanding request: append to regular target list. Only 3155318SN/A // mark pending if current request hasn't been issued yet 3165318SN/A // (isn't in service). 3179725Sandreas.hansson@arm.com targets.add(pkt, whenReady, _order, Target::FromCPU, !inService); 3182810SN/A } 3194665SN/A} 3204665SN/A 3214902SN/Abool 3224902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order) 3234665SN/A{ 32410725Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 3259663Suri.wiener@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 3264910SN/A if (!inService || (pkt->isExpressSnoop() && downstreamPending)) { 3274903SN/A // Request has not been issued yet, or it's been issued 3284903SN/A // locally but is buffered unissued at some downstream cache 3294903SN/A // which is forwarding us this snoop. Either way, the packet 3304903SN/A // we're snooping logically precedes this MSHR's request, so 3314903SN/A // the snoop has no impact on the MSHR, but must be processed 3324903SN/A // in the standard way by the cache. The only exception is 3334903SN/A // that if we're an L2+ cache buffering an UpgradeReq from a 3344903SN/A // higher-level cache, and the snoop is invalidating, then our 3354903SN/A // buffered upgrades must be converted to read exclusives, 3364903SN/A // since the upper-level cache no longer has a valid copy. 3374903SN/A // That is, even though the upper-level cache got out on its 3384903SN/A // local bus first, some other invalidating transaction 3394903SN/A // reached the global bus before the upgrade did. 3404903SN/A if (pkt->needsExclusive()) { 3419725Sandreas.hansson@arm.com targets.replaceUpgrades(); 3429725Sandreas.hansson@arm.com deferredTargets.replaceUpgrades(); 3434903SN/A } 3444903SN/A 3454902SN/A return false; 3464902SN/A } 3474665SN/A 3484903SN/A // From here on down, the request issued by this MSHR logically 3494903SN/A // precedes the request we're snooping. 3504903SN/A if (pkt->needsExclusive()) { 3514903SN/A // snooped request still precedes the re-request we'll have to 3524903SN/A // issue for deferred targets, if any... 3539725Sandreas.hansson@arm.com deferredTargets.replaceUpgrades(); 3544903SN/A } 3554903SN/A 3567667Ssteve.reinhardt@amd.com if (hasPostInvalidate()) { 3574665SN/A // a prior snoop has already appended an invalidation, so 3584903SN/A // logically we don't have the block anymore; no need for 3594903SN/A // further snooping. 3604902SN/A return true; 3614665SN/A } 3624665SN/A 3637667Ssteve.reinhardt@amd.com if (isPendingDirty() || pkt->isInvalidate()) { 3647667Ssteve.reinhardt@amd.com // We need to save and replay the packet in two cases: 3657667Ssteve.reinhardt@amd.com // 1. We're awaiting an exclusive copy, so ownership is pending, 36611271Sandreas.hansson@arm.com // and we need to deal with the snoop after we receive data. 3677667Ssteve.reinhardt@amd.com // 2. It's an invalidation (e.g., UpgradeReq), and we need 3687667Ssteve.reinhardt@amd.com // to forward the snoop up the hierarchy after the current 3697667Ssteve.reinhardt@amd.com // transaction completes. 37010571Sandreas.hansson@arm.com 37111271Sandreas.hansson@arm.com // Start by determining if we will eventually respond or not, 37211271Sandreas.hansson@arm.com // matching the conditions checked in Cache::handleSnoop 37311271Sandreas.hansson@arm.com bool will_respond = isPendingDirty() && pkt->needsResponse() && 37411271Sandreas.hansson@arm.com pkt->cmd != MemCmd::InvalidateReq; 37511271Sandreas.hansson@arm.com 37611271Sandreas.hansson@arm.com // The packet we are snooping may be deleted by the time we 37711271Sandreas.hansson@arm.com // actually process the target, and we consequently need to 37811271Sandreas.hansson@arm.com // save a copy here. Clear flags and also allocate new data as 37911271Sandreas.hansson@arm.com // the original packet data storage may have been deleted by 38011271Sandreas.hansson@arm.com // the time we get to process this packet. In the cases where 38111271Sandreas.hansson@arm.com // we are not responding after handling the snoop we also need 38211271Sandreas.hansson@arm.com // to create a copy of the request to be on the safe side. In 38311271Sandreas.hansson@arm.com // the latter case the cache is responsible for deleting both 38411271Sandreas.hansson@arm.com // the packet and the request as part of handling the deferred 38511271Sandreas.hansson@arm.com // snoop. 38611271Sandreas.hansson@arm.com PacketPtr cp_pkt = will_respond ? new Packet(pkt, true, true) : 38711271Sandreas.hansson@arm.com new Packet(new Request(*pkt->req), pkt->cmd); 3884670SN/A 38910582SCurtis.Dunham@arm.com if (isPendingDirty()) { 39011271Sandreas.hansson@arm.com // The new packet will need to get the response from the 39110826Sstephan.diestelhorst@ARM.com // MSHR already queued up here 3924670SN/A pkt->assertMemInhibit(); 39310821Sandreas.hansson@arm.com // in the case of an uncacheable request there is no need 39410821Sandreas.hansson@arm.com // to set the exclusive flag, but since the recipient does 39510821Sandreas.hansson@arm.com // not care there is no harm in doing so 3964916SN/A pkt->setSupplyExclusive(); 3974670SN/A } 39810826Sstephan.diestelhorst@ARM.com targets.add(cp_pkt, curTick(), _order, Target::FromSnoop, 39910826Sstephan.diestelhorst@ARM.com downstreamPending && targets.needsExclusive); 4004670SN/A 4014670SN/A if (pkt->needsExclusive()) { 4024670SN/A // This transaction will take away our pending copy 4037667Ssteve.reinhardt@amd.com postInvalidate = true; 4044670SN/A } 4057667Ssteve.reinhardt@amd.com } 4067667Ssteve.reinhardt@amd.com 40710821Sandreas.hansson@arm.com if (!pkt->needsExclusive() && !pkt->req->isUncacheable()) { 4087667Ssteve.reinhardt@amd.com // This transaction will get a read-shared copy, downgrading 4097667Ssteve.reinhardt@amd.com // our copy if we had an exclusive one 4107667Ssteve.reinhardt@amd.com postDowngrade = true; 4114670SN/A pkt->assertShared(); 4124667SN/A } 4134902SN/A 4144902SN/A return true; 4154665SN/A} 4164665SN/A 4174665SN/A 4184665SN/Abool 4194665SN/AMSHR::promoteDeferredTargets() 4204665SN/A{ 4219725Sandreas.hansson@arm.com assert(targets.empty()); 4229725Sandreas.hansson@arm.com if (deferredTargets.empty()) { 4234665SN/A return false; 4244665SN/A } 4254665SN/A 4264903SN/A // swap targets & deferredTargets lists 4279725Sandreas.hansson@arm.com std::swap(targets, deferredTargets); 4284903SN/A 4294903SN/A // clear deferredTargets flags 4309725Sandreas.hansson@arm.com deferredTargets.resetFlags(); 4314903SN/A 4329725Sandreas.hansson@arm.com order = targets.front().order; 4339725Sandreas.hansson@arm.com readyTime = std::max(curTick(), targets.front().readyTime); 4344665SN/A 4354665SN/A return true; 4362810SN/A} 4372810SN/A 4382810SN/A 4392810SN/Avoid 44011177Sandreas.hansson@arm.comMSHR::promoteExclusive() 4414668SN/A{ 44211177Sandreas.hansson@arm.com if (deferredTargets.needsExclusive && 44311177Sandreas.hansson@arm.com !(hasPostInvalidate() || hasPostDowngrade())) { 4445270SN/A // We got an exclusive response, but we have deferred targets 4455270SN/A // which are waiting to request an exclusive copy (not because 4465270SN/A // of a pending invalidate). This can happen if the original 4475270SN/A // request was for a read-only (non-exclusive) block, but we 4485270SN/A // got an exclusive copy anyway because of the E part of the 4495270SN/A // MOESI/MESI protocol. Since we got the exclusive copy 4505270SN/A // there's no need to defer the targets, so move them up to 4515270SN/A // the regular target list. 4529725Sandreas.hansson@arm.com assert(!targets.needsExclusive); 4539725Sandreas.hansson@arm.com targets.needsExclusive = true; 4545318SN/A // if any of the deferred targets were upper-level cache 4555318SN/A // requests marked downstreamPending, need to clear that 4565318SN/A assert(!downstreamPending); // not pending here anymore 4579725Sandreas.hansson@arm.com deferredTargets.clearDownstreamPending(); 4585270SN/A // this clears out deferredTargets too 4599725Sandreas.hansson@arm.com targets.splice(targets.end(), deferredTargets); 4609725Sandreas.hansson@arm.com deferredTargets.resetFlags(); 4615270SN/A } 4624668SN/A} 4634668SN/A 4644668SN/A 4655314SN/Abool 4665314SN/AMSHR::checkFunctional(PacketPtr pkt) 4675314SN/A{ 4685314SN/A // For printing, we treat the MSHR as a whole as single entity. 4695314SN/A // For other requests, we iterate over the individual targets 4705314SN/A // since that's where the actual data lies. 4715314SN/A if (pkt->isPrint()) { 47210764Sandreas.hansson@arm.com pkt->checkFunctional(this, blkAddr, isSecure, blkSize, NULL); 4735314SN/A return false; 4745314SN/A } else { 4759725Sandreas.hansson@arm.com return (targets.checkFunctional(pkt) || 4769725Sandreas.hansson@arm.com deferredTargets.checkFunctional(pkt)); 4775314SN/A } 4785314SN/A} 4795314SN/A 4805314SN/A 4814668SN/Avoid 4825314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const 4832810SN/A{ 48410725Sandreas.hansson@arm.com ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n", 48510764Sandreas.hansson@arm.com prefix, blkAddr, blkAddr + blkSize - 1, 48610028SGiacomo.Gabrielli@arm.com isSecure ? "s" : "ns", 4875730SSteve.Reinhardt@amd.com isForward ? "Forward" : "", 48811197Sandreas.hansson@arm.com allocOnFill ? "AllocOnFill" : "", 4895730SSteve.Reinhardt@amd.com isForwardNoResponse() ? "ForwNoResp" : "", 4905314SN/A needsExclusive() ? "Excl" : "", 4915314SN/A _isUncacheable ? "Unc" : "", 4925314SN/A inService ? "InSvc" : "", 4935314SN/A downstreamPending ? "DwnPend" : "", 4947667Ssteve.reinhardt@amd.com hasPostInvalidate() ? "PostInv" : "", 4957667Ssteve.reinhardt@amd.com hasPostDowngrade() ? "PostDowngr" : ""); 4962810SN/A 4975314SN/A ccprintf(os, "%s Targets:\n", prefix); 4989725Sandreas.hansson@arm.com targets.print(os, verbosity, prefix + " "); 4999725Sandreas.hansson@arm.com if (!deferredTargets.empty()) { 5005314SN/A ccprintf(os, "%s Deferred Targets:\n", prefix); 5019725Sandreas.hansson@arm.com deferredTargets.print(os, verbosity, prefix + " "); 5022810SN/A } 5032810SN/A} 5042810SN/A 5059663Suri.wiener@arm.comstd::string 5069663Suri.wiener@arm.comMSHR::print() const 5079663Suri.wiener@arm.com{ 5089663Suri.wiener@arm.com ostringstream str; 5099663Suri.wiener@arm.com print(str); 5109663Suri.wiener@arm.com return str.str(); 5119663Suri.wiener@arm.com} 512