mshr.cc revision 11177
12810SN/A/*
210764Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015 ARM Limited
39663Suri.wiener@arm.com * All rights reserved.
49663Suri.wiener@arm.com *
59663Suri.wiener@arm.com * The license below extends only to copyright in the software and shall
69663Suri.wiener@arm.com * not be construed as granting a license to any other intellectual
79663Suri.wiener@arm.com * property including but not limited to intellectual property relating
89663Suri.wiener@arm.com * to a hardware implementation of the functionality of the software
99663Suri.wiener@arm.com * licensed hereunder.  You may use the software subject to the license
109663Suri.wiener@arm.com * terms below provided that you ensure that this notice is replicated
119663Suri.wiener@arm.com * unmodified and in its entirety in all distributions of the software,
129663Suri.wiener@arm.com * modified or unmodified, in source code or in binary form.
139663Suri.wiener@arm.com *
142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
157636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
162810SN/A * All rights reserved.
172810SN/A *
182810SN/A * Redistribution and use in source and binary forms, with or without
192810SN/A * modification, are permitted provided that the following conditions are
202810SN/A * met: redistributions of source code must retain the above copyright
212810SN/A * notice, this list of conditions and the following disclaimer;
222810SN/A * redistributions in binary form must reproduce the above copyright
232810SN/A * notice, this list of conditions and the following disclaimer in the
242810SN/A * documentation and/or other materials provided with the distribution;
252810SN/A * neither the name of the copyright holders nor the names of its
262810SN/A * contributors may be used to endorse or promote products derived from
272810SN/A * this software without specific prior written permission.
282810SN/A *
292810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402810SN/A *
412810SN/A * Authors: Erik Hallnor
422810SN/A *          Dave Greene
432810SN/A */
442810SN/A
452810SN/A/**
462810SN/A * @file
472810SN/A * Miss Status and Handling Register (MSHR) definitions.
482810SN/A */
492810SN/A
506216Snate@binkert.org#include <algorithm>
516216Snate@binkert.org#include <cassert>
522810SN/A#include <string>
532810SN/A#include <vector>
542810SN/A
556216Snate@binkert.org#include "base/misc.hh"
566216Snate@binkert.org#include "base/types.hh"
578232Snate@binkert.org#include "debug/Cache.hh"
586216Snate@binkert.org#include "mem/cache/cache.hh"
595338Sstever@gmail.com#include "mem/cache/mshr.hh"
606216Snate@binkert.org#include "sim/core.hh"
612810SN/A
622810SN/Ausing namespace std;
632810SN/A
649725Sandreas.hansson@arm.comMSHR::MSHR() : readyTime(0), _isUncacheable(false), downstreamPending(false),
6510582SCurtis.Dunham@arm.com               pendingDirty(false),
6610503SCurtis.Dunham@arm.com               postInvalidate(false), postDowngrade(false),
6710764Sandreas.hansson@arm.com               queue(NULL), order(0), blkAddr(0),
6810764Sandreas.hansson@arm.com               blkSize(0), isSecure(false), inService(false),
6910503SCurtis.Dunham@arm.com               isForward(false), threadNum(InvalidThreadID), data(NULL)
702810SN/A{
712810SN/A}
722810SN/A
734903SN/A
744903SN/AMSHR::TargetList::TargetList()
754903SN/A    : needsExclusive(false), hasUpgrade(false)
764903SN/A{}
774903SN/A
784903SN/A
794903SN/Ainline void
804908SN/AMSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
815875Ssteve.reinhardt@amd.com                      Counter order, Target::Source source, bool markPending)
824903SN/A{
835875Ssteve.reinhardt@amd.com    if (source != Target::FromSnoop) {
844903SN/A        if (pkt->needsExclusive()) {
854903SN/A            needsExclusive = true;
864903SN/A        }
874903SN/A
887669Ssteve.reinhardt@amd.com        // StoreCondReq is effectively an upgrade if it's in an MSHR
897669Ssteve.reinhardt@amd.com        // since it would have been failed already if we didn't have a
907669Ssteve.reinhardt@amd.com        // read-only copy
917669Ssteve.reinhardt@amd.com        if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
924903SN/A            hasUpgrade = true;
934903SN/A        }
945318SN/A    }
954908SN/A
965318SN/A    if (markPending) {
979543Ssascha.bischoff@arm.com        // Iterate over the SenderState stack and see if we find
989543Ssascha.bischoff@arm.com        // an MSHR entry. If we do, set the downstreamPending
999543Ssascha.bischoff@arm.com        // flag. Otherwise, do nothing.
1009543Ssascha.bischoff@arm.com        MSHR *mshr = pkt->findNextSenderState<MSHR>();
1014908SN/A        if (mshr != NULL) {
1024908SN/A            assert(!mshr->downstreamPending);
1034908SN/A            mshr->downstreamPending = true;
10411083Sandreas.hansson@arm.com        } else {
10511083Sandreas.hansson@arm.com            // No need to clear downstreamPending later
10611083Sandreas.hansson@arm.com            markPending = false;
1074908SN/A        }
1084903SN/A    }
1094903SN/A
11010922Sandreas.hansson@arm.com    emplace_back(pkt, readyTime, order, source, markPending);
1114903SN/A}
1124903SN/A
1134903SN/A
1147667Ssteve.reinhardt@amd.comstatic void
1157667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt)
1167667Ssteve.reinhardt@amd.com{
1177667Ssteve.reinhardt@amd.com    if (pkt->cmd == MemCmd::UpgradeReq) {
1187667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::ReadExReq;
1197667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
1207667Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
1217667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::SCUpgradeFailReq;
1227667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
1237669Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::StoreCondReq) {
1247669Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::StoreCondFailReq;
1257669Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
1267667Ssteve.reinhardt@amd.com    }
1277667Ssteve.reinhardt@amd.com}
1287667Ssteve.reinhardt@amd.com
1297667Ssteve.reinhardt@amd.com
1304903SN/Avoid
1314903SN/AMSHR::TargetList::replaceUpgrades()
1324903SN/A{
1334903SN/A    if (!hasUpgrade)
1344903SN/A        return;
1354903SN/A
13610766Sandreas.hansson@arm.com    for (auto& t : *this) {
13710766Sandreas.hansson@arm.com        replaceUpgrade(t.pkt);
1384903SN/A    }
1394903SN/A
1404903SN/A    hasUpgrade = false;
1414903SN/A}
1424903SN/A
1434903SN/A
1442810SN/Avoid
1454908SN/AMSHR::TargetList::clearDownstreamPending()
1464908SN/A{
14710766Sandreas.hansson@arm.com    for (auto& t : *this) {
14810766Sandreas.hansson@arm.com        if (t.markedPending) {
1499543Ssascha.bischoff@arm.com            // Iterate over the SenderState stack and see if we find
1509543Ssascha.bischoff@arm.com            // an MSHR entry. If we find one, clear the
1519543Ssascha.bischoff@arm.com            // downstreamPending flag by calling
1529543Ssascha.bischoff@arm.com            // clearDownstreamPending(). This recursively clears the
1539543Ssascha.bischoff@arm.com            // downstreamPending flag in all caches this packet has
1549543Ssascha.bischoff@arm.com            // passed through.
15510766Sandreas.hansson@arm.com            MSHR *mshr = t.pkt->findNextSenderState<MSHR>();
1565318SN/A            if (mshr != NULL) {
1575318SN/A                mshr->clearDownstreamPending();
1585318SN/A            }
1594908SN/A        }
1604908SN/A    }
1614908SN/A}
1624908SN/A
1634908SN/A
1644920SN/Abool
1654920SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt)
1664920SN/A{
16710766Sandreas.hansson@arm.com    for (auto& t : *this) {
16810766Sandreas.hansson@arm.com        if (pkt->checkFunctional(t.pkt)) {
1694920SN/A            return true;
1704920SN/A        }
1714920SN/A    }
1724920SN/A
1734920SN/A    return false;
1744920SN/A}
1754920SN/A
1764920SN/A
1774908SN/Avoid
17810766Sandreas.hansson@arm.comMSHR::TargetList::print(std::ostream &os, int verbosity,
17910766Sandreas.hansson@arm.com                        const std::string &prefix) const
1805314SN/A{
18110766Sandreas.hansson@arm.com    for (auto& t : *this) {
1825875Ssteve.reinhardt@amd.com        const char *s;
18310766Sandreas.hansson@arm.com        switch (t.source) {
1848988SAli.Saidi@ARM.com          case Target::FromCPU:
1858988SAli.Saidi@ARM.com            s = "FromCPU";
1868988SAli.Saidi@ARM.com            break;
1878988SAli.Saidi@ARM.com          case Target::FromSnoop:
1888988SAli.Saidi@ARM.com            s = "FromSnoop";
1898988SAli.Saidi@ARM.com            break;
1908988SAli.Saidi@ARM.com          case Target::FromPrefetcher:
1918988SAli.Saidi@ARM.com            s = "FromPrefetcher";
1928988SAli.Saidi@ARM.com            break;
1938988SAli.Saidi@ARM.com          default:
1948988SAli.Saidi@ARM.com            s = "";
1958988SAli.Saidi@ARM.com            break;
1965875Ssteve.reinhardt@amd.com        }
1975875Ssteve.reinhardt@amd.com        ccprintf(os, "%s%s: ", prefix, s);
19810766Sandreas.hansson@arm.com        t.pkt->print(os, verbosity, "");
1995314SN/A    }
2005314SN/A}
2015314SN/A
2025314SN/A
2035314SN/Avoid
20410764Sandreas.hansson@arm.comMSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
20510764Sandreas.hansson@arm.com               Tick when_ready, Counter _order)
2062810SN/A{
20710764Sandreas.hansson@arm.com    blkAddr = blk_addr;
20810764Sandreas.hansson@arm.com    blkSize = blk_size;
20910028SGiacomo.Gabrielli@arm.com    isSecure = target->isSecure();
21010764Sandreas.hansson@arm.com    readyTime = when_ready;
2114666SN/A    order = _order;
2124626SN/A    assert(target);
2135730SSteve.Reinhardt@amd.com    isForward = false;
2144626SN/A    _isUncacheable = target->req->isUncacheable();
2154626SN/A    inService = false;
2164908SN/A    downstreamPending = false;
2174626SN/A    threadNum = 0;
2189725Sandreas.hansson@arm.com    assert(targets.isReset());
2194626SN/A    // Don't know of a case where we would allocate a new MSHR for a
2205875Ssteve.reinhardt@amd.com    // snoop (mem-side request), so set source according to request here
2215875Ssteve.reinhardt@amd.com    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
2225875Ssteve.reinhardt@amd.com        Target::FromPrefetcher : Target::FromCPU;
22310764Sandreas.hansson@arm.com    targets.add(target, when_ready, _order, source, true);
2249725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
2254668SN/A    data = NULL;
2262810SN/A}
2272810SN/A
2284908SN/A
2295318SN/Avoid
2305318SN/AMSHR::clearDownstreamPending()
2315318SN/A{
2325318SN/A    assert(downstreamPending);
2335318SN/A    downstreamPending = false;
2345318SN/A    // recursively clear flag on any MSHRs we will be forwarding
2355318SN/A    // responses to
2369725Sandreas.hansson@arm.com    targets.clearDownstreamPending();
2375318SN/A}
2385318SN/A
2394908SN/Abool
24010679Sandreas.hansson@arm.comMSHR::markInService(bool pending_dirty_resp)
2414908SN/A{
2424908SN/A    assert(!inService);
2435730SSteve.Reinhardt@amd.com    if (isForwardNoResponse()) {
2444908SN/A        // we just forwarded the request packet & don't expect a
2454908SN/A        // response, so get rid of it
2464908SN/A        assert(getNumTargets() == 1);
2474908SN/A        popTarget();
2484908SN/A        return true;
2494908SN/A    }
25010424Sandreas.hansson@arm.com
2514908SN/A    inService = true;
25210679Sandreas.hansson@arm.com    pendingDirty = targets.needsExclusive || pending_dirty_resp;
2537667Ssteve.reinhardt@amd.com    postInvalidate = postDowngrade = false;
2547667Ssteve.reinhardt@amd.com
2554908SN/A    if (!downstreamPending) {
2564908SN/A        // let upstream caches know that the request has made it to a
2574908SN/A        // level where it's going to get a response
2589725Sandreas.hansson@arm.com        targets.clearDownstreamPending();
2594908SN/A    }
2604908SN/A    return false;
2614908SN/A}
2624908SN/A
2634908SN/A
2642810SN/Avoid
2652810SN/AMSHR::deallocate()
2662810SN/A{
2679725Sandreas.hansson@arm.com    assert(targets.empty());
2689725Sandreas.hansson@arm.com    targets.resetFlags();
2699725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
2702810SN/A    inService = false;
2712810SN/A}
2722810SN/A
2732810SN/A/*
2742810SN/A * Adds a target to an MSHR
2752810SN/A */
2762810SN/Avoid
2774903SN/AMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order)
2782810SN/A{
27910768Sandreas.hansson@arm.com    // assume we'd never issue a prefetch when we've got an
28010768Sandreas.hansson@arm.com    // outstanding miss
28110768Sandreas.hansson@arm.com    assert(pkt->cmd != MemCmd::HardPFReq);
28210768Sandreas.hansson@arm.com
28310768Sandreas.hansson@arm.com    // uncacheable accesses always allocate a new MSHR, and cacheable
28410768Sandreas.hansson@arm.com    // accesses ignore any uncacheable MSHRs, thus we should never
28510768Sandreas.hansson@arm.com    // have targets addded if originally allocated uncacheable
28610768Sandreas.hansson@arm.com    assert(!_isUncacheable);
28710768Sandreas.hansson@arm.com
2884903SN/A    // if there's a request already in service for this MSHR, we will
2894903SN/A    // have to defer the new target until after the response if any of
2904903SN/A    // the following are true:
2914903SN/A    // - there are other targets already deferred
2924903SN/A    // - there's a pending invalidate to be applied after the response
2934903SN/A    //   comes back (but before this target is processed)
2947667Ssteve.reinhardt@amd.com    // - this target requires an exclusive block and either we're not
2957667Ssteve.reinhardt@amd.com    //   getting an exclusive block back or we have already snooped
2967667Ssteve.reinhardt@amd.com    //   another read request that will downgrade our exclusive block
2977667Ssteve.reinhardt@amd.com    //   to shared
2984903SN/A    if (inService &&
2999725Sandreas.hansson@arm.com        (!deferredTargets.empty() || hasPostInvalidate() ||
3007667Ssteve.reinhardt@amd.com         (pkt->needsExclusive() &&
3017667Ssteve.reinhardt@amd.com          (!isPendingDirty() || hasPostDowngrade() || isForward)))) {
3024903SN/A        // need to put on deferred list
3037667Ssteve.reinhardt@amd.com        if (hasPostInvalidate())
3047667Ssteve.reinhardt@amd.com            replaceUpgrade(pkt);
3059725Sandreas.hansson@arm.com        deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true);
3064665SN/A    } else {
3075318SN/A        // No request outstanding, or still OK to append to
3085318SN/A        // outstanding request: append to regular target list.  Only
3095318SN/A        // mark pending if current request hasn't been issued yet
3105318SN/A        // (isn't in service).
3119725Sandreas.hansson@arm.com        targets.add(pkt, whenReady, _order, Target::FromCPU, !inService);
3122810SN/A    }
3134665SN/A}
3144665SN/A
3154902SN/Abool
3164902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order)
3174665SN/A{
31810725Sandreas.hansson@arm.com    DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
3199663Suri.wiener@arm.com            pkt->cmdString(), pkt->getAddr(), pkt->getSize());
3204910SN/A    if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
3214903SN/A        // Request has not been issued yet, or it's been issued
3224903SN/A        // locally but is buffered unissued at some downstream cache
3234903SN/A        // which is forwarding us this snoop.  Either way, the packet
3244903SN/A        // we're snooping logically precedes this MSHR's request, so
3254903SN/A        // the snoop has no impact on the MSHR, but must be processed
3264903SN/A        // in the standard way by the cache.  The only exception is
3274903SN/A        // that if we're an L2+ cache buffering an UpgradeReq from a
3284903SN/A        // higher-level cache, and the snoop is invalidating, then our
3294903SN/A        // buffered upgrades must be converted to read exclusives,
3304903SN/A        // since the upper-level cache no longer has a valid copy.
3314903SN/A        // That is, even though the upper-level cache got out on its
3324903SN/A        // local bus first, some other invalidating transaction
3334903SN/A        // reached the global bus before the upgrade did.
3344903SN/A        if (pkt->needsExclusive()) {
3359725Sandreas.hansson@arm.com            targets.replaceUpgrades();
3369725Sandreas.hansson@arm.com            deferredTargets.replaceUpgrades();
3374903SN/A        }
3384903SN/A
3394902SN/A        return false;
3404902SN/A    }
3414665SN/A
3424903SN/A    // From here on down, the request issued by this MSHR logically
3434903SN/A    // precedes the request we're snooping.
3444903SN/A    if (pkt->needsExclusive()) {
3454903SN/A        // snooped request still precedes the re-request we'll have to
3464903SN/A        // issue for deferred targets, if any...
3479725Sandreas.hansson@arm.com        deferredTargets.replaceUpgrades();
3484903SN/A    }
3494903SN/A
3507667Ssteve.reinhardt@amd.com    if (hasPostInvalidate()) {
3514665SN/A        // a prior snoop has already appended an invalidation, so
3524903SN/A        // logically we don't have the block anymore; no need for
3534903SN/A        // further snooping.
3544902SN/A        return true;
3554665SN/A    }
3564665SN/A
3577667Ssteve.reinhardt@amd.com    if (isPendingDirty() || pkt->isInvalidate()) {
3587667Ssteve.reinhardt@amd.com        // We need to save and replay the packet in two cases:
3597667Ssteve.reinhardt@amd.com        // 1. We're awaiting an exclusive copy, so ownership is pending,
3607667Ssteve.reinhardt@amd.com        //    and we need to respond after we receive data.
3617667Ssteve.reinhardt@amd.com        // 2. It's an invalidation (e.g., UpgradeReq), and we need
3627667Ssteve.reinhardt@amd.com        //    to forward the snoop up the hierarchy after the current
3637667Ssteve.reinhardt@amd.com        //    transaction completes.
3647667Ssteve.reinhardt@amd.com
3658931Sandreas.hansson@arm.com        // Actual target device (typ. a memory) will delete the
3667667Ssteve.reinhardt@amd.com        // packet on reception, so we need to save a copy here.
36710571Sandreas.hansson@arm.com
36810571Sandreas.hansson@arm.com        // Clear flags and also allocate new data as the original
36910571Sandreas.hansson@arm.com        // packet data storage may have been deleted by the time we
37010571Sandreas.hansson@arm.com        // get to send this packet.
37110826Sstephan.diestelhorst@ARM.com        PacketPtr cp_pkt = nullptr;
3724670SN/A
37310582SCurtis.Dunham@arm.com        if (isPendingDirty()) {
37410826Sstephan.diestelhorst@ARM.com            // Case 1: The new packet will need to get the response from the
37510826Sstephan.diestelhorst@ARM.com            // MSHR already queued up here
37610826Sstephan.diestelhorst@ARM.com            cp_pkt = new Packet(pkt, true, true);
3774670SN/A            pkt->assertMemInhibit();
37810821Sandreas.hansson@arm.com            // in the case of an uncacheable request there is no need
37910821Sandreas.hansson@arm.com            // to set the exclusive flag, but since the recipient does
38010821Sandreas.hansson@arm.com            // not care there is no harm in doing so
3814916SN/A            pkt->setSupplyExclusive();
38210826Sstephan.diestelhorst@ARM.com        } else {
38310826Sstephan.diestelhorst@ARM.com            // Case 2: We only need to buffer the packet for information
38410826Sstephan.diestelhorst@ARM.com            // purposes; the original request can proceed without waiting
38510826Sstephan.diestelhorst@ARM.com            // => Create a copy of the request, as that may get deallocated as
38610826Sstephan.diestelhorst@ARM.com            // well
38710826Sstephan.diestelhorst@ARM.com            cp_pkt = new Packet(new Request(*pkt->req), pkt->cmd);
38810826Sstephan.diestelhorst@ARM.com            DPRINTF(Cache, "Copying packet %p -> %p and request %p -> %p\n",
38910826Sstephan.diestelhorst@ARM.com                    pkt, cp_pkt, pkt->req, cp_pkt->req);
3904670SN/A        }
39110826Sstephan.diestelhorst@ARM.com        targets.add(cp_pkt, curTick(), _order, Target::FromSnoop,
39210826Sstephan.diestelhorst@ARM.com                    downstreamPending && targets.needsExclusive);
3934670SN/A
3944670SN/A        if (pkt->needsExclusive()) {
3954670SN/A            // This transaction will take away our pending copy
3967667Ssteve.reinhardt@amd.com            postInvalidate = true;
3974670SN/A        }
3987667Ssteve.reinhardt@amd.com    }
3997667Ssteve.reinhardt@amd.com
40010821Sandreas.hansson@arm.com    if (!pkt->needsExclusive() && !pkt->req->isUncacheable()) {
4017667Ssteve.reinhardt@amd.com        // This transaction will get a read-shared copy, downgrading
4027667Ssteve.reinhardt@amd.com        // our copy if we had an exclusive one
4037667Ssteve.reinhardt@amd.com        postDowngrade = true;
4044670SN/A        pkt->assertShared();
4054667SN/A    }
4064902SN/A
4074902SN/A    return true;
4084665SN/A}
4094665SN/A
4104665SN/A
4114665SN/Abool
4124665SN/AMSHR::promoteDeferredTargets()
4134665SN/A{
4149725Sandreas.hansson@arm.com    assert(targets.empty());
4159725Sandreas.hansson@arm.com    if (deferredTargets.empty()) {
4164665SN/A        return false;
4174665SN/A    }
4184665SN/A
4194903SN/A    // swap targets & deferredTargets lists
4209725Sandreas.hansson@arm.com    std::swap(targets, deferredTargets);
4214903SN/A
4224903SN/A    // clear deferredTargets flags
4239725Sandreas.hansson@arm.com    deferredTargets.resetFlags();
4244903SN/A
4259725Sandreas.hansson@arm.com    order = targets.front().order;
4269725Sandreas.hansson@arm.com    readyTime = std::max(curTick(), targets.front().readyTime);
4274665SN/A
4284665SN/A    return true;
4292810SN/A}
4302810SN/A
4312810SN/A
4322810SN/Avoid
43311177Sandreas.hansson@arm.comMSHR::promoteExclusive()
4344668SN/A{
43511177Sandreas.hansson@arm.com    if (deferredTargets.needsExclusive &&
43611177Sandreas.hansson@arm.com        !(hasPostInvalidate() || hasPostDowngrade())) {
4375270SN/A        // We got an exclusive response, but we have deferred targets
4385270SN/A        // which are waiting to request an exclusive copy (not because
4395270SN/A        // of a pending invalidate).  This can happen if the original
4405270SN/A        // request was for a read-only (non-exclusive) block, but we
4415270SN/A        // got an exclusive copy anyway because of the E part of the
4425270SN/A        // MOESI/MESI protocol.  Since we got the exclusive copy
4435270SN/A        // there's no need to defer the targets, so move them up to
4445270SN/A        // the regular target list.
4459725Sandreas.hansson@arm.com        assert(!targets.needsExclusive);
4469725Sandreas.hansson@arm.com        targets.needsExclusive = true;
4475318SN/A        // if any of the deferred targets were upper-level cache
4485318SN/A        // requests marked downstreamPending, need to clear that
4495318SN/A        assert(!downstreamPending);  // not pending here anymore
4509725Sandreas.hansson@arm.com        deferredTargets.clearDownstreamPending();
4515270SN/A        // this clears out deferredTargets too
4529725Sandreas.hansson@arm.com        targets.splice(targets.end(), deferredTargets);
4539725Sandreas.hansson@arm.com        deferredTargets.resetFlags();
4545270SN/A    }
4554668SN/A}
4564668SN/A
4574668SN/A
4585314SN/Abool
4595314SN/AMSHR::checkFunctional(PacketPtr pkt)
4605314SN/A{
4615314SN/A    // For printing, we treat the MSHR as a whole as single entity.
4625314SN/A    // For other requests, we iterate over the individual targets
4635314SN/A    // since that's where the actual data lies.
4645314SN/A    if (pkt->isPrint()) {
46510764Sandreas.hansson@arm.com        pkt->checkFunctional(this, blkAddr, isSecure, blkSize, NULL);
4665314SN/A        return false;
4675314SN/A    } else {
4689725Sandreas.hansson@arm.com        return (targets.checkFunctional(pkt) ||
4699725Sandreas.hansson@arm.com                deferredTargets.checkFunctional(pkt));
4705314SN/A    }
4715314SN/A}
4725314SN/A
4735314SN/A
4744668SN/Avoid
4755314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
4762810SN/A{
47710725Sandreas.hansson@arm.com    ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
47810764Sandreas.hansson@arm.com             prefix, blkAddr, blkAddr + blkSize - 1,
47910028SGiacomo.Gabrielli@arm.com             isSecure ? "s" : "ns",
4805730SSteve.Reinhardt@amd.com             isForward ? "Forward" : "",
4815730SSteve.Reinhardt@amd.com             isForwardNoResponse() ? "ForwNoResp" : "",
4825314SN/A             needsExclusive() ? "Excl" : "",
4835314SN/A             _isUncacheable ? "Unc" : "",
4845314SN/A             inService ? "InSvc" : "",
4855314SN/A             downstreamPending ? "DwnPend" : "",
4867667Ssteve.reinhardt@amd.com             hasPostInvalidate() ? "PostInv" : "",
4877667Ssteve.reinhardt@amd.com             hasPostDowngrade() ? "PostDowngr" : "");
4882810SN/A
4895314SN/A    ccprintf(os, "%s  Targets:\n", prefix);
4909725Sandreas.hansson@arm.com    targets.print(os, verbosity, prefix + "    ");
4919725Sandreas.hansson@arm.com    if (!deferredTargets.empty()) {
4925314SN/A        ccprintf(os, "%s  Deferred Targets:\n", prefix);
4939725Sandreas.hansson@arm.com        deferredTargets.print(os, verbosity, prefix + "      ");
4942810SN/A    }
4952810SN/A}
4962810SN/A
4979663Suri.wiener@arm.comstd::string
4989663Suri.wiener@arm.comMSHR::print() const
4999663Suri.wiener@arm.com{
5009663Suri.wiener@arm.com    ostringstream str;
5019663Suri.wiener@arm.com    print(str);
5029663Suri.wiener@arm.com    return str.str();
5039663Suri.wiener@arm.com}
504