mshr.cc revision 10826
12810SN/A/*
210764Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015 ARM Limited
39663Suri.wiener@arm.com * All rights reserved.
49663Suri.wiener@arm.com *
59663Suri.wiener@arm.com * The license below extends only to copyright in the software and shall
69663Suri.wiener@arm.com * not be construed as granting a license to any other intellectual
79663Suri.wiener@arm.com * property including but not limited to intellectual property relating
89663Suri.wiener@arm.com * to a hardware implementation of the functionality of the software
99663Suri.wiener@arm.com * licensed hereunder.  You may use the software subject to the license
109663Suri.wiener@arm.com * terms below provided that you ensure that this notice is replicated
119663Suri.wiener@arm.com * unmodified and in its entirety in all distributions of the software,
129663Suri.wiener@arm.com * modified or unmodified, in source code or in binary form.
139663Suri.wiener@arm.com *
142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
157636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
162810SN/A * All rights reserved.
172810SN/A *
182810SN/A * Redistribution and use in source and binary forms, with or without
192810SN/A * modification, are permitted provided that the following conditions are
202810SN/A * met: redistributions of source code must retain the above copyright
212810SN/A * notice, this list of conditions and the following disclaimer;
222810SN/A * redistributions in binary form must reproduce the above copyright
232810SN/A * notice, this list of conditions and the following disclaimer in the
242810SN/A * documentation and/or other materials provided with the distribution;
252810SN/A * neither the name of the copyright holders nor the names of its
262810SN/A * contributors may be used to endorse or promote products derived from
272810SN/A * this software without specific prior written permission.
282810SN/A *
292810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402810SN/A *
412810SN/A * Authors: Erik Hallnor
422810SN/A *          Dave Greene
432810SN/A */
442810SN/A
452810SN/A/**
462810SN/A * @file
472810SN/A * Miss Status and Handling Register (MSHR) definitions.
482810SN/A */
492810SN/A
506216Snate@binkert.org#include <algorithm>
516216Snate@binkert.org#include <cassert>
522810SN/A#include <string>
532810SN/A#include <vector>
542810SN/A
556216Snate@binkert.org#include "base/misc.hh"
566216Snate@binkert.org#include "base/types.hh"
578232Snate@binkert.org#include "debug/Cache.hh"
586216Snate@binkert.org#include "mem/cache/cache.hh"
595338Sstever@gmail.com#include "mem/cache/mshr.hh"
606216Snate@binkert.org#include "sim/core.hh"
612810SN/A
622810SN/Ausing namespace std;
632810SN/A
649725Sandreas.hansson@arm.comMSHR::MSHR() : readyTime(0), _isUncacheable(false), downstreamPending(false),
6510582SCurtis.Dunham@arm.com               pendingDirty(false),
6610503SCurtis.Dunham@arm.com               postInvalidate(false), postDowngrade(false),
6710764Sandreas.hansson@arm.com               queue(NULL), order(0), blkAddr(0),
6810764Sandreas.hansson@arm.com               blkSize(0), isSecure(false), inService(false),
6911197Sandreas.hansson@arm.com               isForward(false), threadNum(InvalidThreadID), data(NULL)
7011197Sandreas.hansson@arm.com{
712810SN/A}
722810SN/A
732810SN/A
744903SN/AMSHR::TargetList::TargetList()
754903SN/A    : needsExclusive(false), hasUpgrade(false)
764903SN/A{}
774903SN/A
784903SN/A
794903SN/Ainline void
804903SN/AMSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
814908SN/A                      Counter order, Target::Source source, bool markPending)
825875Ssteve.reinhardt@amd.com{
834903SN/A    if (source != Target::FromSnoop) {
845875Ssteve.reinhardt@amd.com        if (pkt->needsExclusive()) {
854903SN/A            needsExclusive = true;
864903SN/A        }
874903SN/A
884903SN/A        // StoreCondReq is effectively an upgrade if it's in an MSHR
897669Ssteve.reinhardt@amd.com        // since it would have been failed already if we didn't have a
907669Ssteve.reinhardt@amd.com        // read-only copy
917669Ssteve.reinhardt@amd.com        if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
927669Ssteve.reinhardt@amd.com            hasUpgrade = true;
934903SN/A        }
944903SN/A    }
955318SN/A
964908SN/A    if (markPending) {
975318SN/A        // Iterate over the SenderState stack and see if we find
989543Ssascha.bischoff@arm.com        // an MSHR entry. If we do, set the downstreamPending
999543Ssascha.bischoff@arm.com        // flag. Otherwise, do nothing.
1009543Ssascha.bischoff@arm.com        MSHR *mshr = pkt->findNextSenderState<MSHR>();
1019543Ssascha.bischoff@arm.com        if (mshr != NULL) {
1024908SN/A            assert(!mshr->downstreamPending);
1034908SN/A            mshr->downstreamPending = true;
1044908SN/A        }
10511083Sandreas.hansson@arm.com    }
10611083Sandreas.hansson@arm.com
10711083Sandreas.hansson@arm.com    emplace_back(Target(pkt, readyTime, order, source, markPending));
1084908SN/A}
1094903SN/A
1104903SN/A
11110922Sandreas.hansson@arm.comstatic void
1124903SN/AreplaceUpgrade(PacketPtr pkt)
1134903SN/A{
1144903SN/A    if (pkt->cmd == MemCmd::UpgradeReq) {
1157667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::ReadExReq;
1167667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
1177667Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
1187667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::SCUpgradeFailReq;
1197667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
1207667Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::StoreCondReq) {
1217667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::StoreCondFailReq;
1227667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
1237667Ssteve.reinhardt@amd.com    }
1247669Ssteve.reinhardt@amd.com}
1257669Ssteve.reinhardt@amd.com
1267669Ssteve.reinhardt@amd.com
1277667Ssteve.reinhardt@amd.comvoid
1287667Ssteve.reinhardt@amd.comMSHR::TargetList::replaceUpgrades()
1297667Ssteve.reinhardt@amd.com{
1307667Ssteve.reinhardt@amd.com    if (!hasUpgrade)
1314903SN/A        return;
1324903SN/A
1334903SN/A    for (auto& t : *this) {
1344903SN/A        replaceUpgrade(t.pkt);
1354903SN/A    }
1364903SN/A
13710766Sandreas.hansson@arm.com    hasUpgrade = false;
13810766Sandreas.hansson@arm.com}
1394903SN/A
1404903SN/A
1414903SN/Avoid
1424903SN/AMSHR::TargetList::clearDownstreamPending()
1434903SN/A{
1444903SN/A    for (auto& t : *this) {
1452810SN/A        if (t.markedPending) {
1464908SN/A            // Iterate over the SenderState stack and see if we find
1474908SN/A            // an MSHR entry. If we find one, clear the
14810766Sandreas.hansson@arm.com            // downstreamPending flag by calling
14910766Sandreas.hansson@arm.com            // clearDownstreamPending(). This recursively clears the
1509543Ssascha.bischoff@arm.com            // downstreamPending flag in all caches this packet has
1519543Ssascha.bischoff@arm.com            // passed through.
1529543Ssascha.bischoff@arm.com            MSHR *mshr = t.pkt->findNextSenderState<MSHR>();
1539543Ssascha.bischoff@arm.com            if (mshr != NULL) {
1549543Ssascha.bischoff@arm.com                mshr->clearDownstreamPending();
1559543Ssascha.bischoff@arm.com            }
15610766Sandreas.hansson@arm.com        }
1575318SN/A    }
1585318SN/A}
1595318SN/A
1604908SN/A
1614908SN/Abool
1624908SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt)
1634908SN/A{
1644908SN/A    for (auto& t : *this) {
1654920SN/A        if (pkt->checkFunctional(t.pkt)) {
1664920SN/A            return true;
1674920SN/A        }
16810766Sandreas.hansson@arm.com    }
16910766Sandreas.hansson@arm.com
1704920SN/A    return false;
1714920SN/A}
1724920SN/A
1734920SN/A
1744920SN/Avoid
1754920SN/AMSHR::TargetList::print(std::ostream &os, int verbosity,
1764920SN/A                        const std::string &prefix) const
1774920SN/A{
1784908SN/A    for (auto& t : *this) {
17910766Sandreas.hansson@arm.com        const char *s;
18010766Sandreas.hansson@arm.com        switch (t.source) {
1815314SN/A          case Target::FromCPU:
18210766Sandreas.hansson@arm.com            s = "FromCPU";
1835875Ssteve.reinhardt@amd.com            break;
18410766Sandreas.hansson@arm.com          case Target::FromSnoop:
1858988SAli.Saidi@ARM.com            s = "FromSnoop";
1868988SAli.Saidi@ARM.com            break;
1878988SAli.Saidi@ARM.com          case Target::FromPrefetcher:
1888988SAli.Saidi@ARM.com            s = "FromPrefetcher";
1898988SAli.Saidi@ARM.com            break;
1908988SAli.Saidi@ARM.com          default:
1918988SAli.Saidi@ARM.com            s = "";
1928988SAli.Saidi@ARM.com            break;
1938988SAli.Saidi@ARM.com        }
1948988SAli.Saidi@ARM.com        ccprintf(os, "%s%s: ", prefix, s);
1958988SAli.Saidi@ARM.com        t.pkt->print(os, verbosity, "");
1968988SAli.Saidi@ARM.com    }
1975875Ssteve.reinhardt@amd.com}
1985875Ssteve.reinhardt@amd.com
19910766Sandreas.hansson@arm.com
2005314SN/Avoid
2015314SN/AMSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
2025314SN/A               Tick when_ready, Counter _order)
2035314SN/A{
2045314SN/A    blkAddr = blk_addr;
20510764Sandreas.hansson@arm.com    blkSize = blk_size;
20611197Sandreas.hansson@arm.com    isSecure = target->isSecure();
2072810SN/A    readyTime = when_ready;
20810764Sandreas.hansson@arm.com    order = _order;
20910764Sandreas.hansson@arm.com    assert(target);
21010028SGiacomo.Gabrielli@arm.com    isForward = false;
21110764Sandreas.hansson@arm.com    _isUncacheable = target->req->isUncacheable();
2124666SN/A    inService = false;
2134626SN/A    downstreamPending = false;
2145730SSteve.Reinhardt@amd.com    threadNum = 0;
21511197Sandreas.hansson@arm.com    assert(targets.isReset());
2164626SN/A    // Don't know of a case where we would allocate a new MSHR for a
2174626SN/A    // snoop (mem-side request), so set source according to request here
2184908SN/A    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
2194626SN/A        Target::FromPrefetcher : Target::FromCPU;
2209725Sandreas.hansson@arm.com    targets.add(target, when_ready, _order, source, true);
2214626SN/A    assert(deferredTargets.isReset());
2225875Ssteve.reinhardt@amd.com    data = NULL;
2235875Ssteve.reinhardt@amd.com}
2245875Ssteve.reinhardt@amd.com
22510764Sandreas.hansson@arm.com
2269725Sandreas.hansson@arm.comvoid
2274668SN/AMSHR::clearDownstreamPending()
2282810SN/A{
2292810SN/A    assert(downstreamPending);
2304908SN/A    downstreamPending = false;
2315318SN/A    // recursively clear flag on any MSHRs we will be forwarding
2325318SN/A    // responses to
2335318SN/A    targets.clearDownstreamPending();
2345318SN/A}
2355318SN/A
2365318SN/Abool
2375318SN/AMSHR::markInService(bool pending_dirty_resp)
2389725Sandreas.hansson@arm.com{
2395318SN/A    assert(!inService);
2405318SN/A    if (isForwardNoResponse()) {
2414908SN/A        // we just forwarded the request packet & don't expect a
24210679Sandreas.hansson@arm.com        // response, so get rid of it
2434908SN/A        assert(getNumTargets() == 1);
2444908SN/A        popTarget();
2455730SSteve.Reinhardt@amd.com        return true;
2464908SN/A    }
2474908SN/A
2484908SN/A    inService = true;
2494908SN/A    pendingDirty = targets.needsExclusive || pending_dirty_resp;
2504908SN/A    postInvalidate = postDowngrade = false;
2514908SN/A
25210424Sandreas.hansson@arm.com    if (!downstreamPending) {
2534908SN/A        // let upstream caches know that the request has made it to a
25410679Sandreas.hansson@arm.com        // level where it's going to get a response
2557667Ssteve.reinhardt@amd.com        targets.clearDownstreamPending();
2567667Ssteve.reinhardt@amd.com    }
2574908SN/A    return false;
2584908SN/A}
2594908SN/A
2609725Sandreas.hansson@arm.com
2614908SN/Avoid
2624908SN/AMSHR::deallocate()
2634908SN/A{
2644908SN/A    assert(targets.empty());
2654908SN/A    targets.resetFlags();
2662810SN/A    assert(deferredTargets.isReset());
2672810SN/A    inService = false;
2682810SN/A}
2699725Sandreas.hansson@arm.com
2709725Sandreas.hansson@arm.com/*
2719725Sandreas.hansson@arm.com * Adds a target to an MSHR
2722810SN/A */
2732810SN/Avoid
2742810SN/AMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order)
2752810SN/A{
2762810SN/A    // assume we'd never issue a prefetch when we've got an
2772810SN/A    // outstanding miss
2782810SN/A    assert(pkt->cmd != MemCmd::HardPFReq);
27911197Sandreas.hansson@arm.com
28011197Sandreas.hansson@arm.com    // uncacheable accesses always allocate a new MSHR, and cacheable
2812810SN/A    // accesses ignore any uncacheable MSHRs, thus we should never
28210768Sandreas.hansson@arm.com    // have targets addded if originally allocated uncacheable
28310768Sandreas.hansson@arm.com    assert(!_isUncacheable);
28410768Sandreas.hansson@arm.com
28510768Sandreas.hansson@arm.com    // if there's a request already in service for this MSHR, we will
28610768Sandreas.hansson@arm.com    // have to defer the new target until after the response if any of
28710768Sandreas.hansson@arm.com    // the following are true:
28810768Sandreas.hansson@arm.com    // - there are other targets already deferred
28910768Sandreas.hansson@arm.com    // - there's a pending invalidate to be applied after the response
29010768Sandreas.hansson@arm.com    //   comes back (but before this target is processed)
29111197Sandreas.hansson@arm.com    // - this target requires an exclusive block and either we're not
29211197Sandreas.hansson@arm.com    //   getting an exclusive block back or we have already snooped
29311197Sandreas.hansson@arm.com    //   another read request that will downgrade our exclusive block
29411197Sandreas.hansson@arm.com    //   to shared
2954903SN/A    if (inService &&
2964903SN/A        (!deferredTargets.empty() || hasPostInvalidate() ||
2974903SN/A         (pkt->needsExclusive() &&
2984903SN/A          (!isPendingDirty() || hasPostDowngrade() || isForward)))) {
2994903SN/A        // need to put on deferred list
3004903SN/A        if (hasPostInvalidate())
3017667Ssteve.reinhardt@amd.com            replaceUpgrade(pkt);
3027667Ssteve.reinhardt@amd.com        deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true);
3037667Ssteve.reinhardt@amd.com    } else {
3047667Ssteve.reinhardt@amd.com        // No request outstanding, or still OK to append to
3054903SN/A        // outstanding request: append to regular target list.  Only
3069725Sandreas.hansson@arm.com        // mark pending if current request hasn't been issued yet
3077667Ssteve.reinhardt@amd.com        // (isn't in service).
3087667Ssteve.reinhardt@amd.com        targets.add(pkt, whenReady, _order, Target::FromCPU, !inService);
3094903SN/A    }
3107667Ssteve.reinhardt@amd.com}
3117667Ssteve.reinhardt@amd.com
3129725Sandreas.hansson@arm.combool
3134665SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order)
3145318SN/A{
3155318SN/A    DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
3165318SN/A            pkt->cmdString(), pkt->getAddr(), pkt->getSize());
3175318SN/A    if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
3189725Sandreas.hansson@arm.com        // Request has not been issued yet, or it's been issued
3192810SN/A        // locally but is buffered unissued at some downstream cache
3204665SN/A        // which is forwarding us this snoop.  Either way, the packet
3214665SN/A        // we're snooping logically precedes this MSHR's request, so
3224902SN/A        // the snoop has no impact on the MSHR, but must be processed
3234902SN/A        // in the standard way by the cache.  The only exception is
3244665SN/A        // that if we're an L2+ cache buffering an UpgradeReq from a
32510725Sandreas.hansson@arm.com        // higher-level cache, and the snoop is invalidating, then our
3269663Suri.wiener@arm.com        // buffered upgrades must be converted to read exclusives,
3274910SN/A        // since the upper-level cache no longer has a valid copy.
3284903SN/A        // That is, even though the upper-level cache got out on its
3294903SN/A        // local bus first, some other invalidating transaction
3304903SN/A        // reached the global bus before the upgrade did.
3314903SN/A        if (pkt->needsExclusive()) {
3324903SN/A            targets.replaceUpgrades();
3334903SN/A            deferredTargets.replaceUpgrades();
3344903SN/A        }
3354903SN/A
3364903SN/A        return false;
3374903SN/A    }
3384903SN/A
3394903SN/A    // From here on down, the request issued by this MSHR logically
3404903SN/A    // precedes the request we're snooping.
3414903SN/A    if (pkt->needsExclusive()) {
3429725Sandreas.hansson@arm.com        // snooped request still precedes the re-request we'll have to
3439725Sandreas.hansson@arm.com        // issue for deferred targets, if any...
3444903SN/A        deferredTargets.replaceUpgrades();
3454903SN/A    }
3464902SN/A
3474902SN/A    if (hasPostInvalidate()) {
3484665SN/A        // a prior snoop has already appended an invalidation, so
3494903SN/A        // logically we don't have the block anymore; no need for
3504903SN/A        // further snooping.
3514903SN/A        return true;
3524903SN/A    }
3534903SN/A
3549725Sandreas.hansson@arm.com    if (isPendingDirty() || pkt->isInvalidate()) {
3554903SN/A        // We need to save and replay the packet in two cases:
3564903SN/A        // 1. We're awaiting an exclusive copy, so ownership is pending,
3577667Ssteve.reinhardt@amd.com        //    and we need to respond after we receive data.
3584665SN/A        // 2. It's an invalidation (e.g., UpgradeReq), and we need
3594903SN/A        //    to forward the snoop up the hierarchy after the current
3604903SN/A        //    transaction completes.
3614902SN/A
3624665SN/A        // Actual target device (typ. a memory) will delete the
3634665SN/A        // packet on reception, so we need to save a copy here.
3647667Ssteve.reinhardt@amd.com
3657667Ssteve.reinhardt@amd.com        // Clear flags and also allocate new data as the original
3667667Ssteve.reinhardt@amd.com        // packet data storage may have been deleted by the time we
3677667Ssteve.reinhardt@amd.com        // get to send this packet.
3687667Ssteve.reinhardt@amd.com        PacketPtr cp_pkt = nullptr;
3697667Ssteve.reinhardt@amd.com
3707667Ssteve.reinhardt@amd.com        if (isPendingDirty()) {
3717667Ssteve.reinhardt@amd.com            // Case 1: The new packet will need to get the response from the
3728931Sandreas.hansson@arm.com            // MSHR already queued up here
3737667Ssteve.reinhardt@amd.com            cp_pkt = new Packet(pkt, true, true);
37410571Sandreas.hansson@arm.com            pkt->assertMemInhibit();
37510571Sandreas.hansson@arm.com            // in the case of an uncacheable request there is no need
37610571Sandreas.hansson@arm.com            // to set the exclusive flag, but since the recipient does
37710571Sandreas.hansson@arm.com            // not care there is no harm in doing so
37810826Sstephan.diestelhorst@ARM.com            pkt->setSupplyExclusive();
3794670SN/A        } else {
38010582SCurtis.Dunham@arm.com            // Case 2: We only need to buffer the packet for information
38110826Sstephan.diestelhorst@ARM.com            // purposes; the original request can proceed without waiting
38210826Sstephan.diestelhorst@ARM.com            // => Create a copy of the request, as that may get deallocated as
38310826Sstephan.diestelhorst@ARM.com            // well
3844670SN/A            cp_pkt = new Packet(new Request(*pkt->req), pkt->cmd);
38510821Sandreas.hansson@arm.com            DPRINTF(Cache, "Copying packet %p -> %p and request %p -> %p\n",
38610821Sandreas.hansson@arm.com                    pkt, cp_pkt, pkt->req, cp_pkt->req);
38710821Sandreas.hansson@arm.com        }
3884916SN/A        targets.add(cp_pkt, curTick(), _order, Target::FromSnoop,
38910826Sstephan.diestelhorst@ARM.com                    downstreamPending && targets.needsExclusive);
39010826Sstephan.diestelhorst@ARM.com
39110826Sstephan.diestelhorst@ARM.com        if (pkt->needsExclusive()) {
39210826Sstephan.diestelhorst@ARM.com            // This transaction will take away our pending copy
39310826Sstephan.diestelhorst@ARM.com            postInvalidate = true;
39410826Sstephan.diestelhorst@ARM.com        }
39510826Sstephan.diestelhorst@ARM.com    }
39610826Sstephan.diestelhorst@ARM.com
3974670SN/A    if (!pkt->needsExclusive() && !pkt->req->isUncacheable()) {
39810826Sstephan.diestelhorst@ARM.com        // This transaction will get a read-shared copy, downgrading
39910826Sstephan.diestelhorst@ARM.com        // our copy if we had an exclusive one
4004670SN/A        postDowngrade = true;
4014670SN/A        pkt->assertShared();
4024670SN/A    }
4037667Ssteve.reinhardt@amd.com
4044670SN/A    return true;
4057667Ssteve.reinhardt@amd.com}
4067667Ssteve.reinhardt@amd.com
40710821Sandreas.hansson@arm.com
4087667Ssteve.reinhardt@amd.combool
4097667Ssteve.reinhardt@amd.comMSHR::promoteDeferredTargets()
4107667Ssteve.reinhardt@amd.com{
4114670SN/A    assert(targets.empty());
4124667SN/A    if (deferredTargets.empty()) {
4134902SN/A        return false;
4144902SN/A    }
4154665SN/A
4164665SN/A    // swap targets & deferredTargets lists
4174665SN/A    std::swap(targets, deferredTargets);
4184665SN/A
4194665SN/A    // clear deferredTargets flags
4204665SN/A    deferredTargets.resetFlags();
4219725Sandreas.hansson@arm.com
4229725Sandreas.hansson@arm.com    order = targets.front().order;
4234665SN/A    readyTime = std::max(curTick(), targets.front().readyTime);
4244665SN/A
4254665SN/A    return true;
4264903SN/A}
4279725Sandreas.hansson@arm.com
4284903SN/A
4294903SN/Avoid
4309725Sandreas.hansson@arm.comMSHR::handleFill(PacketPtr pkt, CacheBlk *blk)
4314903SN/A{
4329725Sandreas.hansson@arm.com    if (!pkt->sharedAsserted()
4339725Sandreas.hansson@arm.com        && !(hasPostInvalidate() || hasPostDowngrade())
4344665SN/A        && deferredTargets.needsExclusive) {
4354665SN/A        // We got an exclusive response, but we have deferred targets
4362810SN/A        // which are waiting to request an exclusive copy (not because
4372810SN/A        // of a pending invalidate).  This can happen if the original
4382810SN/A        // request was for a read-only (non-exclusive) block, but we
4392810SN/A        // got an exclusive copy anyway because of the E part of the
44011177Sandreas.hansson@arm.com        // MOESI/MESI protocol.  Since we got the exclusive copy
4414668SN/A        // there's no need to defer the targets, so move them up to
44211177Sandreas.hansson@arm.com        // the regular target list.
44311177Sandreas.hansson@arm.com        assert(!targets.needsExclusive);
4445270SN/A        targets.needsExclusive = true;
4455270SN/A        // if any of the deferred targets were upper-level cache
4465270SN/A        // requests marked downstreamPending, need to clear that
4475270SN/A        assert(!downstreamPending);  // not pending here anymore
4485270SN/A        deferredTargets.clearDownstreamPending();
4495270SN/A        // this clears out deferredTargets too
4505270SN/A        targets.splice(targets.end(), deferredTargets);
4515270SN/A        deferredTargets.resetFlags();
4529725Sandreas.hansson@arm.com    }
4539725Sandreas.hansson@arm.com}
4545318SN/A
4555318SN/A
4565318SN/Abool
4579725Sandreas.hansson@arm.comMSHR::checkFunctional(PacketPtr pkt)
4585270SN/A{
4599725Sandreas.hansson@arm.com    // For printing, we treat the MSHR as a whole as single entity.
4609725Sandreas.hansson@arm.com    // For other requests, we iterate over the individual targets
4615270SN/A    // since that's where the actual data lies.
4624668SN/A    if (pkt->isPrint()) {
4634668SN/A        pkt->checkFunctional(this, blkAddr, isSecure, blkSize, NULL);
4644668SN/A        return false;
4655314SN/A    } else {
4665314SN/A        return (targets.checkFunctional(pkt) ||
4675314SN/A                deferredTargets.checkFunctional(pkt));
4685314SN/A    }
4695314SN/A}
4705314SN/A
4715314SN/A
47210764Sandreas.hansson@arm.comvoid
4735314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
4745314SN/A{
4759725Sandreas.hansson@arm.com    ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
4769725Sandreas.hansson@arm.com             prefix, blkAddr, blkAddr + blkSize - 1,
4775314SN/A             isSecure ? "s" : "ns",
4785314SN/A             isForward ? "Forward" : "",
4795314SN/A             isForwardNoResponse() ? "ForwNoResp" : "",
4805314SN/A             needsExclusive() ? "Excl" : "",
4814668SN/A             _isUncacheable ? "Unc" : "",
4825314SN/A             inService ? "InSvc" : "",
4832810SN/A             downstreamPending ? "DwnPend" : "",
48410725Sandreas.hansson@arm.com             hasPostInvalidate() ? "PostInv" : "",
48510764Sandreas.hansson@arm.com             hasPostDowngrade() ? "PostDowngr" : "");
48610028SGiacomo.Gabrielli@arm.com
4875730SSteve.Reinhardt@amd.com    ccprintf(os, "%s  Targets:\n", prefix);
48811197Sandreas.hansson@arm.com    targets.print(os, verbosity, prefix + "    ");
4895730SSteve.Reinhardt@amd.com    if (!deferredTargets.empty()) {
4905314SN/A        ccprintf(os, "%s  Deferred Targets:\n", prefix);
4915314SN/A        deferredTargets.print(os, verbosity, prefix + "      ");
4925314SN/A    }
4935314SN/A}
4947667Ssteve.reinhardt@amd.com
4957667Ssteve.reinhardt@amd.comstd::string
4962810SN/AMSHR::print() const
4975314SN/A{
4989725Sandreas.hansson@arm.com    ostringstream str;
4999725Sandreas.hansson@arm.com    print(str);
5005314SN/A    return str.str();
5019725Sandreas.hansson@arm.com}
5022810SN/A