mshr.cc revision 10582
12810SN/A/*
210028SGiacomo.Gabrielli@arm.com * Copyright (c) 2012-2013 ARM Limited
39663Suri.wiener@arm.com * All rights reserved.
49663Suri.wiener@arm.com *
59663Suri.wiener@arm.com * The license below extends only to copyright in the software and shall
69663Suri.wiener@arm.com * not be construed as granting a license to any other intellectual
79663Suri.wiener@arm.com * property including but not limited to intellectual property relating
89663Suri.wiener@arm.com * to a hardware implementation of the functionality of the software
99663Suri.wiener@arm.com * licensed hereunder.  You may use the software subject to the license
109663Suri.wiener@arm.com * terms below provided that you ensure that this notice is replicated
119663Suri.wiener@arm.com * unmodified and in its entirety in all distributions of the software,
129663Suri.wiener@arm.com * modified or unmodified, in source code or in binary form.
139663Suri.wiener@arm.com *
142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
157636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
162810SN/A * All rights reserved.
172810SN/A *
182810SN/A * Redistribution and use in source and binary forms, with or without
192810SN/A * modification, are permitted provided that the following conditions are
202810SN/A * met: redistributions of source code must retain the above copyright
212810SN/A * notice, this list of conditions and the following disclaimer;
222810SN/A * redistributions in binary form must reproduce the above copyright
232810SN/A * notice, this list of conditions and the following disclaimer in the
242810SN/A * documentation and/or other materials provided with the distribution;
252810SN/A * neither the name of the copyright holders nor the names of its
262810SN/A * contributors may be used to endorse or promote products derived from
272810SN/A * this software without specific prior written permission.
282810SN/A *
292810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402810SN/A *
412810SN/A * Authors: Erik Hallnor
422810SN/A *          Dave Greene
432810SN/A */
442810SN/A
452810SN/A/**
462810SN/A * @file
472810SN/A * Miss Status and Handling Register (MSHR) definitions.
482810SN/A */
492810SN/A
506216Snate@binkert.org#include <algorithm>
516216Snate@binkert.org#include <cassert>
522810SN/A#include <string>
532810SN/A#include <vector>
542810SN/A
556216Snate@binkert.org#include "base/misc.hh"
566216Snate@binkert.org#include "base/types.hh"
578232Snate@binkert.org#include "debug/Cache.hh"
586216Snate@binkert.org#include "mem/cache/cache.hh"
595338Sstever@gmail.com#include "mem/cache/mshr.hh"
606216Snate@binkert.org#include "sim/core.hh"
612810SN/A
622810SN/Ausing namespace std;
632810SN/A
649725Sandreas.hansson@arm.comMSHR::MSHR() : readyTime(0), _isUncacheable(false), downstreamPending(false),
6510582SCurtis.Dunham@arm.com               pendingDirty(false),
6610503SCurtis.Dunham@arm.com               postInvalidate(false), postDowngrade(false),
6710582SCurtis.Dunham@arm.com               queue(NULL), order(0), addr(0),
6810503SCurtis.Dunham@arm.com               size(0), isSecure(false), inService(false),
6910503SCurtis.Dunham@arm.com               isForward(false), threadNum(InvalidThreadID), data(NULL)
702810SN/A{
712810SN/A}
722810SN/A
734903SN/A
744903SN/AMSHR::TargetList::TargetList()
754903SN/A    : needsExclusive(false), hasUpgrade(false)
764903SN/A{}
774903SN/A
784903SN/A
794903SN/Ainline void
804908SN/AMSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
815875Ssteve.reinhardt@amd.com                      Counter order, Target::Source source, bool markPending)
824903SN/A{
835875Ssteve.reinhardt@amd.com    if (source != Target::FromSnoop) {
844903SN/A        if (pkt->needsExclusive()) {
854903SN/A            needsExclusive = true;
864903SN/A        }
874903SN/A
887669Ssteve.reinhardt@amd.com        // StoreCondReq is effectively an upgrade if it's in an MSHR
897669Ssteve.reinhardt@amd.com        // since it would have been failed already if we didn't have a
907669Ssteve.reinhardt@amd.com        // read-only copy
917669Ssteve.reinhardt@amd.com        if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
924903SN/A            hasUpgrade = true;
934903SN/A        }
945318SN/A    }
954908SN/A
965318SN/A    if (markPending) {
979543Ssascha.bischoff@arm.com        // Iterate over the SenderState stack and see if we find
989543Ssascha.bischoff@arm.com        // an MSHR entry. If we do, set the downstreamPending
999543Ssascha.bischoff@arm.com        // flag. Otherwise, do nothing.
1009543Ssascha.bischoff@arm.com        MSHR *mshr = pkt->findNextSenderState<MSHR>();
1014908SN/A        if (mshr != NULL) {
1024908SN/A            assert(!mshr->downstreamPending);
1034908SN/A            mshr->downstreamPending = true;
1044908SN/A        }
1054903SN/A    }
1064903SN/A
1075875Ssteve.reinhardt@amd.com    push_back(Target(pkt, readyTime, order, source, markPending));
1084903SN/A}
1094903SN/A
1104903SN/A
1117667Ssteve.reinhardt@amd.comstatic void
1127667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt)
1137667Ssteve.reinhardt@amd.com{
1147667Ssteve.reinhardt@amd.com    if (pkt->cmd == MemCmd::UpgradeReq) {
1157667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::ReadExReq;
1167667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
1177667Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
1187667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::SCUpgradeFailReq;
1197667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
1207669Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::StoreCondReq) {
1217669Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::StoreCondFailReq;
1227669Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
1237667Ssteve.reinhardt@amd.com    }
1247667Ssteve.reinhardt@amd.com}
1257667Ssteve.reinhardt@amd.com
1267667Ssteve.reinhardt@amd.com
1274903SN/Avoid
1284903SN/AMSHR::TargetList::replaceUpgrades()
1294903SN/A{
1304903SN/A    if (!hasUpgrade)
1314903SN/A        return;
1324903SN/A
1334903SN/A    Iterator end_i = end();
1344903SN/A    for (Iterator i = begin(); i != end_i; ++i) {
1357667Ssteve.reinhardt@amd.com        replaceUpgrade(i->pkt);
1364903SN/A    }
1374903SN/A
1384903SN/A    hasUpgrade = false;
1394903SN/A}
1404903SN/A
1414903SN/A
1422810SN/Avoid
1434908SN/AMSHR::TargetList::clearDownstreamPending()
1444908SN/A{
1454908SN/A    Iterator end_i = end();
1464908SN/A    for (Iterator i = begin(); i != end_i; ++i) {
1475318SN/A        if (i->markedPending) {
1489543Ssascha.bischoff@arm.com            // Iterate over the SenderState stack and see if we find
1499543Ssascha.bischoff@arm.com            // an MSHR entry. If we find one, clear the
1509543Ssascha.bischoff@arm.com            // downstreamPending flag by calling
1519543Ssascha.bischoff@arm.com            // clearDownstreamPending(). This recursively clears the
1529543Ssascha.bischoff@arm.com            // downstreamPending flag in all caches this packet has
1539543Ssascha.bischoff@arm.com            // passed through.
1549543Ssascha.bischoff@arm.com            MSHR *mshr = i->pkt->findNextSenderState<MSHR>();
1555318SN/A            if (mshr != NULL) {
1565318SN/A                mshr->clearDownstreamPending();
1575318SN/A            }
1584908SN/A        }
1594908SN/A    }
1604908SN/A}
1614908SN/A
1624908SN/A
1634920SN/Abool
1644920SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt)
1654920SN/A{
1664920SN/A    Iterator end_i = end();
1674920SN/A    for (Iterator i = begin(); i != end_i; ++i) {
1684920SN/A        if (pkt->checkFunctional(i->pkt)) {
1694920SN/A            return true;
1704920SN/A        }
1714920SN/A    }
1724920SN/A
1734920SN/A    return false;
1744920SN/A}
1754920SN/A
1764920SN/A
1774908SN/Avoid
1785314SN/AMSHR::TargetList::
1795314SN/Aprint(std::ostream &os, int verbosity, const std::string &prefix) const
1805314SN/A{
1815314SN/A    ConstIterator end_i = end();
1825314SN/A    for (ConstIterator i = begin(); i != end_i; ++i) {
1835875Ssteve.reinhardt@amd.com        const char *s;
1845875Ssteve.reinhardt@amd.com        switch (i->source) {
1858988SAli.Saidi@ARM.com          case Target::FromCPU:
1868988SAli.Saidi@ARM.com            s = "FromCPU";
1878988SAli.Saidi@ARM.com            break;
1888988SAli.Saidi@ARM.com          case Target::FromSnoop:
1898988SAli.Saidi@ARM.com            s = "FromSnoop";
1908988SAli.Saidi@ARM.com            break;
1918988SAli.Saidi@ARM.com          case Target::FromPrefetcher:
1928988SAli.Saidi@ARM.com            s = "FromPrefetcher";
1938988SAli.Saidi@ARM.com            break;
1948988SAli.Saidi@ARM.com          default:
1958988SAli.Saidi@ARM.com            s = "";
1968988SAli.Saidi@ARM.com            break;
1975875Ssteve.reinhardt@amd.com        }
1985875Ssteve.reinhardt@amd.com        ccprintf(os, "%s%s: ", prefix, s);
1995314SN/A        i->pkt->print(os, verbosity, "");
2005314SN/A    }
2015314SN/A}
2025314SN/A
2035314SN/A
2045314SN/Avoid
20510028SGiacomo.Gabrielli@arm.comMSHR::allocate(Addr _addr, int _size, PacketPtr target, Tick whenReady,
20610028SGiacomo.Gabrielli@arm.com               Counter _order)
2072810SN/A{
2082885SN/A    addr = _addr;
2094626SN/A    size = _size;
21010028SGiacomo.Gabrielli@arm.com    isSecure = target->isSecure();
2114871SN/A    readyTime = whenReady;
2124666SN/A    order = _order;
2134626SN/A    assert(target);
2145730SSteve.Reinhardt@amd.com    isForward = false;
2154626SN/A    _isUncacheable = target->req->isUncacheable();
2164626SN/A    inService = false;
2174908SN/A    downstreamPending = false;
2184626SN/A    threadNum = 0;
2199725Sandreas.hansson@arm.com    assert(targets.isReset());
2204626SN/A    // Don't know of a case where we would allocate a new MSHR for a
2215875Ssteve.reinhardt@amd.com    // snoop (mem-side request), so set source according to request here
2225875Ssteve.reinhardt@amd.com    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
2235875Ssteve.reinhardt@amd.com        Target::FromPrefetcher : Target::FromCPU;
2249725Sandreas.hansson@arm.com    targets.add(target, whenReady, _order, source, true);
2259725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
2264668SN/A    data = NULL;
2272810SN/A}
2282810SN/A
2294908SN/A
2305318SN/Avoid
2315318SN/AMSHR::clearDownstreamPending()
2325318SN/A{
2335318SN/A    assert(downstreamPending);
2345318SN/A    downstreamPending = false;
2355318SN/A    // recursively clear flag on any MSHRs we will be forwarding
2365318SN/A    // responses to
2379725Sandreas.hansson@arm.com    targets.clearDownstreamPending();
2385318SN/A}
2395318SN/A
2404908SN/Abool
2417667Ssteve.reinhardt@amd.comMSHR::markInService(PacketPtr pkt)
2424908SN/A{
2434908SN/A    assert(!inService);
2445730SSteve.Reinhardt@amd.com    if (isForwardNoResponse()) {
2454908SN/A        // we just forwarded the request packet & don't expect a
2464908SN/A        // response, so get rid of it
2474908SN/A        assert(getNumTargets() == 1);
2484908SN/A        popTarget();
2494908SN/A        return true;
2504908SN/A    }
25110424Sandreas.hansson@arm.com
25210424Sandreas.hansson@arm.com    assert(pkt != NULL);
2534908SN/A    inService = true;
25410582SCurtis.Dunham@arm.com    pendingDirty = targets.needsExclusive ||
25510582SCurtis.Dunham@arm.com                   (!pkt->sharedAsserted() && pkt->memInhibitAsserted());
2567667Ssteve.reinhardt@amd.com    postInvalidate = postDowngrade = false;
2577667Ssteve.reinhardt@amd.com
2584908SN/A    if (!downstreamPending) {
2594908SN/A        // let upstream caches know that the request has made it to a
2604908SN/A        // level where it's going to get a response
2619725Sandreas.hansson@arm.com        targets.clearDownstreamPending();
2624908SN/A    }
2634908SN/A    return false;
2644908SN/A}
2654908SN/A
2664908SN/A
2672810SN/Avoid
2682810SN/AMSHR::deallocate()
2692810SN/A{
2709725Sandreas.hansson@arm.com    assert(targets.empty());
2719725Sandreas.hansson@arm.com    targets.resetFlags();
2729725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
2732810SN/A    inService = false;
2742810SN/A}
2752810SN/A
2762810SN/A/*
2772810SN/A * Adds a target to an MSHR
2782810SN/A */
2792810SN/Avoid
2804903SN/AMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order)
2812810SN/A{
2824903SN/A    // if there's a request already in service for this MSHR, we will
2834903SN/A    // have to defer the new target until after the response if any of
2844903SN/A    // the following are true:
2854903SN/A    // - there are other targets already deferred
2864903SN/A    // - there's a pending invalidate to be applied after the response
2874903SN/A    //   comes back (but before this target is processed)
2887667Ssteve.reinhardt@amd.com    // - this target requires an exclusive block and either we're not
2897667Ssteve.reinhardt@amd.com    //   getting an exclusive block back or we have already snooped
2907667Ssteve.reinhardt@amd.com    //   another read request that will downgrade our exclusive block
2917667Ssteve.reinhardt@amd.com    //   to shared
2925875Ssteve.reinhardt@amd.com
2935875Ssteve.reinhardt@amd.com    // assume we'd never issue a prefetch when we've got an
2945875Ssteve.reinhardt@amd.com    // outstanding miss
2955875Ssteve.reinhardt@amd.com    assert(pkt->cmd != MemCmd::HardPFReq);
2965875Ssteve.reinhardt@amd.com
2974903SN/A    if (inService &&
2989725Sandreas.hansson@arm.com        (!deferredTargets.empty() || hasPostInvalidate() ||
2997667Ssteve.reinhardt@amd.com         (pkt->needsExclusive() &&
3007667Ssteve.reinhardt@amd.com          (!isPendingDirty() || hasPostDowngrade() || isForward)))) {
3014903SN/A        // need to put on deferred list
3027667Ssteve.reinhardt@amd.com        if (hasPostInvalidate())
3037667Ssteve.reinhardt@amd.com            replaceUpgrade(pkt);
3049725Sandreas.hansson@arm.com        deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true);
3054665SN/A    } else {
3065318SN/A        // No request outstanding, or still OK to append to
3075318SN/A        // outstanding request: append to regular target list.  Only
3085318SN/A        // mark pending if current request hasn't been issued yet
3095318SN/A        // (isn't in service).
3109725Sandreas.hansson@arm.com        targets.add(pkt, whenReady, _order, Target::FromCPU, !inService);
3112810SN/A    }
3124665SN/A}
3134665SN/A
3144902SN/Abool
3154902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order)
3164665SN/A{
3179663Suri.wiener@arm.com    DPRINTF(Cache, "%s for %s address %x size %d\n", __func__,
3189663Suri.wiener@arm.com            pkt->cmdString(), pkt->getAddr(), pkt->getSize());
3194910SN/A    if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
3204903SN/A        // Request has not been issued yet, or it's been issued
3214903SN/A        // locally but is buffered unissued at some downstream cache
3224903SN/A        // which is forwarding us this snoop.  Either way, the packet
3234903SN/A        // we're snooping logically precedes this MSHR's request, so
3244903SN/A        // the snoop has no impact on the MSHR, but must be processed
3254903SN/A        // in the standard way by the cache.  The only exception is
3264903SN/A        // that if we're an L2+ cache buffering an UpgradeReq from a
3274903SN/A        // higher-level cache, and the snoop is invalidating, then our
3284903SN/A        // buffered upgrades must be converted to read exclusives,
3294903SN/A        // since the upper-level cache no longer has a valid copy.
3304903SN/A        // That is, even though the upper-level cache got out on its
3314903SN/A        // local bus first, some other invalidating transaction
3324903SN/A        // reached the global bus before the upgrade did.
3334903SN/A        if (pkt->needsExclusive()) {
3349725Sandreas.hansson@arm.com            targets.replaceUpgrades();
3359725Sandreas.hansson@arm.com            deferredTargets.replaceUpgrades();
3364903SN/A        }
3374903SN/A
3384902SN/A        return false;
3394902SN/A    }
3404665SN/A
3414903SN/A    // From here on down, the request issued by this MSHR logically
3424903SN/A    // precedes the request we're snooping.
3434903SN/A    if (pkt->needsExclusive()) {
3444903SN/A        // snooped request still precedes the re-request we'll have to
3454903SN/A        // issue for deferred targets, if any...
3469725Sandreas.hansson@arm.com        deferredTargets.replaceUpgrades();
3474903SN/A    }
3484903SN/A
3497667Ssteve.reinhardt@amd.com    if (hasPostInvalidate()) {
3504665SN/A        // a prior snoop has already appended an invalidation, so
3514903SN/A        // logically we don't have the block anymore; no need for
3524903SN/A        // further snooping.
3534902SN/A        return true;
3544665SN/A    }
3554665SN/A
3567667Ssteve.reinhardt@amd.com    if (isPendingDirty() || pkt->isInvalidate()) {
3577667Ssteve.reinhardt@amd.com        // We need to save and replay the packet in two cases:
3587667Ssteve.reinhardt@amd.com        // 1. We're awaiting an exclusive copy, so ownership is pending,
3597667Ssteve.reinhardt@amd.com        //    and we need to respond after we receive data.
3607667Ssteve.reinhardt@amd.com        // 2. It's an invalidation (e.g., UpgradeReq), and we need
3617667Ssteve.reinhardt@amd.com        //    to forward the snoop up the hierarchy after the current
3627667Ssteve.reinhardt@amd.com        //    transaction completes.
3637667Ssteve.reinhardt@amd.com
3648931Sandreas.hansson@arm.com        // Actual target device (typ. a memory) will delete the
3657667Ssteve.reinhardt@amd.com        // packet on reception, so we need to save a copy here.
36610571Sandreas.hansson@arm.com
36710571Sandreas.hansson@arm.com        // Clear flags and also allocate new data as the original
36810571Sandreas.hansson@arm.com        // packet data storage may have been deleted by the time we
36910571Sandreas.hansson@arm.com        // get to send this packet.
37010571Sandreas.hansson@arm.com        PacketPtr cp_pkt = new Packet(pkt, true, true);
3719725Sandreas.hansson@arm.com        targets.add(cp_pkt, curTick(), _order, Target::FromSnoop,
3729725Sandreas.hansson@arm.com                     downstreamPending && targets.needsExclusive);
3734670SN/A
37410582SCurtis.Dunham@arm.com        if (isPendingDirty()) {
3754670SN/A            pkt->assertMemInhibit();
3764916SN/A            pkt->setSupplyExclusive();
3774670SN/A        }
3784670SN/A
3794670SN/A        if (pkt->needsExclusive()) {
3804670SN/A            // This transaction will take away our pending copy
3817667Ssteve.reinhardt@amd.com            postInvalidate = true;
3824670SN/A        }
3837667Ssteve.reinhardt@amd.com    }
3847667Ssteve.reinhardt@amd.com
3857667Ssteve.reinhardt@amd.com    if (!pkt->needsExclusive()) {
3867667Ssteve.reinhardt@amd.com        // This transaction will get a read-shared copy, downgrading
3877667Ssteve.reinhardt@amd.com        // our copy if we had an exclusive one
3887667Ssteve.reinhardt@amd.com        postDowngrade = true;
3894670SN/A        pkt->assertShared();
3904667SN/A    }
3914902SN/A
3924902SN/A    return true;
3934665SN/A}
3944665SN/A
3954665SN/A
3964665SN/Abool
3974665SN/AMSHR::promoteDeferredTargets()
3984665SN/A{
3999725Sandreas.hansson@arm.com    assert(targets.empty());
4009725Sandreas.hansson@arm.com    if (deferredTargets.empty()) {
4014665SN/A        return false;
4024665SN/A    }
4034665SN/A
4044903SN/A    // swap targets & deferredTargets lists
4059725Sandreas.hansson@arm.com    std::swap(targets, deferredTargets);
4064903SN/A
4074903SN/A    // clear deferredTargets flags
4089725Sandreas.hansson@arm.com    deferredTargets.resetFlags();
4094903SN/A
4109725Sandreas.hansson@arm.com    order = targets.front().order;
4119725Sandreas.hansson@arm.com    readyTime = std::max(curTick(), targets.front().readyTime);
4124665SN/A
4134665SN/A    return true;
4142810SN/A}
4152810SN/A
4162810SN/A
4172810SN/Avoid
4184670SN/AMSHR::handleFill(Packet *pkt, CacheBlk *blk)
4194668SN/A{
4207667Ssteve.reinhardt@amd.com    if (!pkt->sharedAsserted()
4217667Ssteve.reinhardt@amd.com        && !(hasPostInvalidate() || hasPostDowngrade())
4229725Sandreas.hansson@arm.com        && deferredTargets.needsExclusive) {
4235270SN/A        // We got an exclusive response, but we have deferred targets
4245270SN/A        // which are waiting to request an exclusive copy (not because
4255270SN/A        // of a pending invalidate).  This can happen if the original
4265270SN/A        // request was for a read-only (non-exclusive) block, but we
4275270SN/A        // got an exclusive copy anyway because of the E part of the
4285270SN/A        // MOESI/MESI protocol.  Since we got the exclusive copy
4295270SN/A        // there's no need to defer the targets, so move them up to
4305270SN/A        // the regular target list.
4319725Sandreas.hansson@arm.com        assert(!targets.needsExclusive);
4329725Sandreas.hansson@arm.com        targets.needsExclusive = true;
4335318SN/A        // if any of the deferred targets were upper-level cache
4345318SN/A        // requests marked downstreamPending, need to clear that
4355318SN/A        assert(!downstreamPending);  // not pending here anymore
4369725Sandreas.hansson@arm.com        deferredTargets.clearDownstreamPending();
4375270SN/A        // this clears out deferredTargets too
4389725Sandreas.hansson@arm.com        targets.splice(targets.end(), deferredTargets);
4399725Sandreas.hansson@arm.com        deferredTargets.resetFlags();
4405270SN/A    }
4414668SN/A}
4424668SN/A
4434668SN/A
4445314SN/Abool
4455314SN/AMSHR::checkFunctional(PacketPtr pkt)
4465314SN/A{
4475314SN/A    // For printing, we treat the MSHR as a whole as single entity.
4485314SN/A    // For other requests, we iterate over the individual targets
4495314SN/A    // since that's where the actual data lies.
4505314SN/A    if (pkt->isPrint()) {
45110028SGiacomo.Gabrielli@arm.com        pkt->checkFunctional(this, addr, isSecure, size, NULL);
4525314SN/A        return false;
4535314SN/A    } else {
4549725Sandreas.hansson@arm.com        return (targets.checkFunctional(pkt) ||
4559725Sandreas.hansson@arm.com                deferredTargets.checkFunctional(pkt));
4565314SN/A    }
4575314SN/A}
4585314SN/A
4595314SN/A
4604668SN/Avoid
4615314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
4622810SN/A{
46310028SGiacomo.Gabrielli@arm.com    ccprintf(os, "%s[%x:%x](%s) %s %s %s state: %s %s %s %s %s\n",
4645314SN/A             prefix, addr, addr+size-1,
46510028SGiacomo.Gabrielli@arm.com             isSecure ? "s" : "ns",
4665730SSteve.Reinhardt@amd.com             isForward ? "Forward" : "",
4675730SSteve.Reinhardt@amd.com             isForwardNoResponse() ? "ForwNoResp" : "",
4685314SN/A             needsExclusive() ? "Excl" : "",
4695314SN/A             _isUncacheable ? "Unc" : "",
4705314SN/A             inService ? "InSvc" : "",
4715314SN/A             downstreamPending ? "DwnPend" : "",
4727667Ssteve.reinhardt@amd.com             hasPostInvalidate() ? "PostInv" : "",
4737667Ssteve.reinhardt@amd.com             hasPostDowngrade() ? "PostDowngr" : "");
4742810SN/A
4755314SN/A    ccprintf(os, "%s  Targets:\n", prefix);
4769725Sandreas.hansson@arm.com    targets.print(os, verbosity, prefix + "    ");
4779725Sandreas.hansson@arm.com    if (!deferredTargets.empty()) {
4785314SN/A        ccprintf(os, "%s  Deferred Targets:\n", prefix);
4799725Sandreas.hansson@arm.com        deferredTargets.print(os, verbosity, prefix + "      ");
4802810SN/A    }
4812810SN/A}
4822810SN/A
4839663Suri.wiener@arm.comstd::string
4849663Suri.wiener@arm.comMSHR::print() const
4859663Suri.wiener@arm.com{
4869663Suri.wiener@arm.com    ostringstream str;
4879663Suri.wiener@arm.com    print(str);
4889663Suri.wiener@arm.com    return str.str();
4899663Suri.wiener@arm.com}
490