mshr.cc revision 10028
12810SN/A/*
210028SGiacomo.Gabrielli@arm.com * Copyright (c) 2012-2013 ARM Limited
39663Suri.wiener@arm.com * All rights reserved.
49663Suri.wiener@arm.com *
59663Suri.wiener@arm.com * The license below extends only to copyright in the software and shall
69663Suri.wiener@arm.com * not be construed as granting a license to any other intellectual
79663Suri.wiener@arm.com * property including but not limited to intellectual property relating
89663Suri.wiener@arm.com * to a hardware implementation of the functionality of the software
99663Suri.wiener@arm.com * licensed hereunder.  You may use the software subject to the license
109663Suri.wiener@arm.com * terms below provided that you ensure that this notice is replicated
119663Suri.wiener@arm.com * unmodified and in its entirety in all distributions of the software,
129663Suri.wiener@arm.com * modified or unmodified, in source code or in binary form.
139663Suri.wiener@arm.com *
142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
157636Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc.
162810SN/A * All rights reserved.
172810SN/A *
182810SN/A * Redistribution and use in source and binary forms, with or without
192810SN/A * modification, are permitted provided that the following conditions are
202810SN/A * met: redistributions of source code must retain the above copyright
212810SN/A * notice, this list of conditions and the following disclaimer;
222810SN/A * redistributions in binary form must reproduce the above copyright
232810SN/A * notice, this list of conditions and the following disclaimer in the
242810SN/A * documentation and/or other materials provided with the distribution;
252810SN/A * neither the name of the copyright holders nor the names of its
262810SN/A * contributors may be used to endorse or promote products derived from
272810SN/A * this software without specific prior written permission.
282810SN/A *
292810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402810SN/A *
412810SN/A * Authors: Erik Hallnor
422810SN/A *          Dave Greene
432810SN/A */
442810SN/A
452810SN/A/**
462810SN/A * @file
472810SN/A * Miss Status and Handling Register (MSHR) definitions.
482810SN/A */
492810SN/A
506216Snate@binkert.org#include <algorithm>
516216Snate@binkert.org#include <cassert>
522810SN/A#include <string>
532810SN/A#include <vector>
542810SN/A
556216Snate@binkert.org#include "base/misc.hh"
566216Snate@binkert.org#include "base/types.hh"
578232Snate@binkert.org#include "debug/Cache.hh"
586216Snate@binkert.org#include "mem/cache/cache.hh"
595338Sstever@gmail.com#include "mem/cache/mshr.hh"
606216Snate@binkert.org#include "sim/core.hh"
612810SN/A
622810SN/Ausing namespace std;
632810SN/A
649725Sandreas.hansson@arm.comMSHR::MSHR() : readyTime(0), _isUncacheable(false), downstreamPending(false),
659725Sandreas.hansson@arm.com               pendingDirty(false), postInvalidate(false),
669725Sandreas.hansson@arm.com               postDowngrade(false), queue(NULL), order(0), addr(0), size(0),
6710028SGiacomo.Gabrielli@arm.com               isSecure(false), inService(false), isForward(false),
6810028SGiacomo.Gabrielli@arm.com               threadNum(InvalidThreadID), data(NULL)
692810SN/A{
702810SN/A}
712810SN/A
724903SN/A
734903SN/AMSHR::TargetList::TargetList()
744903SN/A    : needsExclusive(false), hasUpgrade(false)
754903SN/A{}
764903SN/A
774903SN/A
784903SN/Ainline void
794908SN/AMSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
805875Ssteve.reinhardt@amd.com                      Counter order, Target::Source source, bool markPending)
814903SN/A{
825875Ssteve.reinhardt@amd.com    if (source != Target::FromSnoop) {
834903SN/A        if (pkt->needsExclusive()) {
844903SN/A            needsExclusive = true;
854903SN/A        }
864903SN/A
877669Ssteve.reinhardt@amd.com        // StoreCondReq is effectively an upgrade if it's in an MSHR
887669Ssteve.reinhardt@amd.com        // since it would have been failed already if we didn't have a
897669Ssteve.reinhardt@amd.com        // read-only copy
907669Ssteve.reinhardt@amd.com        if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
914903SN/A            hasUpgrade = true;
924903SN/A        }
935318SN/A    }
944908SN/A
955318SN/A    if (markPending) {
969543Ssascha.bischoff@arm.com        // Iterate over the SenderState stack and see if we find
979543Ssascha.bischoff@arm.com        // an MSHR entry. If we do, set the downstreamPending
989543Ssascha.bischoff@arm.com        // flag. Otherwise, do nothing.
999543Ssascha.bischoff@arm.com        MSHR *mshr = pkt->findNextSenderState<MSHR>();
1004908SN/A        if (mshr != NULL) {
1014908SN/A            assert(!mshr->downstreamPending);
1024908SN/A            mshr->downstreamPending = true;
1034908SN/A        }
1044903SN/A    }
1054903SN/A
1065875Ssteve.reinhardt@amd.com    push_back(Target(pkt, readyTime, order, source, markPending));
1074903SN/A}
1084903SN/A
1094903SN/A
1107667Ssteve.reinhardt@amd.comstatic void
1117667Ssteve.reinhardt@amd.comreplaceUpgrade(PacketPtr pkt)
1127667Ssteve.reinhardt@amd.com{
1137667Ssteve.reinhardt@amd.com    if (pkt->cmd == MemCmd::UpgradeReq) {
1147667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::ReadExReq;
1157667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing UpgradeReq with ReadExReq\n");
1167667Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
1177667Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::SCUpgradeFailReq;
1187667Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
1197669Ssteve.reinhardt@amd.com    } else if (pkt->cmd == MemCmd::StoreCondReq) {
1207669Ssteve.reinhardt@amd.com        pkt->cmd = MemCmd::StoreCondFailReq;
1217669Ssteve.reinhardt@amd.com        DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
1227667Ssteve.reinhardt@amd.com    }
1237667Ssteve.reinhardt@amd.com}
1247667Ssteve.reinhardt@amd.com
1257667Ssteve.reinhardt@amd.com
1264903SN/Avoid
1274903SN/AMSHR::TargetList::replaceUpgrades()
1284903SN/A{
1294903SN/A    if (!hasUpgrade)
1304903SN/A        return;
1314903SN/A
1324903SN/A    Iterator end_i = end();
1334903SN/A    for (Iterator i = begin(); i != end_i; ++i) {
1347667Ssteve.reinhardt@amd.com        replaceUpgrade(i->pkt);
1354903SN/A    }
1364903SN/A
1374903SN/A    hasUpgrade = false;
1384903SN/A}
1394903SN/A
1404903SN/A
1412810SN/Avoid
1424908SN/AMSHR::TargetList::clearDownstreamPending()
1434908SN/A{
1444908SN/A    Iterator end_i = end();
1454908SN/A    for (Iterator i = begin(); i != end_i; ++i) {
1465318SN/A        if (i->markedPending) {
1479543Ssascha.bischoff@arm.com            // Iterate over the SenderState stack and see if we find
1489543Ssascha.bischoff@arm.com            // an MSHR entry. If we find one, clear the
1499543Ssascha.bischoff@arm.com            // downstreamPending flag by calling
1509543Ssascha.bischoff@arm.com            // clearDownstreamPending(). This recursively clears the
1519543Ssascha.bischoff@arm.com            // downstreamPending flag in all caches this packet has
1529543Ssascha.bischoff@arm.com            // passed through.
1539543Ssascha.bischoff@arm.com            MSHR *mshr = i->pkt->findNextSenderState<MSHR>();
1545318SN/A            if (mshr != NULL) {
1555318SN/A                mshr->clearDownstreamPending();
1565318SN/A            }
1574908SN/A        }
1584908SN/A    }
1594908SN/A}
1604908SN/A
1614908SN/A
1624920SN/Abool
1634920SN/AMSHR::TargetList::checkFunctional(PacketPtr pkt)
1644920SN/A{
1654920SN/A    Iterator end_i = end();
1664920SN/A    for (Iterator i = begin(); i != end_i; ++i) {
1674920SN/A        if (pkt->checkFunctional(i->pkt)) {
1684920SN/A            return true;
1694920SN/A        }
1704920SN/A    }
1714920SN/A
1724920SN/A    return false;
1734920SN/A}
1744920SN/A
1754920SN/A
1764908SN/Avoid
1775314SN/AMSHR::TargetList::
1785314SN/Aprint(std::ostream &os, int verbosity, const std::string &prefix) const
1795314SN/A{
1805314SN/A    ConstIterator end_i = end();
1815314SN/A    for (ConstIterator i = begin(); i != end_i; ++i) {
1825875Ssteve.reinhardt@amd.com        const char *s;
1835875Ssteve.reinhardt@amd.com        switch (i->source) {
1848988SAli.Saidi@ARM.com          case Target::FromCPU:
1858988SAli.Saidi@ARM.com            s = "FromCPU";
1868988SAli.Saidi@ARM.com            break;
1878988SAli.Saidi@ARM.com          case Target::FromSnoop:
1888988SAli.Saidi@ARM.com            s = "FromSnoop";
1898988SAli.Saidi@ARM.com            break;
1908988SAli.Saidi@ARM.com          case Target::FromPrefetcher:
1918988SAli.Saidi@ARM.com            s = "FromPrefetcher";
1928988SAli.Saidi@ARM.com            break;
1938988SAli.Saidi@ARM.com          default:
1948988SAli.Saidi@ARM.com            s = "";
1958988SAli.Saidi@ARM.com            break;
1965875Ssteve.reinhardt@amd.com        }
1975875Ssteve.reinhardt@amd.com        ccprintf(os, "%s%s: ", prefix, s);
1985314SN/A        i->pkt->print(os, verbosity, "");
1995314SN/A    }
2005314SN/A}
2015314SN/A
2025314SN/A
2035314SN/Avoid
20410028SGiacomo.Gabrielli@arm.comMSHR::allocate(Addr _addr, int _size, PacketPtr target, Tick whenReady,
20510028SGiacomo.Gabrielli@arm.com               Counter _order)
2062810SN/A{
2072885SN/A    addr = _addr;
2084626SN/A    size = _size;
20910028SGiacomo.Gabrielli@arm.com    isSecure = target->isSecure();
2104871SN/A    readyTime = whenReady;
2114666SN/A    order = _order;
2124626SN/A    assert(target);
2135730SSteve.Reinhardt@amd.com    isForward = false;
2144626SN/A    _isUncacheable = target->req->isUncacheable();
2154626SN/A    inService = false;
2164908SN/A    downstreamPending = false;
2174626SN/A    threadNum = 0;
2189725Sandreas.hansson@arm.com    assert(targets.isReset());
2194626SN/A    // Don't know of a case where we would allocate a new MSHR for a
2205875Ssteve.reinhardt@amd.com    // snoop (mem-side request), so set source according to request here
2215875Ssteve.reinhardt@amd.com    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
2225875Ssteve.reinhardt@amd.com        Target::FromPrefetcher : Target::FromCPU;
2239725Sandreas.hansson@arm.com    targets.add(target, whenReady, _order, source, true);
2249725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
2254668SN/A    data = NULL;
2262810SN/A}
2272810SN/A
2284908SN/A
2295318SN/Avoid
2305318SN/AMSHR::clearDownstreamPending()
2315318SN/A{
2325318SN/A    assert(downstreamPending);
2335318SN/A    downstreamPending = false;
2345318SN/A    // recursively clear flag on any MSHRs we will be forwarding
2355318SN/A    // responses to
2369725Sandreas.hansson@arm.com    targets.clearDownstreamPending();
2375318SN/A}
2385318SN/A
2394908SN/Abool
2407667Ssteve.reinhardt@amd.comMSHR::markInService(PacketPtr pkt)
2414908SN/A{
2424908SN/A    assert(!inService);
2435730SSteve.Reinhardt@amd.com    if (isForwardNoResponse()) {
2444908SN/A        // we just forwarded the request packet & don't expect a
2454908SN/A        // response, so get rid of it
2464908SN/A        assert(getNumTargets() == 1);
2474908SN/A        popTarget();
2484908SN/A        return true;
2494908SN/A    }
2504908SN/A    inService = true;
2519725Sandreas.hansson@arm.com    pendingDirty = (targets.needsExclusive ||
2527667Ssteve.reinhardt@amd.com                    (!pkt->sharedAsserted() && pkt->memInhibitAsserted()));
2537667Ssteve.reinhardt@amd.com    postInvalidate = postDowngrade = false;
2547667Ssteve.reinhardt@amd.com
2554908SN/A    if (!downstreamPending) {
2564908SN/A        // let upstream caches know that the request has made it to a
2574908SN/A        // level where it's going to get a response
2589725Sandreas.hansson@arm.com        targets.clearDownstreamPending();
2594908SN/A    }
2604908SN/A    return false;
2614908SN/A}
2624908SN/A
2634908SN/A
2642810SN/Avoid
2652810SN/AMSHR::deallocate()
2662810SN/A{
2679725Sandreas.hansson@arm.com    assert(targets.empty());
2689725Sandreas.hansson@arm.com    targets.resetFlags();
2699725Sandreas.hansson@arm.com    assert(deferredTargets.isReset());
2702810SN/A    inService = false;
2712810SN/A}
2722810SN/A
2732810SN/A/*
2742810SN/A * Adds a target to an MSHR
2752810SN/A */
2762810SN/Avoid
2774903SN/AMSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order)
2782810SN/A{
2794903SN/A    // if there's a request already in service for this MSHR, we will
2804903SN/A    // have to defer the new target until after the response if any of
2814903SN/A    // the following are true:
2824903SN/A    // - there are other targets already deferred
2834903SN/A    // - there's a pending invalidate to be applied after the response
2844903SN/A    //   comes back (but before this target is processed)
2857667Ssteve.reinhardt@amd.com    // - this target requires an exclusive block and either we're not
2867667Ssteve.reinhardt@amd.com    //   getting an exclusive block back or we have already snooped
2877667Ssteve.reinhardt@amd.com    //   another read request that will downgrade our exclusive block
2887667Ssteve.reinhardt@amd.com    //   to shared
2895875Ssteve.reinhardt@amd.com
2905875Ssteve.reinhardt@amd.com    // assume we'd never issue a prefetch when we've got an
2915875Ssteve.reinhardt@amd.com    // outstanding miss
2925875Ssteve.reinhardt@amd.com    assert(pkt->cmd != MemCmd::HardPFReq);
2935875Ssteve.reinhardt@amd.com
2944903SN/A    if (inService &&
2959725Sandreas.hansson@arm.com        (!deferredTargets.empty() || hasPostInvalidate() ||
2967667Ssteve.reinhardt@amd.com         (pkt->needsExclusive() &&
2977667Ssteve.reinhardt@amd.com          (!isPendingDirty() || hasPostDowngrade() || isForward)))) {
2984903SN/A        // need to put on deferred list
2997667Ssteve.reinhardt@amd.com        if (hasPostInvalidate())
3007667Ssteve.reinhardt@amd.com            replaceUpgrade(pkt);
3019725Sandreas.hansson@arm.com        deferredTargets.add(pkt, whenReady, _order, Target::FromCPU, true);
3024665SN/A    } else {
3035318SN/A        // No request outstanding, or still OK to append to
3045318SN/A        // outstanding request: append to regular target list.  Only
3055318SN/A        // mark pending if current request hasn't been issued yet
3065318SN/A        // (isn't in service).
3079725Sandreas.hansson@arm.com        targets.add(pkt, whenReady, _order, Target::FromCPU, !inService);
3082810SN/A    }
3094665SN/A}
3104665SN/A
3114902SN/Abool
3124902SN/AMSHR::handleSnoop(PacketPtr pkt, Counter _order)
3134665SN/A{
3149663Suri.wiener@arm.com    DPRINTF(Cache, "%s for %s address %x size %d\n", __func__,
3159663Suri.wiener@arm.com            pkt->cmdString(), pkt->getAddr(), pkt->getSize());
3164910SN/A    if (!inService || (pkt->isExpressSnoop() && downstreamPending)) {
3174903SN/A        // Request has not been issued yet, or it's been issued
3184903SN/A        // locally but is buffered unissued at some downstream cache
3194903SN/A        // which is forwarding us this snoop.  Either way, the packet
3204903SN/A        // we're snooping logically precedes this MSHR's request, so
3214903SN/A        // the snoop has no impact on the MSHR, but must be processed
3224903SN/A        // in the standard way by the cache.  The only exception is
3234903SN/A        // that if we're an L2+ cache buffering an UpgradeReq from a
3244903SN/A        // higher-level cache, and the snoop is invalidating, then our
3254903SN/A        // buffered upgrades must be converted to read exclusives,
3264903SN/A        // since the upper-level cache no longer has a valid copy.
3274903SN/A        // That is, even though the upper-level cache got out on its
3284903SN/A        // local bus first, some other invalidating transaction
3294903SN/A        // reached the global bus before the upgrade did.
3304903SN/A        if (pkt->needsExclusive()) {
3319725Sandreas.hansson@arm.com            targets.replaceUpgrades();
3329725Sandreas.hansson@arm.com            deferredTargets.replaceUpgrades();
3334903SN/A        }
3344903SN/A
3354902SN/A        return false;
3364902SN/A    }
3374665SN/A
3384903SN/A    // From here on down, the request issued by this MSHR logically
3394903SN/A    // precedes the request we're snooping.
3404903SN/A    if (pkt->needsExclusive()) {
3414903SN/A        // snooped request still precedes the re-request we'll have to
3424903SN/A        // issue for deferred targets, if any...
3439725Sandreas.hansson@arm.com        deferredTargets.replaceUpgrades();
3444903SN/A    }
3454903SN/A
3467667Ssteve.reinhardt@amd.com    if (hasPostInvalidate()) {
3474665SN/A        // a prior snoop has already appended an invalidation, so
3484903SN/A        // logically we don't have the block anymore; no need for
3494903SN/A        // further snooping.
3504902SN/A        return true;
3514665SN/A    }
3524665SN/A
3537667Ssteve.reinhardt@amd.com    if (isPendingDirty() || pkt->isInvalidate()) {
3547667Ssteve.reinhardt@amd.com        // We need to save and replay the packet in two cases:
3557667Ssteve.reinhardt@amd.com        // 1. We're awaiting an exclusive copy, so ownership is pending,
3567667Ssteve.reinhardt@amd.com        //    and we need to respond after we receive data.
3577667Ssteve.reinhardt@amd.com        // 2. It's an invalidation (e.g., UpgradeReq), and we need
3587667Ssteve.reinhardt@amd.com        //    to forward the snoop up the hierarchy after the current
3597667Ssteve.reinhardt@amd.com        //    transaction completes.
3607667Ssteve.reinhardt@amd.com
3618931Sandreas.hansson@arm.com        // Actual target device (typ. a memory) will delete the
3627667Ssteve.reinhardt@amd.com        // packet on reception, so we need to save a copy here.
3634970SN/A        PacketPtr cp_pkt = new Packet(pkt, true);
3649725Sandreas.hansson@arm.com        targets.add(cp_pkt, curTick(), _order, Target::FromSnoop,
3659725Sandreas.hansson@arm.com                     downstreamPending && targets.needsExclusive);
3664670SN/A
3677667Ssteve.reinhardt@amd.com        if (isPendingDirty()) {
3684670SN/A            pkt->assertMemInhibit();
3694916SN/A            pkt->setSupplyExclusive();
3704670SN/A        }
3714670SN/A
3724670SN/A        if (pkt->needsExclusive()) {
3734670SN/A            // This transaction will take away our pending copy
3747667Ssteve.reinhardt@amd.com            postInvalidate = true;
3754670SN/A        }
3767667Ssteve.reinhardt@amd.com    }
3777667Ssteve.reinhardt@amd.com
3787667Ssteve.reinhardt@amd.com    if (!pkt->needsExclusive()) {
3797667Ssteve.reinhardt@amd.com        // This transaction will get a read-shared copy, downgrading
3807667Ssteve.reinhardt@amd.com        // our copy if we had an exclusive one
3817667Ssteve.reinhardt@amd.com        postDowngrade = true;
3824670SN/A        pkt->assertShared();
3834667SN/A    }
3844902SN/A
3854902SN/A    return true;
3864665SN/A}
3874665SN/A
3884665SN/A
3894665SN/Abool
3904665SN/AMSHR::promoteDeferredTargets()
3914665SN/A{
3929725Sandreas.hansson@arm.com    assert(targets.empty());
3939725Sandreas.hansson@arm.com    if (deferredTargets.empty()) {
3944665SN/A        return false;
3954665SN/A    }
3964665SN/A
3974903SN/A    // swap targets & deferredTargets lists
3989725Sandreas.hansson@arm.com    std::swap(targets, deferredTargets);
3994903SN/A
4004903SN/A    // clear deferredTargets flags
4019725Sandreas.hansson@arm.com    deferredTargets.resetFlags();
4024903SN/A
4039725Sandreas.hansson@arm.com    order = targets.front().order;
4049725Sandreas.hansson@arm.com    readyTime = std::max(curTick(), targets.front().readyTime);
4054665SN/A
4064665SN/A    return true;
4072810SN/A}
4082810SN/A
4092810SN/A
4102810SN/Avoid
4114670SN/AMSHR::handleFill(Packet *pkt, CacheBlk *blk)
4124668SN/A{
4137667Ssteve.reinhardt@amd.com    if (!pkt->sharedAsserted()
4147667Ssteve.reinhardt@amd.com        && !(hasPostInvalidate() || hasPostDowngrade())
4159725Sandreas.hansson@arm.com        && deferredTargets.needsExclusive) {
4165270SN/A        // We got an exclusive response, but we have deferred targets
4175270SN/A        // which are waiting to request an exclusive copy (not because
4185270SN/A        // of a pending invalidate).  This can happen if the original
4195270SN/A        // request was for a read-only (non-exclusive) block, but we
4205270SN/A        // got an exclusive copy anyway because of the E part of the
4215270SN/A        // MOESI/MESI protocol.  Since we got the exclusive copy
4225270SN/A        // there's no need to defer the targets, so move them up to
4235270SN/A        // the regular target list.
4249725Sandreas.hansson@arm.com        assert(!targets.needsExclusive);
4259725Sandreas.hansson@arm.com        targets.needsExclusive = true;
4265318SN/A        // if any of the deferred targets were upper-level cache
4275318SN/A        // requests marked downstreamPending, need to clear that
4285318SN/A        assert(!downstreamPending);  // not pending here anymore
4299725Sandreas.hansson@arm.com        deferredTargets.clearDownstreamPending();
4305270SN/A        // this clears out deferredTargets too
4319725Sandreas.hansson@arm.com        targets.splice(targets.end(), deferredTargets);
4329725Sandreas.hansson@arm.com        deferredTargets.resetFlags();
4335270SN/A    }
4344668SN/A}
4354668SN/A
4364668SN/A
4375314SN/Abool
4385314SN/AMSHR::checkFunctional(PacketPtr pkt)
4395314SN/A{
4405314SN/A    // For printing, we treat the MSHR as a whole as single entity.
4415314SN/A    // For other requests, we iterate over the individual targets
4425314SN/A    // since that's where the actual data lies.
4435314SN/A    if (pkt->isPrint()) {
44410028SGiacomo.Gabrielli@arm.com        pkt->checkFunctional(this, addr, isSecure, size, NULL);
4455314SN/A        return false;
4465314SN/A    } else {
4479725Sandreas.hansson@arm.com        return (targets.checkFunctional(pkt) ||
4489725Sandreas.hansson@arm.com                deferredTargets.checkFunctional(pkt));
4495314SN/A    }
4505314SN/A}
4515314SN/A
4525314SN/A
4534668SN/Avoid
4545314SN/AMSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
4552810SN/A{
45610028SGiacomo.Gabrielli@arm.com    ccprintf(os, "%s[%x:%x](%s) %s %s %s state: %s %s %s %s %s\n",
4575314SN/A             prefix, addr, addr+size-1,
45810028SGiacomo.Gabrielli@arm.com             isSecure ? "s" : "ns",
4595730SSteve.Reinhardt@amd.com             isForward ? "Forward" : "",
4605730SSteve.Reinhardt@amd.com             isForwardNoResponse() ? "ForwNoResp" : "",
4615314SN/A             needsExclusive() ? "Excl" : "",
4625314SN/A             _isUncacheable ? "Unc" : "",
4635314SN/A             inService ? "InSvc" : "",
4645314SN/A             downstreamPending ? "DwnPend" : "",
4657667Ssteve.reinhardt@amd.com             hasPostInvalidate() ? "PostInv" : "",
4667667Ssteve.reinhardt@amd.com             hasPostDowngrade() ? "PostDowngr" : "");
4672810SN/A
4685314SN/A    ccprintf(os, "%s  Targets:\n", prefix);
4699725Sandreas.hansson@arm.com    targets.print(os, verbosity, prefix + "    ");
4709725Sandreas.hansson@arm.com    if (!deferredTargets.empty()) {
4715314SN/A        ccprintf(os, "%s  Deferred Targets:\n", prefix);
4729725Sandreas.hansson@arm.com        deferredTargets.print(os, verbosity, prefix + "      ");
4732810SN/A    }
4742810SN/A}
4752810SN/A
4769663Suri.wiener@arm.comstd::string
4779663Suri.wiener@arm.comMSHR::print() const
4789663Suri.wiener@arm.com{
4799663Suri.wiener@arm.com    ostringstream str;
4809663Suri.wiener@arm.com    print(str);
4819663Suri.wiener@arm.com    return str.str();
4829663Suri.wiener@arm.com}
483