cache.hh revision 9347:b02075171b57
12810SN/A/* 212728Snikos.nikoleris@arm.com * Copyright (c) 2012 ARM Limited 39347SAndreas.Sandberg@arm.com * All rights reserved. 49347SAndreas.Sandberg@arm.com * 59347SAndreas.Sandberg@arm.com * The license below extends only to copyright in the software and shall 69347SAndreas.Sandberg@arm.com * not be construed as granting a license to any other intellectual 79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating 89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software 99347SAndreas.Sandberg@arm.com * licensed hereunder. You may use the software subject to the license 109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated 119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form. 139347SAndreas.Sandberg@arm.com * 142810SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 412810SN/A * Dave Greene 422810SN/A * Steve Reinhardt 432810SN/A * Ron Dreslinski 442810SN/A * Andreas Hansson 452810SN/A */ 462810SN/A 472810SN/A/** 482810SN/A * @file 4912492Sodanrc@yahoo.com.br * Describes a cache based on template policies. 5012492Sodanrc@yahoo.com.br */ 512810SN/A 5212727Snikos.nikoleris@arm.com#ifndef __CACHE_HH__ 5312728Snikos.nikoleris@arm.com#define __CACHE_HH__ 542810SN/A 558229Snate@binkert.org#include "base/misc.hh" // fatal, panic, and warn 568229Snate@binkert.org#include "mem/cache/base.hh" 5712727Snikos.nikoleris@arm.com#include "mem/cache/blk.hh" 582810SN/A#include "mem/cache/mshr.hh" 5912727Snikos.nikoleris@arm.com#include "sim/eventq.hh" 6010815Sdavid.guillen@arm.com 619796Sprakash.ramrakhyani@arm.com//Forward decleration 629796Sprakash.ramrakhyani@arm.comclass BasePrefetcher; 632810SN/A 642810SN/A/** 6512773Sodanrc@yahoo.com.br * A template-policy based cache. The behavior of the cache can be altered by 662810SN/A * supplying different template policies. TagStore handles all tag and data 672810SN/A * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" 682810SN/A */ 692810SN/Atemplate <class TagStore> 709796Sprakash.ramrakhyani@arm.comclass Cache : public BaseCache 712810SN/A{ 722810SN/A public: 739796Sprakash.ramrakhyani@arm.com /** Define the type of cache block to use. */ 749796Sprakash.ramrakhyani@arm.com typedef typename TagStore::BlkType BlkType; 7511893Snikos.nikoleris@arm.com /** A typedef for a list of BlkType pointers. */ 7611893Snikos.nikoleris@arm.com typedef typename TagStore::BlkList BlkList; 779796Sprakash.ramrakhyani@arm.com 789796Sprakash.ramrakhyani@arm.com protected: 7911722Ssophiane.senni@gmail.com typedef CacheBlkVisitorWrapper<Cache<TagStore>, BlkType> WrappedBlkVisitor; 8011722Ssophiane.senni@gmail.com 8111722Ssophiane.senni@gmail.com /** 8211722Ssophiane.senni@gmail.com * The CPU-side port extends the base cache slave port with access 8311722Ssophiane.senni@gmail.com * functions for functional, atomic and timing requests. 8411722Ssophiane.senni@gmail.com */ 8511722Ssophiane.senni@gmail.com class CpuSidePort : public CacheSlavePort 8610693SMarco.Balboni@ARM.com { 872810SN/A private: 882810SN/A 892810SN/A // a pointer to our specific cache implementation 902810SN/A Cache<TagStore> *cache; 912810SN/A 922810SN/A protected: 932810SN/A 9412513Sodanrc@yahoo.com.br virtual bool recvTimingSnoopResp(PacketPtr pkt); 952810SN/A 962810SN/A virtual bool recvTimingReq(PacketPtr pkt); 972810SN/A 986978SLisa.Hsu@amd.com virtual Tick recvAtomic(PacketPtr pkt); 9912553Snikos.nikoleris@arm.com 1006978SLisa.Hsu@amd.com virtual void recvFunctional(PacketPtr pkt); 10112629Sodanrc@yahoo.com.br 10212629Sodanrc@yahoo.com.br virtual unsigned deviceBlockSize() const 10312629Sodanrc@yahoo.com.br { return cache->getBlockSize(); } 1042810SN/A 1052810SN/A virtual AddrRangeList getAddrRanges() const; 10612513Sodanrc@yahoo.com.br 1072810SN/A public: 1082810SN/A 1092810SN/A CpuSidePort(const std::string &_name, Cache<TagStore> *_cache, 1102810SN/A const std::string &_label); 1112810SN/A 1125999Snate@binkert.org }; 1132810SN/A 1142810SN/A /** 1155999Snate@binkert.org * Override the default behaviour of sendDeferredPacket to enable 1162810SN/A * the memory-side cache port to also send requests based on the 1172810SN/A * current MSHR status. This queue has a pointer to our specific 1182810SN/A * cache implementation and is used by the MemSidePort. 1192810SN/A */ 1202810SN/A class MemSidePacketQueue : public MasterPacketQueue 1212810SN/A { 1225999Snate@binkert.org 1232810SN/A protected: 1242810SN/A 1252810SN/A Cache<TagStore> &cache; 1262810SN/A 1272810SN/A public: 1282810SN/A 1292810SN/A MemSidePacketQueue(Cache<TagStore> &cache, MasterPort &port, 13012513Sodanrc@yahoo.com.br const std::string &label) : 1315999Snate@binkert.org MasterPacketQueue(cache, port, label), cache(cache) { } 1326978SLisa.Hsu@amd.com 1338833Sdam.sunwoo@arm.com /** 1346978SLisa.Hsu@amd.com * Override the normal sendDeferredPacket and do not only 1356978SLisa.Hsu@amd.com * consider the transmit list (used for responses), but also 1368833Sdam.sunwoo@arm.com * requests. 1376978SLisa.Hsu@amd.com */ 1386978SLisa.Hsu@amd.com virtual void sendDeferredPacket(); 13910024Sdam.sunwoo@arm.com 14010024Sdam.sunwoo@arm.com }; 14110024Sdam.sunwoo@arm.com 14210024Sdam.sunwoo@arm.com /** 14310024Sdam.sunwoo@arm.com * The memory-side port extends the base cache master port with 14410024Sdam.sunwoo@arm.com * access functions for functional, atomic and timing snoops. 14510024Sdam.sunwoo@arm.com */ 14610024Sdam.sunwoo@arm.com class MemSidePort : public CacheMasterPort 14710024Sdam.sunwoo@arm.com { 14810025Stimothy.jones@arm.com private: 14910025Stimothy.jones@arm.com 15010025Stimothy.jones@arm.com /** The cache-specific queue. */ 15110025Stimothy.jones@arm.com MemSidePacketQueue _queue; 15210025Stimothy.jones@arm.com 1532810SN/A // a pointer to our specific cache implementation 1542810SN/A Cache<TagStore> *cache; 1552810SN/A 1562810SN/A protected: 15713216Sodanrc@yahoo.com.br 15813216Sodanrc@yahoo.com.br virtual void recvTimingSnoopReq(PacketPtr pkt); 15913216Sodanrc@yahoo.com.br 16013216Sodanrc@yahoo.com.br virtual bool recvTimingResp(PacketPtr pkt); 16113216Sodanrc@yahoo.com.br 16213216Sodanrc@yahoo.com.br virtual Tick recvAtomicSnoop(PacketPtr pkt); 16313216Sodanrc@yahoo.com.br 16413217Sodanrc@yahoo.com.br virtual void recvFunctionalSnoop(PacketPtr pkt); 16513217Sodanrc@yahoo.com.br 16613217Sodanrc@yahoo.com.br virtual unsigned deviceBlockSize() const 16713217Sodanrc@yahoo.com.br { return cache->getBlockSize(); } 16813217Sodanrc@yahoo.com.br 16913217Sodanrc@yahoo.com.br public: 17013217Sodanrc@yahoo.com.br 17113217Sodanrc@yahoo.com.br MemSidePort(const std::string &_name, Cache<TagStore> *_cache, 17213217Sodanrc@yahoo.com.br const std::string &_label); 17313217Sodanrc@yahoo.com.br }; 17413217Sodanrc@yahoo.com.br 17513217Sodanrc@yahoo.com.br /** Tag and data Storage */ 1762810SN/A TagStore *tags; 1779796Sprakash.ramrakhyani@arm.com 1789796Sprakash.ramrakhyani@arm.com /** Prefetcher */ 1792810SN/A BasePrefetcher *prefetcher; 1802810SN/A 1812810SN/A /** Temporary cache block for occasional transitory use */ 1822810SN/A BlkType *tempBlock; 1832810SN/A 1842810SN/A /** 1852810SN/A * This cache should allocate a block on a line-sized write miss. 18613216Sodanrc@yahoo.com.br */ 18713216Sodanrc@yahoo.com.br const bool doFastWrites; 1882810SN/A 1892810SN/A /** 19013216Sodanrc@yahoo.com.br * Notify the prefetcher on every access, not just misses. 1912810SN/A */ 1922810SN/A const bool prefetchOnAccess; 1939796Sprakash.ramrakhyani@arm.com 1942810SN/A /** 1959796Sprakash.ramrakhyani@arm.com * @todo this is a temporary workaround until the 4-phase code is committed. 1962810SN/A * upstream caches need this packet until true is returned, so hold it for 1972810SN/A * deletion until a subsequent call 1982810SN/A */ 1992810SN/A std::vector<PacketPtr> pendingDelete; 2002810SN/A 20112728Snikos.nikoleris@arm.com /** 2027612SGene.Wu@arm.com * Does all the processing necessary to perform the provided request. 2037612SGene.Wu@arm.com * @param pkt The memory request to perform. 20410024Sdam.sunwoo@arm.com * @param lat The latency of the access. 20510024Sdam.sunwoo@arm.com * @param writebacks List for any writebacks that need to be performed. 20612728Snikos.nikoleris@arm.com * @param update True if the replacement data should be updated. 20710024Sdam.sunwoo@arm.com * @return Boolean indicating whether the request was satisfied. 20810024Sdam.sunwoo@arm.com */ 2099663Suri.wiener@arm.com bool access(PacketPtr pkt, BlkType *&blk, 2109663Suri.wiener@arm.com Cycles &lat, PacketList &writebacks); 21112728Snikos.nikoleris@arm.com 21210815Sdavid.guillen@arm.com /** 21310815Sdavid.guillen@arm.com *Handle doing the Compare and Swap function for SPARC. 21413217Sodanrc@yahoo.com.br */ 21513217Sodanrc@yahoo.com.br void cmpAndSwap(BlkType *blk, PacketPtr pkt); 21613217Sodanrc@yahoo.com.br 21713217Sodanrc@yahoo.com.br /** 21813217Sodanrc@yahoo.com.br * Find a block frame for new block at address addr, assuming that 21910815Sdavid.guillen@arm.com * the block is not currently in the cache. Append writebacks if 22013217Sodanrc@yahoo.com.br * any to provided packet list. Return free block frame. May 22110815Sdavid.guillen@arm.com * return NULL if there are no replaceable blocks at the moment. 22210815Sdavid.guillen@arm.com */ 22312743Sodanrc@yahoo.com.br BlkType *allocateBlock(Addr addr, PacketList &writebacks); 22412743Sodanrc@yahoo.com.br 22512743Sodanrc@yahoo.com.br /** 22612743Sodanrc@yahoo.com.br * Populates a cache block and handles all outstanding requests for the 22712743Sodanrc@yahoo.com.br * satisfied fill request. This version takes two memory requests. One 22812743Sodanrc@yahoo.com.br * contains the fill data, the other is an optional target to satisfy. 22912743Sodanrc@yahoo.com.br * @param pkt The memory request with the fill data. 23012743Sodanrc@yahoo.com.br * @param blk The cache block if it already exists. 23112743Sodanrc@yahoo.com.br * @param writebacks List for any writebacks that need to be performed. 23211893Snikos.nikoleris@arm.com * @return Pointer to the new cache block. 23311893Snikos.nikoleris@arm.com */ 23411893Snikos.nikoleris@arm.com BlkType *handleFill(PacketPtr pkt, BlkType *blk, 23511893Snikos.nikoleris@arm.com PacketList &writebacks); 23611893Snikos.nikoleris@arm.com 23711893Snikos.nikoleris@arm.com void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk, 23811893Snikos.nikoleris@arm.com bool deferred_response = false, 23911893Snikos.nikoleris@arm.com bool pending_downgrade = false); 24011893Snikos.nikoleris@arm.com bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); 24111893Snikos.nikoleris@arm.com 24210815Sdavid.guillen@arm.com void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, 24310815Sdavid.guillen@arm.com bool already_copied, bool pending_inval); 24410815Sdavid.guillen@arm.com 24510815Sdavid.guillen@arm.com /** 24610815Sdavid.guillen@arm.com * Sets the blk to the new state. 24710815Sdavid.guillen@arm.com * @param blk The cache block being snooped. 24811893Snikos.nikoleris@arm.com * @param new_state The new coherence state for the block. 24910815Sdavid.guillen@arm.com */ 25010815Sdavid.guillen@arm.com void handleSnoop(PacketPtr ptk, BlkType *blk, 25110941Sdavid.guillen@arm.com bool is_timing, bool is_deferred, bool pending_inval); 25210941Sdavid.guillen@arm.com 25310941Sdavid.guillen@arm.com /** 25410941Sdavid.guillen@arm.com * Create a writeback request for the given block. 25510941Sdavid.guillen@arm.com * @param blk The block to writeback. 25610941Sdavid.guillen@arm.com * @return The writeback request for the block. 25710941Sdavid.guillen@arm.com */ 25810941Sdavid.guillen@arm.com PacketPtr writebackBlk(BlkType *blk); 25910941Sdavid.guillen@arm.com 26010941Sdavid.guillen@arm.com 26110941Sdavid.guillen@arm.com void memWriteback(); 26210941Sdavid.guillen@arm.com void memInvalidate(); 26310941Sdavid.guillen@arm.com bool isDirty() const; 26410941Sdavid.guillen@arm.com 26510941Sdavid.guillen@arm.com /** 26610941Sdavid.guillen@arm.com * Cache block visitor that writes back dirty cache blocks using 26710941Sdavid.guillen@arm.com * functional writes. 26810941Sdavid.guillen@arm.com * 26910941Sdavid.guillen@arm.com * \return Always returns true. 27012566Snikos.nikoleris@arm.com */ 27112704Snikos.nikoleris@arm.com bool writebackVisitor(BlkType &blk); 27212704Snikos.nikoleris@arm.com /** 27312704Snikos.nikoleris@arm.com * Cache block visitor that invalidates all blocks in the cache. 27412566Snikos.nikoleris@arm.com * 27512566Snikos.nikoleris@arm.com * @warn Dirty cache lines will not be written back to memory. 27612566Snikos.nikoleris@arm.com * 27712566Snikos.nikoleris@arm.com * \return Always returns true. 27812566Snikos.nikoleris@arm.com */ 27912704Snikos.nikoleris@arm.com bool invalidateVisitor(BlkType &blk); 28012566Snikos.nikoleris@arm.com 28112704Snikos.nikoleris@arm.com public: 28212704Snikos.nikoleris@arm.com /** Instantiates a basic cache object. */ 28312704Snikos.nikoleris@arm.com Cache(const Params *p, TagStore *tags); 28412704Snikos.nikoleris@arm.com 28512566Snikos.nikoleris@arm.com void regStats(); 28610815Sdavid.guillen@arm.com 28712600Sodanrc@yahoo.com.br /** 28812744Sodanrc@yahoo.com.br * Performs the access specified by the request. 28912744Sodanrc@yahoo.com.br * @param pkt The request to perform. 29012744Sodanrc@yahoo.com.br * @return The result of the access. 29112744Sodanrc@yahoo.com.br */ 29212744Sodanrc@yahoo.com.br bool timingAccess(PacketPtr pkt); 29312744Sodanrc@yahoo.com.br 29412744Sodanrc@yahoo.com.br /** 29512600Sodanrc@yahoo.com.br * Performs the access specified by the request. 29612600Sodanrc@yahoo.com.br * @param pkt The request to perform. 29712746Sodanrc@yahoo.com.br * @return The number of ticks required for the access. 29812744Sodanrc@yahoo.com.br */ 29912600Sodanrc@yahoo.com.br Tick atomicAccess(PacketPtr pkt); 30012600Sodanrc@yahoo.com.br 30112746Sodanrc@yahoo.com.br /** 30212746Sodanrc@yahoo.com.br * Performs the access specified by the request. 30312600Sodanrc@yahoo.com.br * @param pkt The request to perform. 30411870Snikos.nikoleris@arm.com * @param fromCpuSide from the CPU side port or the memory side port 30510815Sdavid.guillen@arm.com */ 30610815Sdavid.guillen@arm.com void functionalAccess(PacketPtr pkt, bool fromCpuSide); 30710815Sdavid.guillen@arm.com 30812636Sodanrc@yahoo.com.br /** 30912636Sodanrc@yahoo.com.br * Handles a response (cache line fill/write ack) from the bus. 31012636Sodanrc@yahoo.com.br * @param pkt The request being responded to. 31113215Sodanrc@yahoo.com.br */ 31213215Sodanrc@yahoo.com.br void handleResponse(PacketPtr pkt); 31313215Sodanrc@yahoo.com.br 31413215Sodanrc@yahoo.com.br /** 31512636Sodanrc@yahoo.com.br * Snoops bus transactions to maintain coherence. 31612636Sodanrc@yahoo.com.br * @param pkt The current bus transaction. 31713215Sodanrc@yahoo.com.br */ 31813215Sodanrc@yahoo.com.br void snoopTiming(PacketPtr pkt); 31913215Sodanrc@yahoo.com.br 32010815Sdavid.guillen@arm.com /** 32112574Sodanrc@yahoo.com.br * Snoop for the provided request in the cache and return the estimated 32212574Sodanrc@yahoo.com.br * time of completion. 32312574Sodanrc@yahoo.com.br * @param pkt The memory request to snoop 32412574Sodanrc@yahoo.com.br * @return The number of cycles required for the snoop. 32512574Sodanrc@yahoo.com.br */ 32612574Sodanrc@yahoo.com.br Cycles snoopAtomic(PacketPtr pkt); 32712574Sodanrc@yahoo.com.br 32810815Sdavid.guillen@arm.com /** 32912728Snikos.nikoleris@arm.com * Squash all requests associated with specified thread. 33012728Snikos.nikoleris@arm.com * intended for use by I-cache. 33112728Snikos.nikoleris@arm.com * @param threadNum The thread to squash. 33212728Snikos.nikoleris@arm.com */ 33312728Snikos.nikoleris@arm.com void squash(int threadNum); 33412728Snikos.nikoleris@arm.com 33512728Snikos.nikoleris@arm.com /** 33612728Snikos.nikoleris@arm.com * Generate an appropriate downstream bus request packet for the 33712728Snikos.nikoleris@arm.com * given parameters. 33812728Snikos.nikoleris@arm.com * @param cpu_pkt The upstream request that needs to be satisfied. 33912728Snikos.nikoleris@arm.com * @param blk The block currently in the cache corresponding to 34012728Snikos.nikoleris@arm.com * cpu_pkt (NULL if none). 34112728Snikos.nikoleris@arm.com * @param needsExclusive Indicates that an exclusive copy is required 34212728Snikos.nikoleris@arm.com * even if the request in cpu_pkt doesn't indicate that. 34312728Snikos.nikoleris@arm.com * @return A new Packet containing the request, or NULL if the 34412728Snikos.nikoleris@arm.com * current request in cpu_pkt should just be forwarded on. 34512728Snikos.nikoleris@arm.com */ 34612728Snikos.nikoleris@arm.com PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 34712728Snikos.nikoleris@arm.com bool needsExclusive); 34812728Snikos.nikoleris@arm.com 34912728Snikos.nikoleris@arm.com /** 35012728Snikos.nikoleris@arm.com * Return the next MSHR to service, either a pending miss from the 35112728Snikos.nikoleris@arm.com * mshrQueue, a buffered write from the write buffer, or something 35212728Snikos.nikoleris@arm.com * from the prefetcher. This function is responsible for 35312728Snikos.nikoleris@arm.com * prioritizing among those sources on the fly. 35412728Snikos.nikoleris@arm.com */ 35512728Snikos.nikoleris@arm.com MSHR *getNextMSHR(); 35612728Snikos.nikoleris@arm.com 35712728Snikos.nikoleris@arm.com /** 35812728Snikos.nikoleris@arm.com * Selects an outstanding request to service. Called when the 35912728Snikos.nikoleris@arm.com * cache gets granted the downstream bus in timing mode. 36012728Snikos.nikoleris@arm.com * @return The request to service, NULL if none found. 36112728Snikos.nikoleris@arm.com */ 36212728Snikos.nikoleris@arm.com PacketPtr getTimingPacket(); 36312728Snikos.nikoleris@arm.com 3642810SN/A /** 3652810SN/A * Marks a request as in service (sent on the bus). This can have side 3662810SN/A * effect since storage for no response commands is deallocated once they 3672810SN/A * are successfully sent. 3682810SN/A * @param pkt The request that was sent on the bus. 3692810SN/A */ 3702810SN/A void markInService(MSHR *mshr, PacketPtr pkt = 0); 3712810SN/A 3722810SN/A /** 3732810SN/A * Return whether there are any outstanding misses. 37410024Sdam.sunwoo@arm.com */ 37510024Sdam.sunwoo@arm.com bool outstandingMisses() const 37610024Sdam.sunwoo@arm.com { 37710024Sdam.sunwoo@arm.com return mshrQueue.allocated != 0; 37810024Sdam.sunwoo@arm.com } 37910024Sdam.sunwoo@arm.com 38010024Sdam.sunwoo@arm.com CacheBlk *findBlock(Addr addr) { 38110024Sdam.sunwoo@arm.com return tags->findBlock(addr); 38212492Sodanrc@yahoo.com.br } 383 384 bool inCache(Addr addr) { 385 return (tags->findBlock(addr) != 0); 386 } 387 388 bool inMissQueue(Addr addr) { 389 return (mshrQueue.findMatch(addr) != 0); 390 } 391 392 /** 393 * Find next request ready time from among possible sources. 394 */ 395 Tick nextMSHRReadyTime(); 396 397 /** serialize the state of the caches 398 * We currently don't support checkpointing cache state, so this panics. 399 */ 400 virtual void serialize(std::ostream &os); 401 void unserialize(Checkpoint *cp, const std::string §ion); 402}; 403 404#endif // __CACHE_HH__ 405