cache.hh revision 9264:1607119c36bb 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 *          Dave Greene
42 *          Steve Reinhardt
43 *          Ron Dreslinski
44 *          Andreas Hansson
45 */
46
47/**
48 * @file
49 * Describes a cache based on template policies.
50 */
51
52#ifndef __CACHE_HH__
53#define __CACHE_HH__
54
55#include "base/misc.hh" // fatal, panic, and warn
56#include "mem/cache/base.hh"
57#include "mem/cache/blk.hh"
58#include "mem/cache/mshr.hh"
59#include "sim/eventq.hh"
60
61//Forward decleration
62class BasePrefetcher;
63
64/**
65 * A template-policy based cache. The behavior of the cache can be altered by
66 * supplying different template policies. TagStore handles all tag and data
67 * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System"
68 */
69template <class TagStore>
70class Cache : public BaseCache
71{
72  public:
73    /** Define the type of cache block to use. */
74    typedef typename TagStore::BlkType BlkType;
75    /** A typedef for a list of BlkType pointers. */
76    typedef typename TagStore::BlkList BlkList;
77
78  protected:
79
80    /**
81     * The CPU-side port extends the base cache slave port with access
82     * functions for functional, atomic and timing requests.
83     */
84    class CpuSidePort : public CacheSlavePort
85    {
86      private:
87
88        // a pointer to our specific cache implementation
89        Cache<TagStore> *cache;
90
91      protected:
92
93        virtual bool recvTimingSnoopResp(PacketPtr pkt);
94
95        virtual bool recvTimingReq(PacketPtr pkt);
96
97        virtual Tick recvAtomic(PacketPtr pkt);
98
99        virtual void recvFunctional(PacketPtr pkt);
100
101        virtual unsigned deviceBlockSize() const
102        { return cache->getBlockSize(); }
103
104        virtual AddrRangeList getAddrRanges() const;
105
106      public:
107
108        CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
109                    const std::string &_label);
110
111    };
112
113    /**
114     * Override the default behaviour of sendDeferredPacket to enable
115     * the memory-side cache port to also send requests based on the
116     * current MSHR status. This queue has a pointer to our specific
117     * cache implementation and is used by the MemSidePort.
118     */
119    class MemSidePacketQueue : public MasterPacketQueue
120    {
121
122      protected:
123
124        Cache<TagStore> &cache;
125
126      public:
127
128        MemSidePacketQueue(Cache<TagStore> &cache, MasterPort &port,
129                           const std::string &label) :
130            MasterPacketQueue(cache, port, label), cache(cache) { }
131
132        /**
133         * Override the normal sendDeferredPacket and do not only
134         * consider the transmit list (used for responses), but also
135         * requests.
136         */
137        virtual void sendDeferredPacket();
138
139    };
140
141    /**
142     * The memory-side port extends the base cache master port with
143     * access functions for functional, atomic and timing snoops.
144     */
145    class MemSidePort : public CacheMasterPort
146    {
147      private:
148
149        /** The cache-specific queue. */
150        MemSidePacketQueue _queue;
151
152        // a pointer to our specific cache implementation
153        Cache<TagStore> *cache;
154
155      protected:
156
157        virtual void recvTimingSnoopReq(PacketPtr pkt);
158
159        virtual bool recvTimingResp(PacketPtr pkt);
160
161        virtual Tick recvAtomicSnoop(PacketPtr pkt);
162
163        virtual void recvFunctionalSnoop(PacketPtr pkt);
164
165        virtual unsigned deviceBlockSize() const
166        { return cache->getBlockSize(); }
167
168      public:
169
170        MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
171                    const std::string &_label);
172    };
173
174    /** Tag and data Storage */
175    TagStore *tags;
176
177    /** Prefetcher */
178    BasePrefetcher *prefetcher;
179
180    /** Temporary cache block for occasional transitory use */
181    BlkType *tempBlock;
182
183    /**
184     * This cache should allocate a block on a line-sized write miss.
185     */
186    const bool doFastWrites;
187
188    /**
189     * Notify the prefetcher on every access, not just misses.
190     */
191    const bool prefetchOnAccess;
192
193    /**
194     * @todo this is a temporary workaround until the 4-phase code is committed.
195     * upstream caches need this packet until true is returned, so hold it for
196     * deletion until a subsequent call
197     */
198    std::vector<PacketPtr> pendingDelete;
199
200    /**
201     * Does all the processing necessary to perform the provided request.
202     * @param pkt The memory request to perform.
203     * @param lat The latency of the access.
204     * @param writebacks List for any writebacks that need to be performed.
205     * @param update True if the replacement data should be updated.
206     * @return Boolean indicating whether the request was satisfied.
207     */
208    bool access(PacketPtr pkt, BlkType *&blk,
209                int &lat, PacketList &writebacks);
210
211    /**
212     *Handle doing the Compare and Swap function for SPARC.
213     */
214    void cmpAndSwap(BlkType *blk, PacketPtr pkt);
215
216    /**
217     * Find a block frame for new block at address addr, assuming that
218     * the block is not currently in the cache.  Append writebacks if
219     * any to provided packet list.  Return free block frame.  May
220     * return NULL if there are no replaceable blocks at the moment.
221     */
222    BlkType *allocateBlock(Addr addr, PacketList &writebacks);
223
224    /**
225     * Populates a cache block and handles all outstanding requests for the
226     * satisfied fill request. This version takes two memory requests. One
227     * contains the fill data, the other is an optional target to satisfy.
228     * @param pkt The memory request with the fill data.
229     * @param blk The cache block if it already exists.
230     * @param writebacks List for any writebacks that need to be performed.
231     * @return Pointer to the new cache block.
232     */
233    BlkType *handleFill(PacketPtr pkt, BlkType *blk,
234                        PacketList &writebacks);
235
236    void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
237                               bool deferred_response = false,
238                               bool pending_downgrade = false);
239    bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
240
241    void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
242                                bool already_copied, bool pending_inval);
243
244    /**
245     * Sets the blk to the new state.
246     * @param blk The cache block being snooped.
247     * @param new_state The new coherence state for the block.
248     */
249    void handleSnoop(PacketPtr ptk, BlkType *blk,
250                     bool is_timing, bool is_deferred, bool pending_inval);
251
252    /**
253     * Create a writeback request for the given block.
254     * @param blk The block to writeback.
255     * @return The writeback request for the block.
256     */
257    PacketPtr writebackBlk(BlkType *blk);
258
259  public:
260    /** Instantiates a basic cache object. */
261    Cache(const Params *p, TagStore *tags);
262
263    void regStats();
264
265    /**
266     * Performs the access specified by the request.
267     * @param pkt The request to perform.
268     * @return The result of the access.
269     */
270    bool timingAccess(PacketPtr pkt);
271
272    /**
273     * Performs the access specified by the request.
274     * @param pkt The request to perform.
275     * @return The result of the access.
276     */
277    Tick atomicAccess(PacketPtr pkt);
278
279    /**
280     * Performs the access specified by the request.
281     * @param pkt The request to perform.
282     * @param fromCpuSide from the CPU side port or the memory side port
283     */
284    void functionalAccess(PacketPtr pkt, bool fromCpuSide);
285
286    /**
287     * Handles a response (cache line fill/write ack) from the bus.
288     * @param pkt The request being responded to.
289     */
290    void handleResponse(PacketPtr pkt);
291
292    /**
293     * Snoops bus transactions to maintain coherence.
294     * @param pkt The current bus transaction.
295     */
296    void snoopTiming(PacketPtr pkt);
297
298    /**
299     * Snoop for the provided request in the cache and return the estimated
300     * time of completion.
301     * @param pkt The memory request to snoop
302     * @return The estimated completion time.
303     */
304    Tick snoopAtomic(PacketPtr pkt);
305
306    /**
307     * Squash all requests associated with specified thread.
308     * intended for use by I-cache.
309     * @param threadNum The thread to squash.
310     */
311    void squash(int threadNum);
312
313    /**
314     * Generate an appropriate downstream bus request packet for the
315     * given parameters.
316     * @param cpu_pkt  The upstream request that needs to be satisfied.
317     * @param blk The block currently in the cache corresponding to
318     * cpu_pkt (NULL if none).
319     * @param needsExclusive  Indicates that an exclusive copy is required
320     * even if the request in cpu_pkt doesn't indicate that.
321     * @return A new Packet containing the request, or NULL if the
322     * current request in cpu_pkt should just be forwarded on.
323     */
324    PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
325                           bool needsExclusive);
326
327    /**
328     * Return the next MSHR to service, either a pending miss from the
329     * mshrQueue, a buffered write from the write buffer, or something
330     * from the prefetcher.  This function is responsible for
331     * prioritizing among those sources on the fly.
332     */
333    MSHR *getNextMSHR();
334
335    /**
336     * Selects an outstanding request to service.  Called when the
337     * cache gets granted the downstream bus in timing mode.
338     * @return The request to service, NULL if none found.
339     */
340    PacketPtr getTimingPacket();
341
342    /**
343     * Marks a request as in service (sent on the bus). This can have side
344     * effect since storage for no response commands is deallocated once they
345     * are successfully sent.
346     * @param pkt The request that was sent on the bus.
347     */
348    void markInService(MSHR *mshr, PacketPtr pkt = 0);
349
350    /**
351     * Return whether there are any outstanding misses.
352     */
353    bool outstandingMisses() const
354    {
355        return mshrQueue.allocated != 0;
356    }
357
358    CacheBlk *findBlock(Addr addr) {
359        return tags->findBlock(addr);
360    }
361
362    bool inCache(Addr addr) {
363        return (tags->findBlock(addr) != 0);
364    }
365
366    bool inMissQueue(Addr addr) {
367        return (mshrQueue.findMatch(addr) != 0);
368    }
369
370    /**
371     * Find next request ready time from among possible sources.
372     */
373    Tick nextMSHRReadyTime();
374
375    /** serialize the state of the caches
376     * We currently don't support checkpointing cache state, so this panics.
377     */
378    virtual void serialize(std::ostream &os);
379    void unserialize(Checkpoint *cp, const std::string &section);
380};
381
382#endif // __CACHE_HH__
383