cache.hh revision 8831
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Dave Greene 42 * Steve Reinhardt 43 * Ron Dreslinski 44 */ 45 46/** 47 * @file 48 * Describes a cache based on template policies. 49 */ 50 51#ifndef __CACHE_HH__ 52#define __CACHE_HH__ 53 54#include "base/misc.hh" // fatal, panic, and warn 55#include "mem/cache/base.hh" 56#include "mem/cache/blk.hh" 57#include "mem/cache/mshr.hh" 58#include "sim/eventq.hh" 59 60//Forward decleration 61class BasePrefetcher; 62 63/** 64 * A template-policy based cache. The behavior of the cache can be altered by 65 * supplying different template policies. TagStore handles all tag and data 66 * storage @sa TagStore. 67 */ 68template <class TagStore> 69class Cache : public BaseCache 70{ 71 public: 72 /** Define the type of cache block to use. */ 73 typedef typename TagStore::BlkType BlkType; 74 /** A typedef for a list of BlkType pointers. */ 75 typedef typename TagStore::BlkList BlkList; 76 77 protected: 78 79 class CpuSidePort : public CachePort 80 { 81 public: 82 CpuSidePort(const std::string &_name, 83 Cache<TagStore> *_cache, 84 const std::string &_label); 85 86 // BaseCache::CachePort just has a BaseCache *; this function 87 // lets us get back the type info we lost when we stored the 88 // cache pointer there. 89 Cache<TagStore> *myCache() { 90 return static_cast<Cache<TagStore> *>(cache); 91 } 92 93 virtual AddrRangeList getAddrRanges(); 94 95 virtual bool recvTiming(PacketPtr pkt); 96 97 virtual Tick recvAtomic(PacketPtr pkt); 98 99 virtual void recvFunctional(PacketPtr pkt); 100 }; 101 102 class MemSidePort : public CachePort 103 { 104 public: 105 MemSidePort(const std::string &_name, 106 Cache<TagStore> *_cache, 107 const std::string &_label); 108 109 // BaseCache::CachePort just has a BaseCache *; this function 110 // lets us get back the type info we lost when we stored the 111 // cache pointer there. 112 Cache<TagStore> *myCache() { 113 return static_cast<Cache<TagStore> *>(cache); 114 } 115 116 void sendPacket(); 117 118 void processSendEvent(); 119 120 virtual bool isSnooping(); 121 122 virtual bool recvTiming(PacketPtr pkt); 123 124 virtual void recvRetry(); 125 126 virtual Tick recvAtomic(PacketPtr pkt); 127 128 virtual void recvFunctional(PacketPtr pkt); 129 130 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent> 131 SendEvent; 132 }; 133 134 /** Tag and data Storage */ 135 TagStore *tags; 136 137 /** Prefetcher */ 138 BasePrefetcher *prefetcher; 139 140 /** Temporary cache block for occasional transitory use */ 141 BlkType *tempBlock; 142 143 /** 144 * This cache should allocate a block on a line-sized write miss. 145 */ 146 const bool doFastWrites; 147 148 /** 149 * Notify the prefetcher on every access, not just misses. 150 */ 151 const bool prefetchOnAccess; 152 153 /** 154 * Does all the processing necessary to perform the provided request. 155 * @param pkt The memory request to perform. 156 * @param lat The latency of the access. 157 * @param writebacks List for any writebacks that need to be performed. 158 * @param update True if the replacement data should be updated. 159 * @return Boolean indicating whether the request was satisfied. 160 */ 161 bool access(PacketPtr pkt, BlkType *&blk, 162 int &lat, PacketList &writebacks); 163 164 /** 165 *Handle doing the Compare and Swap function for SPARC. 166 */ 167 void cmpAndSwap(BlkType *blk, PacketPtr pkt); 168 169 /** 170 * Find a block frame for new block at address addr, assuming that 171 * the block is not currently in the cache. Append writebacks if 172 * any to provided packet list. Return free block frame. May 173 * return NULL if there are no replaceable blocks at the moment. 174 */ 175 BlkType *allocateBlock(Addr addr, PacketList &writebacks); 176 177 /** 178 * Populates a cache block and handles all outstanding requests for the 179 * satisfied fill request. This version takes two memory requests. One 180 * contains the fill data, the other is an optional target to satisfy. 181 * @param pkt The memory request with the fill data. 182 * @param blk The cache block if it already exists. 183 * @param writebacks List for any writebacks that need to be performed. 184 * @return Pointer to the new cache block. 185 */ 186 BlkType *handleFill(PacketPtr pkt, BlkType *blk, 187 PacketList &writebacks); 188 189 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk, 190 bool deferred_response = false, 191 bool pending_downgrade = false); 192 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); 193 194 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, 195 bool already_copied, bool pending_inval); 196 197 /** 198 * Sets the blk to the new state. 199 * @param blk The cache block being snooped. 200 * @param new_state The new coherence state for the block. 201 */ 202 void handleSnoop(PacketPtr ptk, BlkType *blk, 203 bool is_timing, bool is_deferred, bool pending_inval); 204 205 /** 206 * Create a writeback request for the given block. 207 * @param blk The block to writeback. 208 * @return The writeback request for the block. 209 */ 210 PacketPtr writebackBlk(BlkType *blk); 211 212 public: 213 /** Instantiates a basic cache object. */ 214 Cache(const Params *p, TagStore *tags); 215 216 virtual Port *getPort(const std::string &if_name, int idx = -1); 217 218 void regStats(); 219 220 /** 221 * Performs the access specified by the request. 222 * @param pkt The request to perform. 223 * @return The result of the access. 224 */ 225 bool timingAccess(PacketPtr pkt); 226 227 /** 228 * Performs the access specified by the request. 229 * @param pkt The request to perform. 230 * @return The result of the access. 231 */ 232 Tick atomicAccess(PacketPtr pkt); 233 234 /** 235 * Performs the access specified by the request. 236 * @param pkt The request to perform. 237 * @param fromCpuSide from the CPU side port or the memory side port 238 */ 239 void functionalAccess(PacketPtr pkt, bool fromCpuSide); 240 241 /** 242 * Handles a response (cache line fill/write ack) from the bus. 243 * @param pkt The request being responded to. 244 */ 245 void handleResponse(PacketPtr pkt); 246 247 /** 248 * Snoops bus transactions to maintain coherence. 249 * @param pkt The current bus transaction. 250 */ 251 void snoopTiming(PacketPtr pkt); 252 253 /** 254 * Snoop for the provided request in the cache and return the estimated 255 * time of completion. 256 * @param pkt The memory request to snoop 257 * @return The estimated completion time. 258 */ 259 Tick snoopAtomic(PacketPtr pkt); 260 261 /** 262 * Squash all requests associated with specified thread. 263 * intended for use by I-cache. 264 * @param threadNum The thread to squash. 265 */ 266 void squash(int threadNum); 267 268 /** 269 * Generate an appropriate downstream bus request packet for the 270 * given parameters. 271 * @param cpu_pkt The upstream request that needs to be satisfied. 272 * @param blk The block currently in the cache corresponding to 273 * cpu_pkt (NULL if none). 274 * @param needsExclusive Indicates that an exclusive copy is required 275 * even if the request in cpu_pkt doesn't indicate that. 276 * @return A new Packet containing the request, or NULL if the 277 * current request in cpu_pkt should just be forwarded on. 278 */ 279 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 280 bool needsExclusive); 281 282 /** 283 * Return the next MSHR to service, either a pending miss from the 284 * mshrQueue, a buffered write from the write buffer, or something 285 * from the prefetcher. This function is responsible for 286 * prioritizing among those sources on the fly. 287 */ 288 MSHR *getNextMSHR(); 289 290 /** 291 * Selects an outstanding request to service. Called when the 292 * cache gets granted the downstream bus in timing mode. 293 * @return The request to service, NULL if none found. 294 */ 295 PacketPtr getTimingPacket(); 296 297 /** 298 * Marks a request as in service (sent on the bus). This can have side 299 * effect since storage for no response commands is deallocated once they 300 * are successfully sent. 301 * @param pkt The request that was sent on the bus. 302 */ 303 void markInService(MSHR *mshr, PacketPtr pkt = 0); 304 305 /** 306 * Perform the given writeback request. 307 * @param pkt The writeback request. 308 */ 309 void doWriteback(PacketPtr pkt); 310 311 /** 312 * Return whether there are any outstanding misses. 313 */ 314 bool outstandingMisses() const 315 { 316 return mshrQueue.allocated != 0; 317 } 318 319 CacheBlk *findBlock(Addr addr) { 320 return tags->findBlock(addr); 321 } 322 323 bool inCache(Addr addr) { 324 return (tags->findBlock(addr) != 0); 325 } 326 327 bool inMissQueue(Addr addr) { 328 return (mshrQueue.findMatch(addr) != 0); 329 } 330 331 /** 332 * Find next request ready time from among possible sources. 333 */ 334 Tick nextMSHRReadyTime(); 335}; 336 337#endif // __CACHE_HH__ 338