cache.hh revision 5314:e902f12a3af1 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Dave Greene
30 *          Steve Reinhardt
31 *          Ron Dreslinski
32 */
33
34/**
35 * @file
36 * Describes a cache based on template policies.
37 */
38
39#ifndef __CACHE_HH__
40#define __CACHE_HH__
41
42#include "base/misc.hh" // fatal, panic, and warn
43
44#include "mem/cache/base_cache.hh"
45#include "mem/cache/cache_blk.hh"
46#include "mem/cache/miss/mshr.hh"
47
48#include "sim/eventq.hh"
49
50//Forward decleration
51class BasePrefetcher;
52
53/**
54 * A template-policy based cache. The behavior of the cache can be altered by
55 * supplying different template policies. TagStore handles all tag and data
56 * storage @sa TagStore.
57 */
58template <class TagStore>
59class Cache : public BaseCache
60{
61  public:
62    /** Define the type of cache block to use. */
63    typedef typename TagStore::BlkType BlkType;
64    /** A typedef for a list of BlkType pointers. */
65    typedef typename TagStore::BlkList BlkList;
66
67    bool prefetchAccess;
68
69  protected:
70
71    class CpuSidePort : public CachePort
72    {
73      public:
74        CpuSidePort(const std::string &_name,
75                    Cache<TagStore> *_cache,
76                    const std::string &_label,
77                    std::vector<Range<Addr> > filterRanges);
78
79        // BaseCache::CachePort just has a BaseCache *; this function
80        // lets us get back the type info we lost when we stored the
81        // cache pointer there.
82        Cache<TagStore> *myCache() {
83            return static_cast<Cache<TagStore> *>(cache);
84        }
85
86        virtual void getDeviceAddressRanges(AddrRangeList &resp,
87                                            bool &snoop);
88
89        virtual bool recvTiming(PacketPtr pkt);
90
91        virtual Tick recvAtomic(PacketPtr pkt);
92
93        virtual void recvFunctional(PacketPtr pkt);
94    };
95
96    class MemSidePort : public CachePort
97    {
98      public:
99        MemSidePort(const std::string &_name,
100                    Cache<TagStore> *_cache,
101                    const std::string &_label,
102                    std::vector<Range<Addr> > filterRanges);
103
104        // BaseCache::CachePort just has a BaseCache *; this function
105        // lets us get back the type info we lost when we stored the
106        // cache pointer there.
107        Cache<TagStore> *myCache() {
108            return static_cast<Cache<TagStore> *>(cache);
109        }
110
111        void sendPacket();
112
113        void processSendEvent();
114
115        virtual void getDeviceAddressRanges(AddrRangeList &resp,
116                                            bool &snoop);
117
118        virtual bool recvTiming(PacketPtr pkt);
119
120        virtual void recvRetry();
121
122        virtual Tick recvAtomic(PacketPtr pkt);
123
124        virtual void recvFunctional(PacketPtr pkt);
125
126        typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
127                SendEvent;
128    };
129
130    /** Tag and data Storage */
131    TagStore *tags;
132
133    /** Prefetcher */
134    BasePrefetcher *prefetcher;
135
136    /** Temporary cache block for occasional transitory use */
137    BlkType *tempBlock;
138
139    /**
140     * Can this cache should allocate a block on a line-sized write miss.
141     */
142    const bool doFastWrites;
143
144    const bool prefetchMiss;
145
146    /**
147     * Handle a replacement for the given request.
148     * @param blk A pointer to the block, usually NULL
149     * @param pkt The memory request to satisfy.
150     * @param new_state The new state of the block.
151     * @param writebacks A list to store any generated writebacks.
152     */
153    BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
154                           CacheBlk::State new_state, PacketList &writebacks);
155
156    /**
157     * Does all the processing necessary to perform the provided request.
158     * @param pkt The memory request to perform.
159     * @param lat The latency of the access.
160     * @param writebacks List for any writebacks that need to be performed.
161     * @param update True if the replacement data should be updated.
162     * @return Pointer to the cache block touched by the request. NULL if it
163     * was a miss.
164     */
165    bool access(PacketPtr pkt, BlkType *&blk, int &lat);
166
167    /**
168     *Handle doing the Compare and Swap function for SPARC.
169     */
170    void cmpAndSwap(BlkType *blk, PacketPtr pkt);
171
172    /**
173     * Populates a cache block and handles all outstanding requests for the
174     * satisfied fill request. This version takes two memory requests. One
175     * contains the fill data, the other is an optional target to satisfy.
176     * Used for Cache::probe.
177     * @param pkt The memory request with the fill data.
178     * @param blk The cache block if it already exists.
179     * @param writebacks List for any writebacks that need to be performed.
180     * @return Pointer to the new cache block.
181     */
182    BlkType *handleFill(PacketPtr pkt, BlkType *blk,
183                        PacketList &writebacks);
184
185    void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
186    bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
187
188    void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
189                                bool already_copied);
190
191    /**
192     * Sets the blk to the new state.
193     * @param blk The cache block being snooped.
194     * @param new_state The new coherence state for the block.
195     */
196    void handleSnoop(PacketPtr ptk, BlkType *blk,
197                     bool is_timing, bool is_deferred);
198
199    /**
200     * Create a writeback request for the given block.
201     * @param blk The block to writeback.
202     * @return The writeback request for the block.
203     */
204    PacketPtr writebackBlk(BlkType *blk);
205
206  public:
207    /** Instantiates a basic cache object. */
208    Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher);
209
210    virtual Port *getPort(const std::string &if_name, int idx = -1);
211    virtual void deletePortRefs(Port *p);
212
213    void regStats();
214
215    /**
216     * Performs the access specified by the request.
217     * @param pkt The request to perform.
218     * @return The result of the access.
219     */
220    bool timingAccess(PacketPtr pkt);
221
222    /**
223     * Performs the access specified by the request.
224     * @param pkt The request to perform.
225     * @return The result of the access.
226     */
227    Tick atomicAccess(PacketPtr pkt);
228
229    /**
230     * Performs the access specified by the request.
231     * @param pkt The request to perform.
232     * @return The result of the access.
233     */
234    void functionalAccess(PacketPtr pkt, CachePort *incomingPort,
235                          CachePort *otherSidePort);
236
237    /**
238     * Handles a response (cache line fill/write ack) from the bus.
239     * @param pkt The request being responded to.
240     */
241    void handleResponse(PacketPtr pkt);
242
243    /**
244     * Snoops bus transactions to maintain coherence.
245     * @param pkt The current bus transaction.
246     */
247    void snoopTiming(PacketPtr pkt);
248
249    /**
250     * Snoop for the provided request in the cache and return the estimated
251     * time of completion.
252     * @param pkt The memory request to snoop
253     * @return The estimated completion time.
254     */
255    Tick snoopAtomic(PacketPtr pkt);
256
257    /**
258     * Squash all requests associated with specified thread.
259     * intended for use by I-cache.
260     * @param threadNum The thread to squash.
261     */
262    void squash(int threadNum);
263
264    /**
265     * Selects a outstanding request to service.
266     * @return The request to service, NULL if none found.
267     */
268    PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
269                           bool needsExclusive);
270    MSHR *getNextMSHR();
271    PacketPtr getTimingPacket();
272
273    /**
274     * Marks a request as in service (sent on the bus). This can have side
275     * effect since storage for no response commands is deallocated once they
276     * are successfully sent.
277     * @param pkt The request that was sent on the bus.
278     */
279    void markInService(MSHR *mshr);
280
281    /**
282     * Perform the given writeback request.
283     * @param pkt The writeback request.
284     */
285    void doWriteback(PacketPtr pkt);
286
287    /**
288     * Return whether there are any outstanding misses.
289     */
290    bool outstandingMisses() const
291    {
292        return mshrQueue.allocated != 0;
293    }
294
295    CacheBlk *findBlock(Addr addr) {
296        return tags->findBlock(addr);
297    }
298
299    bool inCache(Addr addr) {
300        return (tags->findBlock(addr) != 0);
301    }
302
303    bool inMissQueue(Addr addr) {
304        return (mshrQueue.findMatch(addr) != 0);
305    }
306};
307
308#endif // __CACHE_HH__
309