cache.hh revision 5034:6186ef720dd4 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Dave Greene
30 *          Steve Reinhardt
31 *          Ron Dreslinski
32 */
33
34/**
35 * @file
36 * Describes a cache based on template policies.
37 */
38
39#ifndef __CACHE_HH__
40#define __CACHE_HH__
41
42#include "base/misc.hh" // fatal, panic, and warn
43
44#include "mem/cache/base_cache.hh"
45#include "mem/cache/cache_blk.hh"
46#include "mem/cache/miss/mshr.hh"
47
48#include "sim/eventq.hh"
49
50//Forward decleration
51class BasePrefetcher;
52
53/**
54 * A template-policy based cache. The behavior of the cache can be altered by
55 * supplying different template policies. TagStore handles all tag and data
56 * storage @sa TagStore.
57 */
58template <class TagStore>
59class Cache : public BaseCache
60{
61  public:
62    /** Define the type of cache block to use. */
63    typedef typename TagStore::BlkType BlkType;
64    /** A typedef for a list of BlkType pointers. */
65    typedef typename TagStore::BlkList BlkList;
66
67    bool prefetchAccess;
68
69  protected:
70
71    class CpuSidePort : public CachePort
72    {
73      public:
74        CpuSidePort(const std::string &_name,
75                    Cache<TagStore> *_cache,
76                    std::vector<Range<Addr> > filterRanges);
77
78        // BaseCache::CachePort just has a BaseCache *; this function
79        // lets us get back the type info we lost when we stored the
80        // cache pointer there.
81        Cache<TagStore> *myCache() {
82            return static_cast<Cache<TagStore> *>(cache);
83        }
84
85        virtual void getDeviceAddressRanges(AddrRangeList &resp,
86                                            bool &snoop);
87
88        virtual bool recvTiming(PacketPtr pkt);
89
90        virtual Tick recvAtomic(PacketPtr pkt);
91
92        virtual void recvFunctional(PacketPtr pkt);
93    };
94
95    class MemSidePort : public CachePort
96    {
97      public:
98        MemSidePort(const std::string &_name,
99                    Cache<TagStore> *_cache,
100                    std::vector<Range<Addr> > filterRanges);
101
102        // BaseCache::CachePort just has a BaseCache *; this function
103        // lets us get back the type info we lost when we stored the
104        // cache pointer there.
105        Cache<TagStore> *myCache() {
106            return static_cast<Cache<TagStore> *>(cache);
107        }
108
109        void sendPacket();
110
111        void processSendEvent();
112
113        virtual void getDeviceAddressRanges(AddrRangeList &resp,
114                                            bool &snoop);
115
116        virtual bool recvTiming(PacketPtr pkt);
117
118        virtual void recvRetry();
119
120        virtual Tick recvAtomic(PacketPtr pkt);
121
122        virtual void recvFunctional(PacketPtr pkt);
123
124        typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
125                SendEvent;
126    };
127
128    /** Tag and data Storage */
129    TagStore *tags;
130
131    /** Prefetcher */
132    BasePrefetcher *prefetcher;
133
134    /** Temporary cache block for occasional transitory use */
135    BlkType *tempBlock;
136
137    /**
138     * Can this cache should allocate a block on a line-sized write miss.
139     */
140    const bool doFastWrites;
141
142    const bool prefetchMiss;
143
144    /**
145     * Handle a replacement for the given request.
146     * @param blk A pointer to the block, usually NULL
147     * @param pkt The memory request to satisfy.
148     * @param new_state The new state of the block.
149     * @param writebacks A list to store any generated writebacks.
150     */
151    BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
152                           CacheBlk::State new_state, PacketList &writebacks);
153
154    /**
155     * Does all the processing necessary to perform the provided request.
156     * @param pkt The memory request to perform.
157     * @param lat The latency of the access.
158     * @param writebacks List for any writebacks that need to be performed.
159     * @param update True if the replacement data should be updated.
160     * @return Pointer to the cache block touched by the request. NULL if it
161     * was a miss.
162     */
163    bool access(PacketPtr pkt, BlkType *&blk, int &lat);
164
165    /**
166     *Handle doing the Compare and Swap function for SPARC.
167     */
168    void cmpAndSwap(BlkType *blk, PacketPtr pkt);
169
170    /**
171     * Populates a cache block and handles all outstanding requests for the
172     * satisfied fill request. This version takes two memory requests. One
173     * contains the fill data, the other is an optional target to satisfy.
174     * Used for Cache::probe.
175     * @param pkt The memory request with the fill data.
176     * @param blk The cache block if it already exists.
177     * @param writebacks List for any writebacks that need to be performed.
178     * @return Pointer to the new cache block.
179     */
180    BlkType *handleFill(PacketPtr pkt, BlkType *blk,
181                        PacketList &writebacks);
182
183    void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
184    bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
185
186    void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
187                                bool already_copied);
188
189    /**
190     * Sets the blk to the new state.
191     * @param blk The cache block being snooped.
192     * @param new_state The new coherence state for the block.
193     */
194    void handleSnoop(PacketPtr ptk, BlkType *blk,
195                     bool is_timing, bool is_deferred);
196
197    /**
198     * Create a writeback request for the given block.
199     * @param blk The block to writeback.
200     * @return The writeback request for the block.
201     */
202    PacketPtr writebackBlk(BlkType *blk);
203
204  public:
205    /** Instantiates a basic cache object. */
206    Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher);
207
208    virtual Port *getPort(const std::string &if_name, int idx = -1);
209    virtual void deletePortRefs(Port *p);
210
211    void regStats();
212
213    /**
214     * Performs the access specified by the request.
215     * @param pkt The request to perform.
216     * @return The result of the access.
217     */
218    bool timingAccess(PacketPtr pkt);
219
220    /**
221     * Performs the access specified by the request.
222     * @param pkt The request to perform.
223     * @return The result of the access.
224     */
225    Tick atomicAccess(PacketPtr pkt);
226
227    /**
228     * Performs the access specified by the request.
229     * @param pkt The request to perform.
230     * @return The result of the access.
231     */
232    void functionalAccess(PacketPtr pkt, CachePort *otherSidePort);
233
234    /**
235     * Handles a response (cache line fill/write ack) from the bus.
236     * @param pkt The request being responded to.
237     */
238    void handleResponse(PacketPtr pkt);
239
240    /**
241     * Snoops bus transactions to maintain coherence.
242     * @param pkt The current bus transaction.
243     */
244    void snoopTiming(PacketPtr pkt);
245
246    /**
247     * Snoop for the provided request in the cache and return the estimated
248     * time of completion.
249     * @param pkt The memory request to snoop
250     * @return The estimated completion time.
251     */
252    Tick snoopAtomic(PacketPtr pkt);
253
254    /**
255     * Squash all requests associated with specified thread.
256     * intended for use by I-cache.
257     * @param threadNum The thread to squash.
258     */
259    void squash(int threadNum);
260
261    /**
262     * Selects a outstanding request to service.
263     * @return The request to service, NULL if none found.
264     */
265    PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
266                           bool needsExclusive);
267    MSHR *getNextMSHR();
268    PacketPtr getTimingPacket();
269
270    /**
271     * Marks a request as in service (sent on the bus). This can have side
272     * effect since storage for no response commands is deallocated once they
273     * are successfully sent.
274     * @param pkt The request that was sent on the bus.
275     */
276    void markInService(MSHR *mshr);
277
278    /**
279     * Perform the given writeback request.
280     * @param pkt The writeback request.
281     */
282    void doWriteback(PacketPtr pkt);
283
284    /**
285     * Return whether there are any outstanding misses.
286     */
287    bool outstandingMisses() const
288    {
289        return mshrQueue.allocated != 0;
290    }
291
292    CacheBlk *findBlock(Addr addr) {
293        return tags->findBlock(addr);
294    }
295
296    bool inCache(Addr addr) {
297        return (tags->findBlock(addr) != 0);
298    }
299
300    bool inMissQueue(Addr addr) {
301        return (mshrQueue.findMatch(addr) != 0);
302    }
303};
304
305#endif // __CACHE_HH__
306