cache.hh revision 4671:5d29d3be0f79 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Dave Greene
30 *          Steve Reinhardt
31 *          Ron Dreslinski
32 */
33
34/**
35 * @file
36 * Describes a cache based on template policies.
37 */
38
39#ifndef __CACHE_HH__
40#define __CACHE_HH__
41
42#include "base/compression/base.hh"
43#include "base/misc.hh" // fatal, panic, and warn
44#include "cpu/smt.hh" // SMT_MAX_THREADS
45
46#include "mem/cache/base_cache.hh"
47#include "mem/cache/cache_blk.hh"
48#include "mem/cache/miss/mshr.hh"
49
50#include "sim/eventq.hh"
51
52//Forward decleration
53class BasePrefetcher;
54
55/**
56 * A template-policy based cache. The behavior of the cache can be altered by
57 * supplying different template policies. TagStore handles all tag and data
58 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
59 * @sa MissQueue. Coherence handles all coherence policy details @sa
60 * UniCoherence, SimpleMultiCoherence.
61 */
62template <class TagStore, class Coherence>
63class Cache : public BaseCache
64{
65  public:
66    /** Define the type of cache block to use. */
67    typedef typename TagStore::BlkType BlkType;
68    /** A typedef for a list of BlkType pointers. */
69    typedef typename TagStore::BlkList BlkList;
70
71    bool prefetchAccess;
72
73  protected:
74
75    class CpuSidePort : public CachePort
76    {
77      public:
78        CpuSidePort(const std::string &_name,
79                    Cache<TagStore,Coherence> *_cache);
80
81        // BaseCache::CachePort just has a BaseCache *; this function
82        // lets us get back the type info we lost when we stored the
83        // cache pointer there.
84        Cache<TagStore,Coherence> *myCache() {
85            return static_cast<Cache<TagStore,Coherence> *>(cache);
86        }
87
88        virtual void getDeviceAddressRanges(AddrRangeList &resp,
89                                            bool &snoop);
90
91        virtual bool recvTiming(PacketPtr pkt);
92
93        virtual Tick recvAtomic(PacketPtr pkt);
94
95        virtual void recvFunctional(PacketPtr pkt);
96    };
97
98    class MemSidePort : public CachePort
99    {
100      public:
101        MemSidePort(const std::string &_name,
102                    Cache<TagStore,Coherence> *_cache);
103
104        // BaseCache::CachePort just has a BaseCache *; this function
105        // lets us get back the type info we lost when we stored the
106        // cache pointer there.
107        Cache<TagStore,Coherence> *myCache() {
108            return static_cast<Cache<TagStore,Coherence> *>(cache);
109        }
110
111        void sendPacket();
112
113        void processSendEvent();
114
115        virtual void getDeviceAddressRanges(AddrRangeList &resp,
116                                            bool &snoop);
117
118        virtual bool recvTiming(PacketPtr pkt);
119
120        virtual void recvRetry();
121
122        virtual Tick recvAtomic(PacketPtr pkt);
123
124        virtual void recvFunctional(PacketPtr pkt);
125
126        typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
127                SendEvent;
128    };
129
130    /** Tag and data Storage */
131    TagStore *tags;
132
133    /** Coherence protocol. */
134    Coherence *coherence;
135
136    /** Prefetcher */
137    BasePrefetcher *prefetcher;
138
139    /** Temporary cache block for occasional transitory use */
140    BlkType *tempBlock;
141
142    /**
143     * Can this cache should allocate a block on a line-sized write miss.
144     */
145    const bool doFastWrites;
146
147    const bool prefetchMiss;
148
149    /**
150     * Handle a replacement for the given request.
151     * @param blk A pointer to the block, usually NULL
152     * @param pkt The memory request to satisfy.
153     * @param new_state The new state of the block.
154     * @param writebacks A list to store any generated writebacks.
155     */
156    BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
157                           CacheBlk::State new_state, PacketList &writebacks);
158
159    /**
160     * Does all the processing necessary to perform the provided request.
161     * @param pkt The memory request to perform.
162     * @param lat The latency of the access.
163     * @param writebacks List for any writebacks that need to be performed.
164     * @param update True if the replacement data should be updated.
165     * @return Pointer to the cache block touched by the request. NULL if it
166     * was a miss.
167     */
168    bool access(PacketPtr pkt, BlkType *&blk, int &lat);
169
170    /**
171     *Handle doing the Compare and Swap function for SPARC.
172     */
173    void cmpAndSwap(BlkType *blk, PacketPtr pkt);
174
175    /**
176     * Populates a cache block and handles all outstanding requests for the
177     * satisfied fill request. This version takes two memory requests. One
178     * contains the fill data, the other is an optional target to satisfy.
179     * Used for Cache::probe.
180     * @param pkt The memory request with the fill data.
181     * @param blk The cache block if it already exists.
182     * @param writebacks List for any writebacks that need to be performed.
183     * @return Pointer to the new cache block.
184     */
185    BlkType *handleFill(PacketPtr pkt, BlkType *blk,
186                        PacketList &writebacks);
187
188    void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
189    bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
190
191    void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
192                                bool already_copied);
193
194    /**
195     * Sets the blk to the new state.
196     * @param blk The cache block being snooped.
197     * @param new_state The new coherence state for the block.
198     */
199    void handleSnoop(PacketPtr ptk, BlkType *blk,
200                     bool is_timing, bool is_deferred);
201
202    /**
203     * Create a writeback request for the given block.
204     * @param blk The block to writeback.
205     * @return The writeback request for the block.
206     */
207    PacketPtr writebackBlk(BlkType *blk);
208
209  public:
210
211    class Params
212    {
213      public:
214        TagStore *tags;
215        Coherence *coherence;
216        BaseCache::Params baseParams;
217        BasePrefetcher*prefetcher;
218        bool prefetchAccess;
219        const bool doFastWrites;
220        const bool prefetchMiss;
221
222        Params(TagStore *_tags, Coherence *coh,
223               BaseCache::Params params,
224               BasePrefetcher *_prefetcher,
225               bool prefetch_access, int hit_latency,
226               bool do_fast_writes,
227               bool prefetch_miss)
228            : tags(_tags), coherence(coh),
229              baseParams(params),
230              prefetcher(_prefetcher), prefetchAccess(prefetch_access),
231              doFastWrites(do_fast_writes),
232              prefetchMiss(prefetch_miss)
233        {
234        }
235    };
236
237    /** Instantiates a basic cache object. */
238    Cache(const std::string &_name, Params &params);
239
240    virtual Port *getPort(const std::string &if_name, int idx = -1);
241    virtual void deletePortRefs(Port *p);
242
243    void regStats();
244
245    /**
246     * Performs the access specified by the request.
247     * @param pkt The request to perform.
248     * @return The result of the access.
249     */
250    bool timingAccess(PacketPtr pkt);
251
252    /**
253     * Performs the access specified by the request.
254     * @param pkt The request to perform.
255     * @return The result of the access.
256     */
257    Tick atomicAccess(PacketPtr pkt);
258
259    /**
260     * Performs the access specified by the request.
261     * @param pkt The request to perform.
262     * @return The result of the access.
263     */
264    void functionalAccess(PacketPtr pkt, CachePort *otherSidePort);
265
266    /**
267     * Handles a response (cache line fill/write ack) from the bus.
268     * @param pkt The request being responded to.
269     */
270    void handleResponse(PacketPtr pkt);
271
272    /**
273     * Snoops bus transactions to maintain coherence.
274     * @param pkt The current bus transaction.
275     */
276    void snoopTiming(PacketPtr pkt);
277
278    /**
279     * Snoop for the provided request in the cache and return the estimated
280     * time of completion.
281     * @param pkt The memory request to snoop
282     * @return The estimated completion time.
283     */
284    Tick snoopAtomic(PacketPtr pkt);
285
286    /**
287     * Squash all requests associated with specified thread.
288     * intended for use by I-cache.
289     * @param threadNum The thread to squash.
290     */
291    void squash(int threadNum);
292
293    /**
294     * Selects a outstanding request to service.
295     * @return The request to service, NULL if none found.
296     */
297    PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
298                           bool needsExclusive);
299    MSHR *getNextMSHR();
300    PacketPtr getTimingPacket();
301
302    /**
303     * Marks a request as in service (sent on the bus). This can have side
304     * effect since storage for no response commands is deallocated once they
305     * are successfully sent.
306     * @param pkt The request that was sent on the bus.
307     */
308    void markInService(MSHR *mshr);
309
310    /**
311     * Perform the given writeback request.
312     * @param pkt The writeback request.
313     */
314    void doWriteback(PacketPtr pkt);
315
316    /**
317     * Return whether there are any outstanding misses.
318     */
319    bool outstandingMisses() const
320    {
321        return mshrQueue.allocated != 0;
322    }
323
324    CacheBlk *findBlock(Addr addr) {
325        return tags->findBlock(addr);
326    }
327
328    bool inCache(Addr addr) {
329        return (tags->findBlock(addr) != 0);
330    }
331
332    bool inMissQueue(Addr addr) {
333        return (mshrQueue.findMatch(addr) != 0);
334    }
335};
336
337#endif // __CACHE_HH__
338