cache.hh revision 13358:5e1605b47a21
12381SN/A/* 210405Sandreas.hansson@arm.com * Copyright (c) 2012-2018 ARM Limited 38711SN/A * All rights reserved. 48711SN/A * 58711SN/A * The license below extends only to copyright in the software and shall 68711SN/A * not be construed as granting a license to any other intellectual 78711SN/A * property including but not limited to intellectual property relating 88711SN/A * to a hardware implementation of the functionality of the software 98711SN/A * licensed hereunder. You may use the software subject to the license 108711SN/A * terms below provided that you ensure that this notice is replicated 118711SN/A * unmodified and in its entirety in all distributions of the software, 128711SN/A * modified or unmodified, in source code or in binary form. 138711SN/A * 142381SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152381SN/A * All rights reserved. 162381SN/A * 172381SN/A * Redistribution and use in source and binary forms, with or without 182381SN/A * modification, are permitted provided that the following conditions are 192381SN/A * met: redistributions of source code must retain the above copyright 202381SN/A * notice, this list of conditions and the following disclaimer; 212381SN/A * redistributions in binary form must reproduce the above copyright 222381SN/A * notice, this list of conditions and the following disclaimer in the 232381SN/A * documentation and/or other materials provided with the distribution; 242381SN/A * neither the name of the copyright holders nor the names of its 252381SN/A * contributors may be used to endorse or promote products derived from 262381SN/A * this software without specific prior written permission. 272381SN/A * 282381SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292381SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302381SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312381SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322381SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332381SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342381SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352381SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362381SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372381SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382381SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Erik Hallnor 412772SN/A * Dave Greene 428715SN/A * Steve Reinhardt 438922SN/A * Ron Dreslinski 442381SN/A * Andreas Hansson 452381SN/A */ 462381SN/A 472982SN/A/** 4810405Sandreas.hansson@arm.com * @file 492381SN/A * Describes a cache 502381SN/A */ 5110405Sandreas.hansson@arm.com 5210405Sandreas.hansson@arm.com#ifndef __MEM_CACHE_CACHE_HH__ 532381SN/A#define __MEM_CACHE_CACHE_HH__ 549291SN/A 552381SN/A#include <cstdint> 569235SN/A#include <unordered_set> 576215SN/A 582381SN/A#include "base/types.hh" 5910405Sandreas.hansson@arm.com#include "mem/cache/base.hh" 609712SN/A#include "mem/packet.hh" 612381SN/A 629036SN/Aclass CacheBlk; 6310405Sandreas.hansson@arm.comstruct CacheParams; 6410405Sandreas.hansson@arm.comclass MSHR; 6510405Sandreas.hansson@arm.com 6610405Sandreas.hansson@arm.com/** 679036SN/A * A coherent cache that can be arranged in flexible topologies. 6810405Sandreas.hansson@arm.com */ 699036SN/Aclass Cache : public BaseCache 709036SN/A{ 7110405Sandreas.hansson@arm.com protected: 722381SN/A /** 739031SN/A * This cache should allocate a block on a line-sized write miss. 749036SN/A */ 752381SN/A const bool doFastWrites; 769091SN/A 7710405Sandreas.hansson@arm.com /** 7810405Sandreas.hansson@arm.com * Store the outstanding requests that we are expecting snoop 7910405Sandreas.hansson@arm.com * responses from so we can determine which snoop responses we 8010405Sandreas.hansson@arm.com * generated and which ones were merely forwarded. 8110405Sandreas.hansson@arm.com */ 8210405Sandreas.hansson@arm.com std::unordered_set<RequestPtr> outstandingSnoop; 839093SN/A 849093SN/A protected: 8510405Sandreas.hansson@arm.com /** 8610405Sandreas.hansson@arm.com * Turn line-sized writes into WriteInvalidate transactions. 8710405Sandreas.hansson@arm.com */ 8810405Sandreas.hansson@arm.com void promoteWholeLineWrites(PacketPtr pkt); 899091SN/A 909715SN/A bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 919342SN/A PacketList &writebacks) override; 929092SN/A 939091SN/A void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, 949092SN/A Tick request_time) override; 959092SN/A 969092SN/A void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, 9710405Sandreas.hansson@arm.com Tick forward_time, 9810405Sandreas.hansson@arm.com Tick request_time) override; 999092SN/A 1009715SN/A void recvTimingReq(PacketPtr pkt) override; 10110405Sandreas.hansson@arm.com 1029092SN/A void doWritebacks(PacketList& writebacks, Tick forward_time) override; 1039092SN/A 10410405Sandreas.hansson@arm.com void doWritebacksAtomic(PacketList& writebacks) override; 1059092SN/A 1069092SN/A void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk, 10710405Sandreas.hansson@arm.com PacketList& writebacks) override; 1089092SN/A 1099092SN/A void recvTimingSnoopReq(PacketPtr pkt) override; 1109092SN/A 1119092SN/A void recvTimingSnoopResp(PacketPtr pkt) override; 1129092SN/A 1139092SN/A Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, 1149092SN/A PacketList &writebacks) override; 1159342SN/A 1169092SN/A Tick recvAtomic(PacketPtr pkt) override; 1179092SN/A 11810405Sandreas.hansson@arm.com Tick recvAtomicSnoop(PacketPtr pkt) override; 1199092SN/A 12010405Sandreas.hansson@arm.com void satisfyRequest(PacketPtr pkt, CacheBlk *blk, 1219092SN/A bool deferred_response = false, 1229092SN/A bool pending_downgrade = false) override; 1239092SN/A 12410405Sandreas.hansson@arm.com void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 1259092SN/A bool already_copied, bool pending_inval); 1269612SN/A 1279714SN/A /** 1289092SN/A * Perform an upward snoop if needed, and update the block state 1299612SN/A * (possibly invalidating the block). Also create a response if required. 1309092SN/A * 13110405Sandreas.hansson@arm.com * @param pkt Snoop packet 1329092SN/A * @param blk Cache block being snooped 1339715SN/A * @param is_timing Timing or atomic for the response 1349092SN/A * @param is_deferred Is this a deferred snoop or not? 1359092SN/A * @param pending_inval Do we have a pending invalidation? 1369092SN/A * 1379092SN/A * @return The snoop delay incurred by the upwards snoop 13810405Sandreas.hansson@arm.com */ 1399092SN/A uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk, 1409092SN/A bool is_timing, bool is_deferred, bool pending_inval); 1419092SN/A 1429092SN/A M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override; 1439092SN/A 1449092SN/A /** 1459092SN/A * Create a CleanEvict request for the given block. 1469092SN/A * 14710405Sandreas.hansson@arm.com * @param blk The block to evict. 1489092SN/A * @return The CleanEvict request for the block. 1499092SN/A */ 1509612SN/A PacketPtr cleanEvictBlk(CacheBlk *blk); 1519092SN/A 1529092SN/A PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 1539715SN/A bool needs_writable, 1549092SN/A bool is_whole_line_write) const override; 15510405Sandreas.hansson@arm.com 1569092SN/A /** 1579092SN/A * Send up a snoop request and find cached copies. If cached copies are 1589092SN/A * found, set the BLOCK_CACHED flag in pkt. 1599612SN/A */ 1609092SN/A bool isCachedAbove(PacketPtr pkt, bool is_timing = true); 1619092SN/A 1629092SN/A public: 1639092SN/A /** Instantiates a basic cache object. */ 1649092SN/A Cache(const CacheParams *p); 1659612SN/A 1669092SN/A /** 1679092SN/A * Take an MSHR, turn it into a suitable downstream packet, and 1689092SN/A * send it out. This construct allows a queue entry to choose a suitable 1699715SN/A * approach based on its type. 1709092SN/A * 1719712SN/A * @param mshr The MSHR to turn into a packet and send 1729712SN/A * @return True if the port is waiting for a retry 1739712SN/A */ 1749712SN/A bool sendMSHRQueuePacket(MSHR* mshr) override; 1759712SN/A}; 1769092SN/A 1779092SN/A#endif // __MEM_CACHE_CACHE_HH__ 1789715SN/A