cache.hh revision 11190:0964165d1857
1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Dave Greene 42 * Steve Reinhardt 43 * Ron Dreslinski 44 * Andreas Hansson 45 */ 46 47/** 48 * @file 49 * Describes a cache based on template policies. 50 */ 51 52#ifndef __MEM_CACHE_CACHE_HH__ 53#define __MEM_CACHE_CACHE_HH__ 54 55#include "base/misc.hh" // fatal, panic, and warn 56#include "mem/cache/base.hh" 57#include "mem/cache/blk.hh" 58#include "mem/cache/mshr.hh" 59#include "mem/cache/tags/base.hh" 60#include "params/Cache.hh" 61#include "sim/eventq.hh" 62 63//Forward decleration 64class BasePrefetcher; 65 66/** 67 * A template-policy based cache. The behavior of the cache can be altered by 68 * supplying different template policies. TagStore handles all tag and data 69 * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" 70 */ 71class Cache : public BaseCache 72{ 73 public: 74 75 /** A typedef for a list of CacheBlk pointers. */ 76 typedef std::list<CacheBlk*> BlkList; 77 78 protected: 79 80 /** 81 * The CPU-side port extends the base cache slave port with access 82 * functions for functional, atomic and timing requests. 83 */ 84 class CpuSidePort : public CacheSlavePort 85 { 86 private: 87 88 // a pointer to our specific cache implementation 89 Cache *cache; 90 91 protected: 92 93 virtual bool recvTimingSnoopResp(PacketPtr pkt); 94 95 virtual bool recvTimingReq(PacketPtr pkt); 96 97 virtual Tick recvAtomic(PacketPtr pkt); 98 99 virtual void recvFunctional(PacketPtr pkt); 100 101 virtual AddrRangeList getAddrRanges() const; 102 103 public: 104 105 CpuSidePort(const std::string &_name, Cache *_cache, 106 const std::string &_label); 107 108 }; 109 110 /** 111 * Override the default behaviour of sendDeferredPacket to enable 112 * the memory-side cache port to also send requests based on the 113 * current MSHR status. This queue has a pointer to our specific 114 * cache implementation and is used by the MemSidePort. 115 */ 116 class CacheReqPacketQueue : public ReqPacketQueue 117 { 118 119 protected: 120 121 Cache &cache; 122 SnoopRespPacketQueue &snoopRespQueue; 123 124 public: 125 126 CacheReqPacketQueue(Cache &cache, MasterPort &port, 127 SnoopRespPacketQueue &snoop_resp_queue, 128 const std::string &label) : 129 ReqPacketQueue(cache, port, label), cache(cache), 130 snoopRespQueue(snoop_resp_queue) { } 131 132 /** 133 * Override the normal sendDeferredPacket and do not only 134 * consider the transmit list (used for responses), but also 135 * requests. 136 */ 137 virtual void sendDeferredPacket(); 138 139 }; 140 141 /** 142 * The memory-side port extends the base cache master port with 143 * access functions for functional, atomic and timing snoops. 144 */ 145 class MemSidePort : public CacheMasterPort 146 { 147 private: 148 149 /** The cache-specific queue. */ 150 CacheReqPacketQueue _reqQueue; 151 152 SnoopRespPacketQueue _snoopRespQueue; 153 154 // a pointer to our specific cache implementation 155 Cache *cache; 156 157 protected: 158 159 virtual void recvTimingSnoopReq(PacketPtr pkt); 160 161 virtual bool recvTimingResp(PacketPtr pkt); 162 163 virtual Tick recvAtomicSnoop(PacketPtr pkt); 164 165 virtual void recvFunctionalSnoop(PacketPtr pkt); 166 167 public: 168 169 MemSidePort(const std::string &_name, Cache *_cache, 170 const std::string &_label); 171 }; 172 173 /** Tag and data Storage */ 174 BaseTags *tags; 175 176 /** Prefetcher */ 177 BasePrefetcher *prefetcher; 178 179 /** Temporary cache block for occasional transitory use */ 180 CacheBlk *tempBlock; 181 182 /** 183 * This cache should allocate a block on a line-sized write miss. 184 */ 185 const bool doFastWrites; 186 187 /** 188 * Turn line-sized writes into WriteInvalidate transactions. 189 */ 190 void promoteWholeLineWrites(PacketPtr pkt); 191 192 /** 193 * Notify the prefetcher on every access, not just misses. 194 */ 195 const bool prefetchOnAccess; 196 197 /** 198 * Upstream caches need this packet until true is returned, so 199 * hold it for deletion until a subsequent call 200 */ 201 std::unique_ptr<Packet> pendingDelete; 202 203 /** 204 * Does all the processing necessary to perform the provided request. 205 * @param pkt The memory request to perform. 206 * @param blk The cache block to be updated. 207 * @param lat The latency of the access. 208 * @param writebacks List for any writebacks that need to be performed. 209 * @return Boolean indicating whether the request was satisfied. 210 */ 211 bool access(PacketPtr pkt, CacheBlk *&blk, 212 Cycles &lat, PacketList &writebacks); 213 214 /** 215 *Handle doing the Compare and Swap function for SPARC. 216 */ 217 void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); 218 219 /** 220 * Find a block frame for new block at address addr targeting the 221 * given security space, assuming that the block is not currently 222 * in the cache. Append writebacks if any to provided packet 223 * list. Return free block frame. May return NULL if there are 224 * no replaceable blocks at the moment. 225 */ 226 CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); 227 228 /** 229 * Populates a cache block and handles all outstanding requests for the 230 * satisfied fill request. This version takes two memory requests. One 231 * contains the fill data, the other is an optional target to satisfy. 232 * @param pkt The memory request with the fill data. 233 * @param blk The cache block if it already exists. 234 * @param writebacks List for any writebacks that need to be performed. 235 * @return Pointer to the new cache block. 236 */ 237 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, 238 PacketList &writebacks); 239 240 241 /** 242 * Performs the access specified by the request. 243 * @param pkt The request to perform. 244 * @return The result of the access. 245 */ 246 bool recvTimingReq(PacketPtr pkt); 247 248 /** 249 * Insert writebacks into the write buffer 250 */ 251 void doWritebacks(PacketList& writebacks, Tick forward_time); 252 253 /** 254 * Send writebacks down the memory hierarchy in atomic mode 255 */ 256 void doWritebacksAtomic(PacketList& writebacks); 257 258 /** 259 * Handles a response (cache line fill/write ack) from the bus. 260 * @param pkt The response packet 261 */ 262 void recvTimingResp(PacketPtr pkt); 263 264 /** 265 * Snoops bus transactions to maintain coherence. 266 * @param pkt The current bus transaction. 267 */ 268 void recvTimingSnoopReq(PacketPtr pkt); 269 270 /** 271 * Handle a snoop response. 272 * @param pkt Snoop response packet 273 */ 274 void recvTimingSnoopResp(PacketPtr pkt); 275 276 /** 277 * Performs the access specified by the request. 278 * @param pkt The request to perform. 279 * @return The number of ticks required for the access. 280 */ 281 Tick recvAtomic(PacketPtr pkt); 282 283 /** 284 * Snoop for the provided request in the cache and return the estimated 285 * time taken. 286 * @param pkt The memory request to snoop 287 * @return The number of ticks required for the snoop. 288 */ 289 Tick recvAtomicSnoop(PacketPtr pkt); 290 291 /** 292 * Performs the access specified by the request. 293 * @param pkt The request to perform. 294 * @param fromCpuSide from the CPU side port or the memory side port 295 */ 296 void functionalAccess(PacketPtr pkt, bool fromCpuSide); 297 298 void satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, 299 bool deferred_response = false, 300 bool pending_downgrade = false); 301 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, CacheBlk *blk); 302 303 void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 304 bool already_copied, bool pending_inval); 305 306 /** 307 * Perform an upward snoop if needed, and update the block state 308 * (possibly invalidating the block). Also create a response if required. 309 * 310 * @param pkt Snoop packet 311 * @param blk Cache block being snooped 312 * @param is_timing Timing or atomic for the response 313 * @param is_deferred Is this a deferred snoop or not? 314 * @param pending_inval Do we have a pending invalidation? 315 * 316 * @return The snoop delay incurred by the upwards snoop 317 */ 318 uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk, 319 bool is_timing, bool is_deferred, bool pending_inval); 320 321 /** 322 * Create a writeback request for the given block. 323 * @param blk The block to writeback. 324 * @return The writeback request for the block. 325 */ 326 PacketPtr writebackBlk(CacheBlk *blk); 327 328 /** 329 * Create a CleanEvict request for the given block. 330 * @param blk The block to evict. 331 * @return The CleanEvict request for the block. 332 */ 333 PacketPtr cleanEvictBlk(CacheBlk *blk); 334 335 336 void memWriteback() override; 337 void memInvalidate() override; 338 bool isDirty() const override; 339 340 /** 341 * Cache block visitor that writes back dirty cache blocks using 342 * functional writes. 343 * 344 * \return Always returns true. 345 */ 346 bool writebackVisitor(CacheBlk &blk); 347 /** 348 * Cache block visitor that invalidates all blocks in the cache. 349 * 350 * @warn Dirty cache lines will not be written back to memory. 351 * 352 * \return Always returns true. 353 */ 354 bool invalidateVisitor(CacheBlk &blk); 355 356 /** 357 * Generate an appropriate downstream bus request packet for the 358 * given parameters. 359 * @param cpu_pkt The upstream request that needs to be satisfied. 360 * @param blk The block currently in the cache corresponding to 361 * cpu_pkt (NULL if none). 362 * @param needsExclusive Indicates that an exclusive copy is required 363 * even if the request in cpu_pkt doesn't indicate that. 364 * @return A new Packet containing the request, or NULL if the 365 * current request in cpu_pkt should just be forwarded on. 366 */ 367 PacketPtr getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, 368 bool needsExclusive) const; 369 370 /** 371 * Return the next MSHR to service, either a pending miss from the 372 * mshrQueue, a buffered write from the write buffer, or something 373 * from the prefetcher. This function is responsible for 374 * prioritizing among those sources on the fly. 375 */ 376 MSHR *getNextMSHR(); 377 378 /** 379 * Send up a snoop request and find cached copies. If cached copies are 380 * found, set the BLOCK_CACHED flag in pkt. 381 */ 382 bool isCachedAbove(PacketPtr pkt, bool is_timing = true) const; 383 384 /** 385 * Selects an outstanding request to service. Called when the 386 * cache gets granted the downstream bus in timing mode. 387 * @return The request to service, NULL if none found. 388 */ 389 PacketPtr getTimingPacket(); 390 391 /** 392 * Marks a request as in service (sent on the bus). This can have 393 * side effect since storage for no response commands is 394 * deallocated once they are successfully sent. Also remember if 395 * we are expecting a dirty response from another cache, 396 * effectively making this MSHR the ordering point. 397 */ 398 void markInService(MSHR *mshr, bool pending_dirty_resp); 399 400 /** 401 * Return whether there are any outstanding misses. 402 */ 403 bool outstandingMisses() const 404 { 405 return mshrQueue.allocated != 0; 406 } 407 408 CacheBlk *findBlock(Addr addr, bool is_secure) const { 409 return tags->findBlock(addr, is_secure); 410 } 411 412 bool inCache(Addr addr, bool is_secure) const override { 413 return (tags->findBlock(addr, is_secure) != 0); 414 } 415 416 bool inMissQueue(Addr addr, bool is_secure) const override { 417 return (mshrQueue.findMatch(addr, is_secure) != 0); 418 } 419 420 /** 421 * Find next request ready time from among possible sources. 422 */ 423 Tick nextMSHRReadyTime() const; 424 425 public: 426 /** Instantiates a basic cache object. */ 427 Cache(const CacheParams *p); 428 429 /** Non-default destructor is needed to deallocate memory. */ 430 virtual ~Cache(); 431 432 void regStats() override; 433 434 /** serialize the state of the caches 435 * We currently don't support checkpointing cache state, so this panics. 436 */ 437 void serialize(CheckpointOut &cp) const override; 438 void unserialize(CheckpointIn &cp) override; 439}; 440 441/** 442 * Wrap a method and present it as a cache block visitor. 443 * 444 * For example the forEachBlk method in the tag arrays expects a 445 * callable object/function as their parameter. This class wraps a 446 * method in an object and presents callable object that adheres to 447 * the cache block visitor protocol. 448 */ 449class CacheBlkVisitorWrapper : public CacheBlkVisitor 450{ 451 public: 452 typedef bool (Cache::*VisitorPtr)(CacheBlk &blk); 453 454 CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor) 455 : cache(_cache), visitor(_visitor) {} 456 457 bool operator()(CacheBlk &blk) override { 458 return (cache.*visitor)(blk); 459 } 460 461 private: 462 Cache &cache; 463 VisitorPtr visitor; 464}; 465 466/** 467 * Cache block visitor that determines if there are dirty blocks in a 468 * cache. 469 * 470 * Use with the forEachBlk method in the tag array to determine if the 471 * array contains dirty blocks. 472 */ 473class CacheBlkIsDirtyVisitor : public CacheBlkVisitor 474{ 475 public: 476 CacheBlkIsDirtyVisitor() 477 : _isDirty(false) {} 478 479 bool operator()(CacheBlk &blk) override { 480 if (blk.isDirty()) { 481 _isDirty = true; 482 return false; 483 } else { 484 return true; 485 } 486 } 487 488 /** 489 * Does the array contain a dirty line? 490 * 491 * \return true if yes, false otherwise. 492 */ 493 bool isDirty() const { return _isDirty; }; 494 495 private: 496 bool _isDirty; 497}; 498 499#endif // __MEM_CACHE_CACHE_HH__ 500