cache.hh revision 11054:00bddca96da6
1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Dave Greene 42 * Steve Reinhardt 43 * Ron Dreslinski 44 * Andreas Hansson 45 */ 46 47/** 48 * @file 49 * Describes a cache based on template policies. 50 */ 51 52#ifndef __MEM_CACHE_CACHE_HH__ 53#define __MEM_CACHE_CACHE_HH__ 54 55#include "base/misc.hh" // fatal, panic, and warn 56#include "mem/cache/base.hh" 57#include "mem/cache/blk.hh" 58#include "mem/cache/mshr.hh" 59#include "mem/cache/tags/base.hh" 60#include "params/Cache.hh" 61#include "sim/eventq.hh" 62 63//Forward decleration 64class BasePrefetcher; 65 66/** 67 * A template-policy based cache. The behavior of the cache can be altered by 68 * supplying different template policies. TagStore handles all tag and data 69 * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" 70 */ 71class Cache : public BaseCache 72{ 73 public: 74 75 /** A typedef for a list of CacheBlk pointers. */ 76 typedef std::list<CacheBlk*> BlkList; 77 78 protected: 79 80 /** 81 * The CPU-side port extends the base cache slave port with access 82 * functions for functional, atomic and timing requests. 83 */ 84 class CpuSidePort : public CacheSlavePort 85 { 86 private: 87 88 // a pointer to our specific cache implementation 89 Cache *cache; 90 91 protected: 92 93 virtual bool recvTimingSnoopResp(PacketPtr pkt); 94 95 virtual bool recvTimingReq(PacketPtr pkt); 96 97 virtual Tick recvAtomic(PacketPtr pkt); 98 99 virtual void recvFunctional(PacketPtr pkt); 100 101 virtual AddrRangeList getAddrRanges() const; 102 103 public: 104 105 CpuSidePort(const std::string &_name, Cache *_cache, 106 const std::string &_label); 107 108 }; 109 110 /** 111 * Override the default behaviour of sendDeferredPacket to enable 112 * the memory-side cache port to also send requests based on the 113 * current MSHR status. This queue has a pointer to our specific 114 * cache implementation and is used by the MemSidePort. 115 */ 116 class CacheReqPacketQueue : public ReqPacketQueue 117 { 118 119 protected: 120 121 Cache &cache; 122 SnoopRespPacketQueue &snoopRespQueue; 123 124 public: 125 126 CacheReqPacketQueue(Cache &cache, MasterPort &port, 127 SnoopRespPacketQueue &snoop_resp_queue, 128 const std::string &label) : 129 ReqPacketQueue(cache, port, label), cache(cache), 130 snoopRespQueue(snoop_resp_queue) { } 131 132 /** 133 * Override the normal sendDeferredPacket and do not only 134 * consider the transmit list (used for responses), but also 135 * requests. 136 */ 137 virtual void sendDeferredPacket(); 138 139 }; 140 141 /** 142 * The memory-side port extends the base cache master port with 143 * access functions for functional, atomic and timing snoops. 144 */ 145 class MemSidePort : public CacheMasterPort 146 { 147 private: 148 149 /** The cache-specific queue. */ 150 CacheReqPacketQueue _reqQueue; 151 152 SnoopRespPacketQueue _snoopRespQueue; 153 154 // a pointer to our specific cache implementation 155 Cache *cache; 156 157 protected: 158 159 virtual void recvTimingSnoopReq(PacketPtr pkt); 160 161 virtual bool recvTimingResp(PacketPtr pkt); 162 163 virtual Tick recvAtomicSnoop(PacketPtr pkt); 164 165 virtual void recvFunctionalSnoop(PacketPtr pkt); 166 167 public: 168 169 MemSidePort(const std::string &_name, Cache *_cache, 170 const std::string &_label); 171 }; 172 173 /** Tag and data Storage */ 174 BaseTags *tags; 175 176 /** Prefetcher */ 177 BasePrefetcher *prefetcher; 178 179 /** Temporary cache block for occasional transitory use */ 180 CacheBlk *tempBlock; 181 182 /** 183 * This cache should allocate a block on a line-sized write miss. 184 */ 185 const bool doFastWrites; 186 187 /** 188 * Turn line-sized writes into WriteInvalidate transactions. 189 */ 190 void promoteWholeLineWrites(PacketPtr pkt); 191 192 /** 193 * Notify the prefetcher on every access, not just misses. 194 */ 195 const bool prefetchOnAccess; 196 197 /** 198 * @todo this is a temporary workaround until the 4-phase code is committed. 199 * upstream caches need this packet until true is returned, so hold it for 200 * deletion until a subsequent call 201 */ 202 std::vector<PacketPtr> pendingDelete; 203 204 /** 205 * Does all the processing necessary to perform the provided request. 206 * @param pkt The memory request to perform. 207 * @param blk The cache block to be updated. 208 * @param lat The latency of the access. 209 * @param writebacks List for any writebacks that need to be performed. 210 * @return Boolean indicating whether the request was satisfied. 211 */ 212 bool access(PacketPtr pkt, CacheBlk *&blk, 213 Cycles &lat, PacketList &writebacks); 214 215 /** 216 *Handle doing the Compare and Swap function for SPARC. 217 */ 218 void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); 219 220 /** 221 * Find a block frame for new block at address addr targeting the 222 * given security space, assuming that the block is not currently 223 * in the cache. Append writebacks if any to provided packet 224 * list. Return free block frame. May return NULL if there are 225 * no replaceable blocks at the moment. 226 */ 227 CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); 228 229 /** 230 * Populates a cache block and handles all outstanding requests for the 231 * satisfied fill request. This version takes two memory requests. One 232 * contains the fill data, the other is an optional target to satisfy. 233 * @param pkt The memory request with the fill data. 234 * @param blk The cache block if it already exists. 235 * @param writebacks List for any writebacks that need to be performed. 236 * @return Pointer to the new cache block. 237 */ 238 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, 239 PacketList &writebacks); 240 241 242 /** 243 * Performs the access specified by the request. 244 * @param pkt The request to perform. 245 * @return The result of the access. 246 */ 247 bool recvTimingReq(PacketPtr pkt); 248 249 /** 250 * Insert writebacks into the write buffer 251 */ 252 void doWritebacks(PacketList& writebacks, Tick forward_time); 253 254 /** 255 * Handles a response (cache line fill/write ack) from the bus. 256 * @param pkt The response packet 257 */ 258 void recvTimingResp(PacketPtr pkt); 259 260 /** 261 * Snoops bus transactions to maintain coherence. 262 * @param pkt The current bus transaction. 263 */ 264 void recvTimingSnoopReq(PacketPtr pkt); 265 266 /** 267 * Handle a snoop response. 268 * @param pkt Snoop response packet 269 */ 270 void recvTimingSnoopResp(PacketPtr pkt); 271 272 /** 273 * Performs the access specified by the request. 274 * @param pkt The request to perform. 275 * @return The number of ticks required for the access. 276 */ 277 Tick recvAtomic(PacketPtr pkt); 278 279 /** 280 * Snoop for the provided request in the cache and return the estimated 281 * time taken. 282 * @param pkt The memory request to snoop 283 * @return The number of ticks required for the snoop. 284 */ 285 Tick recvAtomicSnoop(PacketPtr pkt); 286 287 /** 288 * Performs the access specified by the request. 289 * @param pkt The request to perform. 290 * @param fromCpuSide from the CPU side port or the memory side port 291 */ 292 void functionalAccess(PacketPtr pkt, bool fromCpuSide); 293 294 void satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, 295 bool deferred_response = false, 296 bool pending_downgrade = false); 297 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, CacheBlk *blk); 298 299 void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 300 bool already_copied, bool pending_inval); 301 302 /** 303 * Sets the blk to the new state. 304 * @param blk The cache block being snooped. 305 * @param new_state The new coherence state for the block. 306 */ 307 void handleSnoop(PacketPtr ptk, CacheBlk *blk, 308 bool is_timing, bool is_deferred, bool pending_inval); 309 310 /** 311 * Create a writeback request for the given block. 312 * @param blk The block to writeback. 313 * @return The writeback request for the block. 314 */ 315 PacketPtr writebackBlk(CacheBlk *blk); 316 317 /** 318 * Create a CleanEvict request for the given block. 319 * @param blk The block to evict. 320 * @return The CleanEvict request for the block. 321 */ 322 PacketPtr cleanEvictBlk(CacheBlk *blk); 323 324 325 void memWriteback(); 326 void memInvalidate(); 327 bool isDirty() const; 328 329 /** 330 * Cache block visitor that writes back dirty cache blocks using 331 * functional writes. 332 * 333 * \return Always returns true. 334 */ 335 bool writebackVisitor(CacheBlk &blk); 336 /** 337 * Cache block visitor that invalidates all blocks in the cache. 338 * 339 * @warn Dirty cache lines will not be written back to memory. 340 * 341 * \return Always returns true. 342 */ 343 bool invalidateVisitor(CacheBlk &blk); 344 345 /** 346 * Generate an appropriate downstream bus request packet for the 347 * given parameters. 348 * @param cpu_pkt The upstream request that needs to be satisfied. 349 * @param blk The block currently in the cache corresponding to 350 * cpu_pkt (NULL if none). 351 * @param needsExclusive Indicates that an exclusive copy is required 352 * even if the request in cpu_pkt doesn't indicate that. 353 * @return A new Packet containing the request, or NULL if the 354 * current request in cpu_pkt should just be forwarded on. 355 */ 356 PacketPtr getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, 357 bool needsExclusive) const; 358 359 /** 360 * Return the next MSHR to service, either a pending miss from the 361 * mshrQueue, a buffered write from the write buffer, or something 362 * from the prefetcher. This function is responsible for 363 * prioritizing among those sources on the fly. 364 */ 365 MSHR *getNextMSHR(); 366 367 /** 368 * Send up a snoop request and find cached copies. If cached copies are 369 * found, set the BLOCK_CACHED flag in pkt. 370 */ 371 bool isCachedAbove(const PacketPtr pkt) const; 372 373 /** 374 * Selects an outstanding request to service. Called when the 375 * cache gets granted the downstream bus in timing mode. 376 * @return The request to service, NULL if none found. 377 */ 378 PacketPtr getTimingPacket(); 379 380 /** 381 * Marks a request as in service (sent on the bus). This can have 382 * side effect since storage for no response commands is 383 * deallocated once they are successfully sent. Also remember if 384 * we are expecting a dirty response from another cache, 385 * effectively making this MSHR the ordering point. 386 */ 387 void markInService(MSHR *mshr, bool pending_dirty_resp); 388 389 /** 390 * Return whether there are any outstanding misses. 391 */ 392 bool outstandingMisses() const 393 { 394 return mshrQueue.allocated != 0; 395 } 396 397 CacheBlk *findBlock(Addr addr, bool is_secure) const { 398 return tags->findBlock(addr, is_secure); 399 } 400 401 bool inCache(Addr addr, bool is_secure) const { 402 return (tags->findBlock(addr, is_secure) != 0); 403 } 404 405 bool inMissQueue(Addr addr, bool is_secure) const { 406 return (mshrQueue.findMatch(addr, is_secure) != 0); 407 } 408 409 /** 410 * Find next request ready time from among possible sources. 411 */ 412 Tick nextMSHRReadyTime() const; 413 414 public: 415 /** Instantiates a basic cache object. */ 416 Cache(const CacheParams *p); 417 418 /** Non-default destructor is needed to deallocate memory. */ 419 virtual ~Cache(); 420 421 void regStats(); 422 423 /** serialize the state of the caches 424 * We currently don't support checkpointing cache state, so this panics. 425 */ 426 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 427 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 428}; 429 430/** 431 * Wrap a method and present it as a cache block visitor. 432 * 433 * For example the forEachBlk method in the tag arrays expects a 434 * callable object/function as their parameter. This class wraps a 435 * method in an object and presents callable object that adheres to 436 * the cache block visitor protocol. 437 */ 438class CacheBlkVisitorWrapper : public CacheBlkVisitor 439{ 440 public: 441 typedef bool (Cache::*VisitorPtr)(CacheBlk &blk); 442 443 CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor) 444 : cache(_cache), visitor(_visitor) {} 445 446 bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE { 447 return (cache.*visitor)(blk); 448 } 449 450 private: 451 Cache &cache; 452 VisitorPtr visitor; 453}; 454 455/** 456 * Cache block visitor that determines if there are dirty blocks in a 457 * cache. 458 * 459 * Use with the forEachBlk method in the tag array to determine if the 460 * array contains dirty blocks. 461 */ 462class CacheBlkIsDirtyVisitor : public CacheBlkVisitor 463{ 464 public: 465 CacheBlkIsDirtyVisitor() 466 : _isDirty(false) {} 467 468 bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE { 469 if (blk.isDirty()) { 470 _isDirty = true; 471 return false; 472 } else { 473 return true; 474 } 475 } 476 477 /** 478 * Does the array contain a dirty line? 479 * 480 * \return true if yes, false otherwise. 481 */ 482 bool isDirty() const { return _isDirty; }; 483 484 private: 485 bool _isDirty; 486}; 487 488#endif // __MEM_CACHE_CACHE_HH__ 489