cache.hh revision 10343
1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Dave Greene 42 * Steve Reinhardt 43 * Ron Dreslinski 44 * Andreas Hansson 45 */ 46 47/** 48 * @file 49 * Describes a cache based on template policies. 50 */ 51 52#ifndef __CACHE_HH__ 53#define __CACHE_HH__ 54 55#include "base/misc.hh" // fatal, panic, and warn 56#include "mem/cache/base.hh" 57#include "mem/cache/blk.hh" 58#include "mem/cache/mshr.hh" 59#include "sim/eventq.hh" 60 61//Forward decleration 62class BasePrefetcher; 63 64/** 65 * A template-policy based cache. The behavior of the cache can be altered by 66 * supplying different template policies. TagStore handles all tag and data 67 * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" 68 */ 69template <class TagStore> 70class Cache : public BaseCache 71{ 72 public: 73 /** Define the type of cache block to use. */ 74 typedef typename TagStore::BlkType BlkType; 75 /** A typedef for a list of BlkType pointers. */ 76 typedef typename TagStore::BlkList BlkList; 77 78 protected: 79 typedef CacheBlkVisitorWrapper<Cache<TagStore>, BlkType> WrappedBlkVisitor; 80 81 /** 82 * The CPU-side port extends the base cache slave port with access 83 * functions for functional, atomic and timing requests. 84 */ 85 class CpuSidePort : public CacheSlavePort 86 { 87 private: 88 89 // a pointer to our specific cache implementation 90 Cache<TagStore> *cache; 91 92 protected: 93 94 virtual bool recvTimingSnoopResp(PacketPtr pkt); 95 96 virtual bool recvTimingReq(PacketPtr pkt); 97 98 virtual Tick recvAtomic(PacketPtr pkt); 99 100 virtual void recvFunctional(PacketPtr pkt); 101 102 virtual AddrRangeList getAddrRanges() const; 103 104 public: 105 106 CpuSidePort(const std::string &_name, Cache<TagStore> *_cache, 107 const std::string &_label); 108 109 }; 110 111 /** 112 * Override the default behaviour of sendDeferredPacket to enable 113 * the memory-side cache port to also send requests based on the 114 * current MSHR status. This queue has a pointer to our specific 115 * cache implementation and is used by the MemSidePort. 116 */ 117 class MemSidePacketQueue : public MasterPacketQueue 118 { 119 120 protected: 121 122 Cache<TagStore> &cache; 123 124 public: 125 126 MemSidePacketQueue(Cache<TagStore> &cache, MasterPort &port, 127 const std::string &label) : 128 MasterPacketQueue(cache, port, label), cache(cache) { } 129 130 /** 131 * Override the normal sendDeferredPacket and do not only 132 * consider the transmit list (used for responses), but also 133 * requests. 134 */ 135 virtual void sendDeferredPacket(); 136 137 }; 138 139 /** 140 * The memory-side port extends the base cache master port with 141 * access functions for functional, atomic and timing snoops. 142 */ 143 class MemSidePort : public CacheMasterPort 144 { 145 private: 146 147 /** The cache-specific queue. */ 148 MemSidePacketQueue _queue; 149 150 // a pointer to our specific cache implementation 151 Cache<TagStore> *cache; 152 153 protected: 154 155 virtual void recvTimingSnoopReq(PacketPtr pkt); 156 157 virtual bool recvTimingResp(PacketPtr pkt); 158 159 virtual Tick recvAtomicSnoop(PacketPtr pkt); 160 161 virtual void recvFunctionalSnoop(PacketPtr pkt); 162 163 public: 164 165 MemSidePort(const std::string &_name, Cache<TagStore> *_cache, 166 const std::string &_label); 167 }; 168 169 /** Tag and data Storage */ 170 TagStore *tags; 171 172 /** Prefetcher */ 173 BasePrefetcher *prefetcher; 174 175 /** Temporary cache block for occasional transitory use */ 176 BlkType *tempBlock; 177 178 /** 179 * This cache should allocate a block on a line-sized write miss. 180 */ 181 const bool doFastWrites; 182 183 /** 184 * Notify the prefetcher on every access, not just misses. 185 */ 186 const bool prefetchOnAccess; 187 188 /** 189 * @todo this is a temporary workaround until the 4-phase code is committed. 190 * upstream caches need this packet until true is returned, so hold it for 191 * deletion until a subsequent call 192 */ 193 std::vector<PacketPtr> pendingDelete; 194 195 /** 196 * Does all the processing necessary to perform the provided request. 197 * @param pkt The memory request to perform. 198 * @param blk The cache block to be updated. 199 * @param lat The latency of the access. 200 * @param writebacks List for any writebacks that need to be performed. 201 * @return Boolean indicating whether the request was satisfied. 202 */ 203 bool access(PacketPtr pkt, BlkType *&blk, 204 Cycles &lat, PacketList &writebacks); 205 206 /** 207 *Handle doing the Compare and Swap function for SPARC. 208 */ 209 void cmpAndSwap(BlkType *blk, PacketPtr pkt); 210 211 /** 212 * Find a block frame for new block at address addr targeting the 213 * given security space, assuming that the block is not currently 214 * in the cache. Append writebacks if any to provided packet 215 * list. Return free block frame. May return NULL if there are 216 * no replaceable blocks at the moment. 217 */ 218 BlkType *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); 219 220 /** 221 * Populates a cache block and handles all outstanding requests for the 222 * satisfied fill request. This version takes two memory requests. One 223 * contains the fill data, the other is an optional target to satisfy. 224 * @param pkt The memory request with the fill data. 225 * @param blk The cache block if it already exists. 226 * @param writebacks List for any writebacks that need to be performed. 227 * @return Pointer to the new cache block. 228 */ 229 BlkType *handleFill(PacketPtr pkt, BlkType *blk, 230 PacketList &writebacks); 231 232 233 /** 234 * Performs the access specified by the request. 235 * @param pkt The request to perform. 236 * @return The result of the access. 237 */ 238 bool recvTimingReq(PacketPtr pkt); 239 240 /** 241 * Handles a response (cache line fill/write ack) from the bus. 242 * @param pkt The response packet 243 */ 244 void recvTimingResp(PacketPtr pkt); 245 246 /** 247 * Snoops bus transactions to maintain coherence. 248 * @param pkt The current bus transaction. 249 */ 250 void recvTimingSnoopReq(PacketPtr pkt); 251 252 /** 253 * Handle a snoop response. 254 * @param pkt Snoop response packet 255 */ 256 void recvTimingSnoopResp(PacketPtr pkt); 257 258 /** 259 * Performs the access specified by the request. 260 * @param pkt The request to perform. 261 * @return The number of ticks required for the access. 262 */ 263 Tick recvAtomic(PacketPtr pkt); 264 265 /** 266 * Snoop for the provided request in the cache and return the estimated 267 * time taken. 268 * @param pkt The memory request to snoop 269 * @return The number of ticks required for the snoop. 270 */ 271 Tick recvAtomicSnoop(PacketPtr pkt); 272 273 /** 274 * Performs the access specified by the request. 275 * @param pkt The request to perform. 276 * @param fromCpuSide from the CPU side port or the memory side port 277 */ 278 void functionalAccess(PacketPtr pkt, bool fromCpuSide); 279 280 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk, 281 bool deferred_response = false, 282 bool pending_downgrade = false); 283 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); 284 285 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, 286 bool already_copied, bool pending_inval); 287 288 /** 289 * Sets the blk to the new state. 290 * @param blk The cache block being snooped. 291 * @param new_state The new coherence state for the block. 292 */ 293 void handleSnoop(PacketPtr ptk, BlkType *blk, 294 bool is_timing, bool is_deferred, bool pending_inval); 295 296 /** 297 * Create a writeback request for the given block. 298 * @param blk The block to writeback. 299 * @return The writeback request for the block. 300 */ 301 PacketPtr writebackBlk(BlkType *blk); 302 303 304 void memWriteback(); 305 void memInvalidate(); 306 bool isDirty() const; 307 308 /** 309 * Cache block visitor that writes back dirty cache blocks using 310 * functional writes. 311 * 312 * \return Always returns true. 313 */ 314 bool writebackVisitor(BlkType &blk); 315 /** 316 * Cache block visitor that invalidates all blocks in the cache. 317 * 318 * @warn Dirty cache lines will not be written back to memory. 319 * 320 * \return Always returns true. 321 */ 322 bool invalidateVisitor(BlkType &blk); 323 324 /** 325 * Flush a cache line due to an uncacheable memory access to the 326 * line. 327 * 328 * @note This shouldn't normally happen, but we need to handle it 329 * since some architecture models don't implement cache 330 * maintenance operations. We won't even try to get a decent 331 * timing here since the line should have been flushed earlier by 332 * a cache maintenance operation. 333 */ 334 void uncacheableFlush(PacketPtr pkt); 335 336 /** 337 * Squash all requests associated with specified thread. 338 * intended for use by I-cache. 339 * @param threadNum The thread to squash. 340 */ 341 void squash(int threadNum); 342 343 /** 344 * Generate an appropriate downstream bus request packet for the 345 * given parameters. 346 * @param cpu_pkt The upstream request that needs to be satisfied. 347 * @param blk The block currently in the cache corresponding to 348 * cpu_pkt (NULL if none). 349 * @param needsExclusive Indicates that an exclusive copy is required 350 * even if the request in cpu_pkt doesn't indicate that. 351 * @return A new Packet containing the request, or NULL if the 352 * current request in cpu_pkt should just be forwarded on. 353 */ 354 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 355 bool needsExclusive) const; 356 357 /** 358 * Return the next MSHR to service, either a pending miss from the 359 * mshrQueue, a buffered write from the write buffer, or something 360 * from the prefetcher. This function is responsible for 361 * prioritizing among those sources on the fly. 362 */ 363 MSHR *getNextMSHR(); 364 365 /** 366 * Selects an outstanding request to service. Called when the 367 * cache gets granted the downstream bus in timing mode. 368 * @return The request to service, NULL if none found. 369 */ 370 PacketPtr getTimingPacket(); 371 372 /** 373 * Marks a request as in service (sent on the bus). This can have side 374 * effect since storage for no response commands is deallocated once they 375 * are successfully sent. 376 * @param pkt The request that was sent on the bus. 377 */ 378 void markInService(MSHR *mshr, PacketPtr pkt = 0); 379 380 /** 381 * Return whether there are any outstanding misses. 382 */ 383 bool outstandingMisses() const 384 { 385 return mshrQueue.allocated != 0; 386 } 387 388 CacheBlk *findBlock(Addr addr, bool is_secure) const { 389 return tags->findBlock(addr, is_secure); 390 } 391 392 bool inCache(Addr addr, bool is_secure) const { 393 return (tags->findBlock(addr, is_secure) != 0); 394 } 395 396 bool inMissQueue(Addr addr, bool is_secure) const { 397 return (mshrQueue.findMatch(addr, is_secure) != 0); 398 } 399 400 /** 401 * Find next request ready time from among possible sources. 402 */ 403 Tick nextMSHRReadyTime() const; 404 405 public: 406 /** Instantiates a basic cache object. */ 407 Cache(const Params *p); 408 409 /** Non-default destructor is needed to deallocate memory. */ 410 virtual ~Cache(); 411 412 void regStats(); 413 414 /** serialize the state of the caches 415 * We currently don't support checkpointing cache state, so this panics. 416 */ 417 virtual void serialize(std::ostream &os); 418 void unserialize(Checkpoint *cp, const std::string §ion); 419}; 420 421#endif // __CACHE_HH__ 422