cache.hh revision 3135
12810Srdreslin@umich.edu/* 22810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 32810Srdreslin@umich.edu * All rights reserved. 42810Srdreslin@umich.edu * 52810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 62810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 72810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 82810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 92810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 102810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 112810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 122810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 132810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 142810Srdreslin@umich.edu * this software without specific prior written permission. 152810Srdreslin@umich.edu * 162810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * Authors: Erik Hallnor 292810Srdreslin@umich.edu * Dave Greene 302810Srdreslin@umich.edu * Steve Reinhardt 312810Srdreslin@umich.edu */ 322810Srdreslin@umich.edu 332810Srdreslin@umich.edu/** 342810Srdreslin@umich.edu * @file 352810Srdreslin@umich.edu * Describes a cache based on template policies. 362810Srdreslin@umich.edu */ 372810Srdreslin@umich.edu 382810Srdreslin@umich.edu#ifndef __CACHE_HH__ 392810Srdreslin@umich.edu#define __CACHE_HH__ 402810Srdreslin@umich.edu 412810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 422810Srdreslin@umich.edu#include "cpu/smt.hh" // SMT_MAX_THREADS 432810Srdreslin@umich.edu 442810Srdreslin@umich.edu#include "mem/cache/base_cache.hh" 452810Srdreslin@umich.edu#include "mem/cache/prefetch/prefetcher.hh" 462810Srdreslin@umich.edu 472813Srdreslin@umich.edu//Forward decleration 482813Srdreslin@umich.educlass MSHR; 492813Srdreslin@umich.edu 502810Srdreslin@umich.edu 512810Srdreslin@umich.edu/** 522810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 532810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 542810Srdreslin@umich.edu * storage @sa TagStore. Buffering handles all misses and writes/writebacks 552810Srdreslin@umich.edu * @sa MissQueue. Coherence handles all coherence policy details @sa 562810Srdreslin@umich.edu * UniCoherence, SimpleMultiCoherence. 572810Srdreslin@umich.edu */ 582810Srdreslin@umich.edutemplate <class TagStore, class Buffering, class Coherence> 592810Srdreslin@umich.educlass Cache : public BaseCache 602810Srdreslin@umich.edu{ 612810Srdreslin@umich.edu public: 622810Srdreslin@umich.edu /** Define the type of cache block to use. */ 632810Srdreslin@umich.edu typedef typename TagStore::BlkType BlkType; 642810Srdreslin@umich.edu 652810Srdreslin@umich.edu bool prefetchAccess; 662810Srdreslin@umich.edu protected: 672810Srdreslin@umich.edu 682810Srdreslin@umich.edu /** Tag and data Storage */ 692810Srdreslin@umich.edu TagStore *tags; 702810Srdreslin@umich.edu /** Miss and Writeback handler */ 712810Srdreslin@umich.edu Buffering *missQueue; 722810Srdreslin@umich.edu /** Coherence protocol. */ 732810Srdreslin@umich.edu Coherence *coherence; 742810Srdreslin@umich.edu 752810Srdreslin@umich.edu /** Prefetcher */ 762810Srdreslin@umich.edu Prefetcher<TagStore, Buffering> *prefetcher; 772810Srdreslin@umich.edu 782810Srdreslin@umich.edu /** Do fast copies in this cache. */ 792810Srdreslin@umich.edu bool doCopy; 802810Srdreslin@umich.edu 812810Srdreslin@umich.edu /** Block on a delayed copy. */ 822810Srdreslin@umich.edu bool blockOnCopy; 832810Srdreslin@umich.edu 842810Srdreslin@umich.edu /** 852810Srdreslin@umich.edu * The clock ratio of the outgoing bus. 862810Srdreslin@umich.edu * Used for calculating critical word first. 872810Srdreslin@umich.edu */ 882810Srdreslin@umich.edu int busRatio; 892810Srdreslin@umich.edu 902810Srdreslin@umich.edu /** 912810Srdreslin@umich.edu * The bus width in bytes of the outgoing bus. 922810Srdreslin@umich.edu * Used for calculating critical word first. 932810Srdreslin@umich.edu */ 942810Srdreslin@umich.edu int busWidth; 952810Srdreslin@umich.edu 962813Srdreslin@umich.edu /** 972813Srdreslin@umich.edu * The latency of a hit in this device. 982813Srdreslin@umich.edu */ 992813Srdreslin@umich.edu int hitLatency; 1002813Srdreslin@umich.edu 1012810Srdreslin@umich.edu /** 1022810Srdreslin@umich.edu * A permanent mem req to always be used to cause invalidations. 1032810Srdreslin@umich.edu * Used to append to target list, to cause an invalidation. 1042810Srdreslin@umich.edu */ 1052810Srdreslin@umich.edu Packet * invalidatePkt; 1062810Srdreslin@umich.edu 1072810Srdreslin@umich.edu /** 1082810Srdreslin@umich.edu * Temporarily move a block into a MSHR. 1092810Srdreslin@umich.edu * @todo Remove this when LSQ/SB are fixed and implemented in memtest. 1102810Srdreslin@umich.edu */ 1112991Srdreslin@umich.edu void pseudoFill(Addr addr); 1122810Srdreslin@umich.edu 1132810Srdreslin@umich.edu /** 1142810Srdreslin@umich.edu * Temporarily move a block into an existing MSHR. 1152810Srdreslin@umich.edu * @todo Remove this when LSQ/SB are fixed and implemented in memtest. 1162810Srdreslin@umich.edu */ 1172810Srdreslin@umich.edu void pseudoFill(MSHR *mshr); 1182810Srdreslin@umich.edu 1192810Srdreslin@umich.edu public: 1202810Srdreslin@umich.edu 1212810Srdreslin@umich.edu class Params 1222810Srdreslin@umich.edu { 1232810Srdreslin@umich.edu public: 1242810Srdreslin@umich.edu TagStore *tags; 1252810Srdreslin@umich.edu Buffering *missQueue; 1262810Srdreslin@umich.edu Coherence *coherence; 1272810Srdreslin@umich.edu bool doCopy; 1282810Srdreslin@umich.edu bool blockOnCopy; 1292810Srdreslin@umich.edu BaseCache::Params baseParams; 1302810Srdreslin@umich.edu Prefetcher<TagStore, Buffering> *prefetcher; 1312810Srdreslin@umich.edu bool prefetchAccess; 1322813Srdreslin@umich.edu int hitLatency; 1332810Srdreslin@umich.edu 1342810Srdreslin@umich.edu Params(TagStore *_tags, Buffering *mq, Coherence *coh, 1352813Srdreslin@umich.edu bool do_copy, BaseCache::Params params, 1362813Srdreslin@umich.edu Prefetcher<TagStore, Buffering> *_prefetcher, 1372813Srdreslin@umich.edu bool prefetch_access, int hit_latency) 1382810Srdreslin@umich.edu : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy), 1392813Srdreslin@umich.edu blockOnCopy(false), baseParams(params), 1402813Srdreslin@umich.edu prefetcher(_prefetcher), prefetchAccess(prefetch_access), 1412813Srdreslin@umich.edu hitLatency(hit_latency) 1422810Srdreslin@umich.edu { 1432810Srdreslin@umich.edu } 1442810Srdreslin@umich.edu }; 1452810Srdreslin@umich.edu 1462810Srdreslin@umich.edu /** Instantiates a basic cache object. */ 1472812Srdreslin@umich.edu Cache(const std::string &_name, Params ¶ms); 1482810Srdreslin@umich.edu 1492825Srdreslin@umich.edu virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, 1502813Srdreslin@umich.edu bool isCpuSide); 1512813Srdreslin@umich.edu 1522826Srdreslin@umich.edu virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide); 1532813Srdreslin@umich.edu 1542826Srdreslin@umich.edu virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide); 1552813Srdreslin@umich.edu 1562825Srdreslin@umich.edu virtual void recvStatusChange(Port::Status status, bool isCpuSide); 1572813Srdreslin@umich.edu 1582810Srdreslin@umich.edu void regStats(); 1592810Srdreslin@umich.edu 1602810Srdreslin@umich.edu /** 1612810Srdreslin@umich.edu * Performs the access specified by the request. 1622982Sstever@eecs.umich.edu * @param pkt The request to perform. 1632810Srdreslin@umich.edu * @return The result of the access. 1642810Srdreslin@umich.edu */ 1652812Srdreslin@umich.edu bool access(Packet * &pkt); 1662810Srdreslin@umich.edu 1672810Srdreslin@umich.edu /** 1682810Srdreslin@umich.edu * Selects a request to send on the bus. 1692810Srdreslin@umich.edu * @return The memory request to service. 1702810Srdreslin@umich.edu */ 1712844Srdreslin@umich.edu virtual Packet * getPacket(); 1722810Srdreslin@umich.edu 1732810Srdreslin@umich.edu /** 1742810Srdreslin@umich.edu * Was the request was sent successfully? 1752982Sstever@eecs.umich.edu * @param pkt The request. 1762810Srdreslin@umich.edu * @param success True if the request was sent successfully. 1772810Srdreslin@umich.edu */ 1782855Srdreslin@umich.edu virtual void sendResult(Packet * &pkt, bool success); 1792810Srdreslin@umich.edu 1802810Srdreslin@umich.edu /** 1812810Srdreslin@umich.edu * Handles a response (cache line fill/write ack) from the bus. 1822982Sstever@eecs.umich.edu * @param pkt The request being responded to. 1832810Srdreslin@umich.edu */ 1842810Srdreslin@umich.edu void handleResponse(Packet * &pkt); 1852810Srdreslin@umich.edu 1862810Srdreslin@umich.edu /** 1872810Srdreslin@umich.edu * Start handling a copy transaction. 1882982Sstever@eecs.umich.edu * @param pkt The copy request to perform. 1892810Srdreslin@umich.edu */ 1902810Srdreslin@umich.edu void startCopy(Packet * &pkt); 1912810Srdreslin@umich.edu 1922810Srdreslin@umich.edu /** 1932810Srdreslin@umich.edu * Handle a delayed copy transaction. 1942982Sstever@eecs.umich.edu * @param pkt The delayed copy request to continue. 1952810Srdreslin@umich.edu * @param addr The address being responded to. 1962810Srdreslin@umich.edu * @param blk The block of the current response. 1972810Srdreslin@umich.edu * @param mshr The mshr being handled. 1982810Srdreslin@umich.edu */ 1992810Srdreslin@umich.edu void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr); 2002810Srdreslin@umich.edu 2012810Srdreslin@umich.edu /** 2022810Srdreslin@umich.edu * Selects a coherence message to forward to lower levels of the hierarchy. 2032810Srdreslin@umich.edu * @return The coherence message to forward. 2042810Srdreslin@umich.edu */ 2052855Srdreslin@umich.edu virtual Packet * getCoherencePacket(); 2062810Srdreslin@umich.edu 2072810Srdreslin@umich.edu /** 2082810Srdreslin@umich.edu * Snoops bus transactions to maintain coherence. 2092982Sstever@eecs.umich.edu * @param pkt The current bus transaction. 2102810Srdreslin@umich.edu */ 2112810Srdreslin@umich.edu void snoop(Packet * &pkt); 2122810Srdreslin@umich.edu 2132810Srdreslin@umich.edu void snoopResponse(Packet * &pkt); 2142810Srdreslin@umich.edu 2152810Srdreslin@umich.edu /** 2162810Srdreslin@umich.edu * Invalidates the block containing address if found. 2172810Srdreslin@umich.edu * @param addr The address to look for. 2182810Srdreslin@umich.edu * @param asid The address space ID of the address. 2192810Srdreslin@umich.edu * @todo Is this function necessary? 2202810Srdreslin@umich.edu */ 2212991Srdreslin@umich.edu void invalidateBlk(Addr addr); 2222810Srdreslin@umich.edu 2232810Srdreslin@umich.edu /** 2242982Sstever@eecs.umich.edu * Squash all requests associated with specified thread. 2252810Srdreslin@umich.edu * intended for use by I-cache. 2262982Sstever@eecs.umich.edu * @param threadNum The thread to squash. 2272810Srdreslin@umich.edu */ 2282811Srdreslin@umich.edu void squash(int threadNum) 2292810Srdreslin@umich.edu { 2302811Srdreslin@umich.edu missQueue->squash(threadNum); 2312810Srdreslin@umich.edu } 2322810Srdreslin@umich.edu 2332810Srdreslin@umich.edu /** 2342810Srdreslin@umich.edu * Return the number of outstanding misses in a Cache. 2352810Srdreslin@umich.edu * Default returns 0. 2362810Srdreslin@umich.edu * 2372810Srdreslin@umich.edu * @retval unsigned The number of missing still outstanding. 2382810Srdreslin@umich.edu */ 2392810Srdreslin@umich.edu unsigned outstandingMisses() const 2402810Srdreslin@umich.edu { 2412810Srdreslin@umich.edu return missQueue->getMisses(); 2422810Srdreslin@umich.edu } 2432810Srdreslin@umich.edu 2442810Srdreslin@umich.edu /** 2452810Srdreslin@umich.edu * Perform the access specified in the request and return the estimated 2462810Srdreslin@umich.edu * time of completion. This function can either update the hierarchy state 2472810Srdreslin@umich.edu * or just perform the access wherever the data is found depending on the 2482810Srdreslin@umich.edu * state of the update flag. 2492982Sstever@eecs.umich.edu * @param pkt The memory request to satisfy 2502810Srdreslin@umich.edu * @param update If true, update the hierarchy, otherwise just perform the 2512810Srdreslin@umich.edu * request. 2522810Srdreslin@umich.edu * @return The estimated completion time. 2532810Srdreslin@umich.edu */ 2543135Srdreslin@umich.edu Tick probe(Packet * &pkt, bool update, CachePort * otherSidePort); 2552810Srdreslin@umich.edu 2562810Srdreslin@umich.edu /** 2572810Srdreslin@umich.edu * Snoop for the provided request in the cache and return the estimated 2582810Srdreslin@umich.edu * time of completion. 2592810Srdreslin@umich.edu * @todo Can a snoop probe not change state? 2602982Sstever@eecs.umich.edu * @param pkt The memory request to satisfy 2612810Srdreslin@umich.edu * @param update If true, update the hierarchy, otherwise just perform the 2622810Srdreslin@umich.edu * request. 2632810Srdreslin@umich.edu * @return The estimated completion time. 2642810Srdreslin@umich.edu */ 2653135Srdreslin@umich.edu Tick snoopProbe(Packet * &pkt); 2662810Srdreslin@umich.edu}; 2672810Srdreslin@umich.edu 2682810Srdreslin@umich.edu#endif // __CACHE_HH__ 269