cache.hh revision 11375
12810Srdreslin@umich.edu/* 211375Sandreas.hansson@arm.com * Copyright (c) 2012-2016 ARM Limited 38702Sandreas.hansson@arm.com * All rights reserved. 48702Sandreas.hansson@arm.com * 58702Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68702Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78702Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88702Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98702Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108702Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118702Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128702Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138702Sandreas.hansson@arm.com * 142810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Erik Hallnor 412810Srdreslin@umich.edu * Dave Greene 422810Srdreslin@umich.edu * Steve Reinhardt 434458Sstever@eecs.umich.edu * Ron Dreslinski 448856Sandreas.hansson@arm.com * Andreas Hansson 452810Srdreslin@umich.edu */ 462810Srdreslin@umich.edu 472810Srdreslin@umich.edu/** 482810Srdreslin@umich.edu * @file 492810Srdreslin@umich.edu * Describes a cache based on template policies. 502810Srdreslin@umich.edu */ 512810Srdreslin@umich.edu 5211051Sandreas.hansson@arm.com#ifndef __MEM_CACHE_CACHE_HH__ 5311051Sandreas.hansson@arm.com#define __MEM_CACHE_CACHE_HH__ 542810Srdreslin@umich.edu 552810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 5611197Sandreas.hansson@arm.com#include "enums/Clusivity.hh" 575338Sstever@gmail.com#include "mem/cache/base.hh" 585338Sstever@gmail.com#include "mem/cache/blk.hh" 595338Sstever@gmail.com#include "mem/cache/mshr.hh" 6010815Sdavid.guillen@arm.com#include "mem/cache/tags/base.hh" 6111053Sandreas.hansson@arm.com#include "params/Cache.hh" 624458Sstever@eecs.umich.edu#include "sim/eventq.hh" 634458Sstever@eecs.umich.edu 642813Srdreslin@umich.edu//Forward decleration 653861Sstever@eecs.umich.educlass BasePrefetcher; 662810Srdreslin@umich.edu 672810Srdreslin@umich.edu/** 682810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 692810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 709264Sdjordje.kovacevic@arm.com * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" 712810Srdreslin@umich.edu */ 722810Srdreslin@umich.educlass Cache : public BaseCache 732810Srdreslin@umich.edu{ 742810Srdreslin@umich.edu public: 7510815Sdavid.guillen@arm.com 7610815Sdavid.guillen@arm.com /** A typedef for a list of CacheBlk pointers. */ 7710815Sdavid.guillen@arm.com typedef std::list<CacheBlk*> BlkList; 782810Srdreslin@umich.edu 792810Srdreslin@umich.edu protected: 802810Srdreslin@umich.edu 818856Sandreas.hansson@arm.com /** 828856Sandreas.hansson@arm.com * The CPU-side port extends the base cache slave port with access 838856Sandreas.hansson@arm.com * functions for functional, atomic and timing requests. 848856Sandreas.hansson@arm.com */ 858856Sandreas.hansson@arm.com class CpuSidePort : public CacheSlavePort 863738Sstever@eecs.umich.edu { 878856Sandreas.hansson@arm.com private: 883738Sstever@eecs.umich.edu 898856Sandreas.hansson@arm.com // a pointer to our specific cache implementation 9010815Sdavid.guillen@arm.com Cache *cache; 913738Sstever@eecs.umich.edu 928856Sandreas.hansson@arm.com protected: 934478Sstever@eecs.umich.edu 948975Sandreas.hansson@arm.com virtual bool recvTimingSnoopResp(PacketPtr pkt); 958948Sandreas.hansson@arm.com 968975Sandreas.hansson@arm.com virtual bool recvTimingReq(PacketPtr pkt); 973738Sstever@eecs.umich.edu 983738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 993738Sstever@eecs.umich.edu 1003738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1018856Sandreas.hansson@arm.com 1029090Sandreas.hansson@arm.com virtual AddrRangeList getAddrRanges() const; 1038856Sandreas.hansson@arm.com 1048856Sandreas.hansson@arm.com public: 1058856Sandreas.hansson@arm.com 10610815Sdavid.guillen@arm.com CpuSidePort(const std::string &_name, Cache *_cache, 1078856Sandreas.hansson@arm.com const std::string &_label); 1088856Sandreas.hansson@arm.com 1093738Sstever@eecs.umich.edu }; 1103738Sstever@eecs.umich.edu 1118856Sandreas.hansson@arm.com /** 1128914Sandreas.hansson@arm.com * Override the default behaviour of sendDeferredPacket to enable 1138914Sandreas.hansson@arm.com * the memory-side cache port to also send requests based on the 1148914Sandreas.hansson@arm.com * current MSHR status. This queue has a pointer to our specific 1158914Sandreas.hansson@arm.com * cache implementation and is used by the MemSidePort. 1168914Sandreas.hansson@arm.com */ 11710713Sandreas.hansson@arm.com class CacheReqPacketQueue : public ReqPacketQueue 1188914Sandreas.hansson@arm.com { 1198914Sandreas.hansson@arm.com 1208914Sandreas.hansson@arm.com protected: 1218914Sandreas.hansson@arm.com 12210815Sdavid.guillen@arm.com Cache &cache; 12310713Sandreas.hansson@arm.com SnoopRespPacketQueue &snoopRespQueue; 1248914Sandreas.hansson@arm.com 1258914Sandreas.hansson@arm.com public: 1268914Sandreas.hansson@arm.com 12710815Sdavid.guillen@arm.com CacheReqPacketQueue(Cache &cache, MasterPort &port, 12810713Sandreas.hansson@arm.com SnoopRespPacketQueue &snoop_resp_queue, 12910713Sandreas.hansson@arm.com const std::string &label) : 13010713Sandreas.hansson@arm.com ReqPacketQueue(cache, port, label), cache(cache), 13110713Sandreas.hansson@arm.com snoopRespQueue(snoop_resp_queue) { } 1328914Sandreas.hansson@arm.com 1338914Sandreas.hansson@arm.com /** 1348914Sandreas.hansson@arm.com * Override the normal sendDeferredPacket and do not only 1358914Sandreas.hansson@arm.com * consider the transmit list (used for responses), but also 1368914Sandreas.hansson@arm.com * requests. 1378914Sandreas.hansson@arm.com */ 1388914Sandreas.hansson@arm.com virtual void sendDeferredPacket(); 1398914Sandreas.hansson@arm.com 14011375Sandreas.hansson@arm.com /** 14111375Sandreas.hansson@arm.com * Check if there is a conflicting snoop response about to be 14211375Sandreas.hansson@arm.com * send out, and if so simply stall any requests, and schedule 14311375Sandreas.hansson@arm.com * a send event at the same time as the next snoop response is 14411375Sandreas.hansson@arm.com * being sent out. 14511375Sandreas.hansson@arm.com */ 14611375Sandreas.hansson@arm.com bool checkConflictingSnoop(Addr addr) 14711375Sandreas.hansson@arm.com { 14811375Sandreas.hansson@arm.com if (snoopRespQueue.hasAddr(addr)) { 14911375Sandreas.hansson@arm.com DPRINTF(CachePort, "Waiting for snoop response to be " 15011375Sandreas.hansson@arm.com "sent\n"); 15111375Sandreas.hansson@arm.com Tick when = snoopRespQueue.deferredPacketReadyTime(); 15211375Sandreas.hansson@arm.com schedSendEvent(when); 15311375Sandreas.hansson@arm.com return true; 15411375Sandreas.hansson@arm.com } 15511375Sandreas.hansson@arm.com return false; 15611375Sandreas.hansson@arm.com } 1578914Sandreas.hansson@arm.com }; 1588914Sandreas.hansson@arm.com 1598914Sandreas.hansson@arm.com /** 1608856Sandreas.hansson@arm.com * The memory-side port extends the base cache master port with 1618856Sandreas.hansson@arm.com * access functions for functional, atomic and timing snoops. 1628856Sandreas.hansson@arm.com */ 1638856Sandreas.hansson@arm.com class MemSidePort : public CacheMasterPort 1643738Sstever@eecs.umich.edu { 1658856Sandreas.hansson@arm.com private: 1663738Sstever@eecs.umich.edu 1678914Sandreas.hansson@arm.com /** The cache-specific queue. */ 16810713Sandreas.hansson@arm.com CacheReqPacketQueue _reqQueue; 16910713Sandreas.hansson@arm.com 17010713Sandreas.hansson@arm.com SnoopRespPacketQueue _snoopRespQueue; 1718914Sandreas.hansson@arm.com 1728856Sandreas.hansson@arm.com // a pointer to our specific cache implementation 17310815Sdavid.guillen@arm.com Cache *cache; 1743738Sstever@eecs.umich.edu 1758856Sandreas.hansson@arm.com protected: 1764478Sstever@eecs.umich.edu 1778975Sandreas.hansson@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt); 1788948Sandreas.hansson@arm.com 1798975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1803738Sstever@eecs.umich.edu 1818948Sandreas.hansson@arm.com virtual Tick recvAtomicSnoop(PacketPtr pkt); 1823738Sstever@eecs.umich.edu 1838948Sandreas.hansson@arm.com virtual void recvFunctionalSnoop(PacketPtr pkt); 1844458Sstever@eecs.umich.edu 1858856Sandreas.hansson@arm.com public: 1868856Sandreas.hansson@arm.com 18710815Sdavid.guillen@arm.com MemSidePort(const std::string &_name, Cache *_cache, 1888856Sandreas.hansson@arm.com const std::string &_label); 1893738Sstever@eecs.umich.edu }; 1903738Sstever@eecs.umich.edu 1912810Srdreslin@umich.edu /** Tag and data Storage */ 19210815Sdavid.guillen@arm.com BaseTags *tags; 1934626Sstever@eecs.umich.edu 1942810Srdreslin@umich.edu /** Prefetcher */ 1953861Sstever@eecs.umich.edu BasePrefetcher *prefetcher; 1962810Srdreslin@umich.edu 1974671Sstever@eecs.umich.edu /** Temporary cache block for occasional transitory use */ 19810815Sdavid.guillen@arm.com CacheBlk *tempBlock; 1994671Sstever@eecs.umich.edu 2002810Srdreslin@umich.edu /** 2015707Shsul@eecs.umich.edu * This cache should allocate a block on a line-sized write miss. 2023860Sstever@eecs.umich.edu */ 2033860Sstever@eecs.umich.edu const bool doFastWrites; 2043860Sstever@eecs.umich.edu 2055875Ssteve.reinhardt@amd.com /** 20610345SCurtis.Dunham@arm.com * Turn line-sized writes into WriteInvalidate transactions. 20710345SCurtis.Dunham@arm.com */ 20810345SCurtis.Dunham@arm.com void promoteWholeLineWrites(PacketPtr pkt); 20910345SCurtis.Dunham@arm.com 21010345SCurtis.Dunham@arm.com /** 2115875Ssteve.reinhardt@amd.com * Notify the prefetcher on every access, not just misses. 2125875Ssteve.reinhardt@amd.com */ 2135875Ssteve.reinhardt@amd.com const bool prefetchOnAccess; 2143860Sstever@eecs.umich.edu 21511197Sandreas.hansson@arm.com /** 21611197Sandreas.hansson@arm.com * Clusivity with respect to the upstream cache, determining if we 21711197Sandreas.hansson@arm.com * fill into both this cache and the cache above on a miss. Note 21811197Sandreas.hansson@arm.com * that we currently do not support strict clusivity policies. 21911197Sandreas.hansson@arm.com */ 22011197Sandreas.hansson@arm.com const Enums::Clusivity clusivity; 22111197Sandreas.hansson@arm.com 22211199Sandreas.hansson@arm.com /** 22311199Sandreas.hansson@arm.com * Determine if clean lines should be written back or not. In 22411199Sandreas.hansson@arm.com * cases where a downstream cache is mostly inclusive we likely 22511199Sandreas.hansson@arm.com * want it to act as a victim cache also for lines that have not 22611199Sandreas.hansson@arm.com * been modified. Hence, we cannot simply drop the line (or send a 22711199Sandreas.hansson@arm.com * clean evict), but rather need to send the actual data. 22811199Sandreas.hansson@arm.com */ 22911199Sandreas.hansson@arm.com const bool writebackClean; 23011199Sandreas.hansson@arm.com 2313860Sstever@eecs.umich.edu /** 23211190Sandreas.hansson@arm.com * Upstream caches need this packet until true is returned, so 23311190Sandreas.hansson@arm.com * hold it for deletion until a subsequent call 2349063SAli.Saidi@ARM.com */ 23511190Sandreas.hansson@arm.com std::unique_ptr<Packet> pendingDelete; 2369063SAli.Saidi@ARM.com 2379063SAli.Saidi@ARM.com /** 23811197Sandreas.hansson@arm.com * Writebacks from the tempBlock, resulting on the response path 23911197Sandreas.hansson@arm.com * in atomic mode, must happen after the call to recvAtomic has 24011197Sandreas.hansson@arm.com * finished (for the right ordering of the packets). We therefore 24111197Sandreas.hansson@arm.com * need to hold on to the packets, and have a method and an event 24211197Sandreas.hansson@arm.com * to send them. 24311197Sandreas.hansson@arm.com */ 24411197Sandreas.hansson@arm.com PacketPtr tempBlockWriteback; 24511197Sandreas.hansson@arm.com 24611197Sandreas.hansson@arm.com /** 24711197Sandreas.hansson@arm.com * Send the outstanding tempBlock writeback. To be called after 24811197Sandreas.hansson@arm.com * recvAtomic finishes in cases where the block we filled is in 24911197Sandreas.hansson@arm.com * fact the tempBlock, and now needs to be written back. 25011197Sandreas.hansson@arm.com */ 25111197Sandreas.hansson@arm.com void writebackTempBlockAtomic() { 25211197Sandreas.hansson@arm.com assert(tempBlockWriteback != nullptr); 25311197Sandreas.hansson@arm.com PacketList writebacks{tempBlockWriteback}; 25411197Sandreas.hansson@arm.com doWritebacksAtomic(writebacks); 25511197Sandreas.hansson@arm.com tempBlockWriteback = nullptr; 25611197Sandreas.hansson@arm.com } 25711197Sandreas.hansson@arm.com 25811197Sandreas.hansson@arm.com /** 25911197Sandreas.hansson@arm.com * An event to writeback the tempBlock after recvAtomic 26011197Sandreas.hansson@arm.com * finishes. To avoid other calls to recvAtomic getting in 26111197Sandreas.hansson@arm.com * between, we create this event with a higher priority. 26211197Sandreas.hansson@arm.com */ 26311197Sandreas.hansson@arm.com EventWrapper<Cache, &Cache::writebackTempBlockAtomic> \ 26411197Sandreas.hansson@arm.com writebackTempBlockAtomicEvent; 26511197Sandreas.hansson@arm.com 26611197Sandreas.hansson@arm.com /** 26711276Sandreas.hansson@arm.com * Store the outstanding requests that we are expecting snoop 26811276Sandreas.hansson@arm.com * responses from so we can determine which snoop responses we 26911276Sandreas.hansson@arm.com * generated and which ones were merely forwarded. 27011276Sandreas.hansson@arm.com */ 27111276Sandreas.hansson@arm.com std::unordered_set<RequestPtr> outstandingSnoop; 27211276Sandreas.hansson@arm.com 27311276Sandreas.hansson@arm.com /** 2743860Sstever@eecs.umich.edu * Does all the processing necessary to perform the provided request. 2753860Sstever@eecs.umich.edu * @param pkt The memory request to perform. 27610048Saminfar@gmail.com * @param blk The cache block to be updated. 2773860Sstever@eecs.umich.edu * @param lat The latency of the access. 2783860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2795707Shsul@eecs.umich.edu * @return Boolean indicating whether the request was satisfied. 2803860Sstever@eecs.umich.edu */ 28110815Sdavid.guillen@arm.com bool access(PacketPtr pkt, CacheBlk *&blk, 2829288Sandreas.hansson@arm.com Cycles &lat, PacketList &writebacks); 2834219Srdreslin@umich.edu 2844219Srdreslin@umich.edu /** 2854219Srdreslin@umich.edu *Handle doing the Compare and Swap function for SPARC. 2864219Srdreslin@umich.edu */ 28710815Sdavid.guillen@arm.com void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); 2883860Sstever@eecs.umich.edu 2893860Sstever@eecs.umich.edu /** 29010028SGiacomo.Gabrielli@arm.com * Find a block frame for new block at address addr targeting the 29110028SGiacomo.Gabrielli@arm.com * given security space, assuming that the block is not currently 29210028SGiacomo.Gabrielli@arm.com * in the cache. Append writebacks if any to provided packet 29310028SGiacomo.Gabrielli@arm.com * list. Return free block frame. May return NULL if there are 29410028SGiacomo.Gabrielli@arm.com * no replaceable blocks at the moment. 2955350Sstever@gmail.com */ 29610815Sdavid.guillen@arm.com CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); 2975350Sstever@gmail.com 2985350Sstever@gmail.com /** 29911197Sandreas.hansson@arm.com * Invalidate a cache block. 30011197Sandreas.hansson@arm.com * 30111197Sandreas.hansson@arm.com * @param blk Block to invalidate 30211197Sandreas.hansson@arm.com */ 30311197Sandreas.hansson@arm.com void invalidateBlock(CacheBlk *blk); 30411197Sandreas.hansson@arm.com 30511197Sandreas.hansson@arm.com /** 3063860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 3073860Sstever@eecs.umich.edu * satisfied fill request. This version takes two memory requests. One 3083860Sstever@eecs.umich.edu * contains the fill data, the other is an optional target to satisfy. 3094626Sstever@eecs.umich.edu * @param pkt The memory request with the fill data. 3103860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 3113860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 31211197Sandreas.hansson@arm.com * @param allocate Whether to allocate a block or use the temp block 3133860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 3143860Sstever@eecs.umich.edu */ 31510815Sdavid.guillen@arm.com CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, 31611197Sandreas.hansson@arm.com PacketList &writebacks, bool allocate); 3173860Sstever@eecs.umich.edu 31811197Sandreas.hansson@arm.com /** 31911197Sandreas.hansson@arm.com * Determine whether we should allocate on a fill or not. If this 32011197Sandreas.hansson@arm.com * cache is mostly inclusive with regards to the upstream cache(s) 32111197Sandreas.hansson@arm.com * we always allocate (for any non-forwarded and cacheable 32211197Sandreas.hansson@arm.com * requests). In the case of a mostly exclusive cache, we allocate 32311197Sandreas.hansson@arm.com * on fill if the packet did not come from a cache, thus if we: 32411197Sandreas.hansson@arm.com * are dealing with a whole-line write (the latter behaves much 32511197Sandreas.hansson@arm.com * like a writeback), the original target packet came from a 32611197Sandreas.hansson@arm.com * non-caching source, or if we are performing a prefetch or LLSC. 32711197Sandreas.hansson@arm.com * 32811197Sandreas.hansson@arm.com * @param cmd Command of the incoming requesting packet 32911197Sandreas.hansson@arm.com * @return Whether we should allocate on the fill 33011197Sandreas.hansson@arm.com */ 33111211Sandreas.sandberg@arm.com inline bool allocOnFill(MemCmd cmd) const override 33211197Sandreas.hansson@arm.com { 33311197Sandreas.hansson@arm.com return clusivity == Enums::mostly_incl || 33411197Sandreas.hansson@arm.com cmd == MemCmd::WriteLineReq || 33511197Sandreas.hansson@arm.com cmd == MemCmd::ReadReq || 33611197Sandreas.hansson@arm.com cmd == MemCmd::WriteReq || 33711197Sandreas.hansson@arm.com cmd.isPrefetch() || 33811197Sandreas.hansson@arm.com cmd.isLLSC(); 33911197Sandreas.hansson@arm.com } 3409548Sandreas.hansson@arm.com 3419548Sandreas.hansson@arm.com /** 3429548Sandreas.hansson@arm.com * Performs the access specified by the request. 3439548Sandreas.hansson@arm.com * @param pkt The request to perform. 3449548Sandreas.hansson@arm.com * @return The result of the access. 3459548Sandreas.hansson@arm.com */ 3469548Sandreas.hansson@arm.com bool recvTimingReq(PacketPtr pkt); 3479548Sandreas.hansson@arm.com 3489548Sandreas.hansson@arm.com /** 34910883Sali.jafri@arm.com * Insert writebacks into the write buffer 35010883Sali.jafri@arm.com */ 35110883Sali.jafri@arm.com void doWritebacks(PacketList& writebacks, Tick forward_time); 35210883Sali.jafri@arm.com 35310883Sali.jafri@arm.com /** 35411130Sali.jafri@arm.com * Send writebacks down the memory hierarchy in atomic mode 35511130Sali.jafri@arm.com */ 35611130Sali.jafri@arm.com void doWritebacksAtomic(PacketList& writebacks); 35711130Sali.jafri@arm.com 35811130Sali.jafri@arm.com /** 35911375Sandreas.hansson@arm.com * Handling the special case of uncacheable write responses to 36011375Sandreas.hansson@arm.com * make recvTimingResp less cluttered. 36111375Sandreas.hansson@arm.com */ 36211375Sandreas.hansson@arm.com void handleUncacheableWriteResp(PacketPtr pkt); 36311375Sandreas.hansson@arm.com 36411375Sandreas.hansson@arm.com /** 3659548Sandreas.hansson@arm.com * Handles a response (cache line fill/write ack) from the bus. 3669548Sandreas.hansson@arm.com * @param pkt The response packet 3679548Sandreas.hansson@arm.com */ 3689548Sandreas.hansson@arm.com void recvTimingResp(PacketPtr pkt); 3699548Sandreas.hansson@arm.com 3709548Sandreas.hansson@arm.com /** 3719548Sandreas.hansson@arm.com * Snoops bus transactions to maintain coherence. 3729548Sandreas.hansson@arm.com * @param pkt The current bus transaction. 3739548Sandreas.hansson@arm.com */ 3749548Sandreas.hansson@arm.com void recvTimingSnoopReq(PacketPtr pkt); 3759548Sandreas.hansson@arm.com 3769548Sandreas.hansson@arm.com /** 3779548Sandreas.hansson@arm.com * Handle a snoop response. 3789548Sandreas.hansson@arm.com * @param pkt Snoop response packet 3799548Sandreas.hansson@arm.com */ 3809548Sandreas.hansson@arm.com void recvTimingSnoopResp(PacketPtr pkt); 3819548Sandreas.hansson@arm.com 3829548Sandreas.hansson@arm.com /** 3839548Sandreas.hansson@arm.com * Performs the access specified by the request. 3849548Sandreas.hansson@arm.com * @param pkt The request to perform. 3859782Sandreas.hansson@arm.com * @return The number of ticks required for the access. 3869548Sandreas.hansson@arm.com */ 3879782Sandreas.hansson@arm.com Tick recvAtomic(PacketPtr pkt); 3889548Sandreas.hansson@arm.com 3899548Sandreas.hansson@arm.com /** 3909548Sandreas.hansson@arm.com * Snoop for the provided request in the cache and return the estimated 3919782Sandreas.hansson@arm.com * time taken. 3929548Sandreas.hansson@arm.com * @param pkt The memory request to snoop 3939782Sandreas.hansson@arm.com * @return The number of ticks required for the snoop. 3949548Sandreas.hansson@arm.com */ 3959782Sandreas.hansson@arm.com Tick recvAtomicSnoop(PacketPtr pkt); 3969548Sandreas.hansson@arm.com 3979548Sandreas.hansson@arm.com /** 3989548Sandreas.hansson@arm.com * Performs the access specified by the request. 3999548Sandreas.hansson@arm.com * @param pkt The request to perform. 4009548Sandreas.hansson@arm.com * @param fromCpuSide from the CPU side port or the memory side port 4019548Sandreas.hansson@arm.com */ 4029548Sandreas.hansson@arm.com void functionalAccess(PacketPtr pkt, bool fromCpuSide); 4039548Sandreas.hansson@arm.com 40410815Sdavid.guillen@arm.com void satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, 4057667Ssteve.reinhardt@amd.com bool deferred_response = false, 4067667Ssteve.reinhardt@amd.com bool pending_downgrade = false); 40710815Sdavid.guillen@arm.com bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, CacheBlk *blk); 4084626Sstever@eecs.umich.edu 40910563Sandreas.hansson@arm.com void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 4105319Sstever@gmail.com bool already_copied, bool pending_inval); 4113860Sstever@eecs.umich.edu 4123860Sstever@eecs.umich.edu /** 41311127Sandreas.hansson@arm.com * Perform an upward snoop if needed, and update the block state 41411127Sandreas.hansson@arm.com * (possibly invalidating the block). Also create a response if required. 41511127Sandreas.hansson@arm.com * 41611127Sandreas.hansson@arm.com * @param pkt Snoop packet 41711127Sandreas.hansson@arm.com * @param blk Cache block being snooped 41811127Sandreas.hansson@arm.com * @param is_timing Timing or atomic for the response 41911127Sandreas.hansson@arm.com * @param is_deferred Is this a deferred snoop or not? 42011127Sandreas.hansson@arm.com * @param pending_inval Do we have a pending invalidation? 42111127Sandreas.hansson@arm.com * 42211127Sandreas.hansson@arm.com * @return The snoop delay incurred by the upwards snoop 4233860Sstever@eecs.umich.edu */ 42411127Sandreas.hansson@arm.com uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk, 42511127Sandreas.hansson@arm.com bool is_timing, bool is_deferred, bool pending_inval); 4263860Sstever@eecs.umich.edu 4273860Sstever@eecs.umich.edu /** 4283860Sstever@eecs.umich.edu * Create a writeback request for the given block. 4293860Sstever@eecs.umich.edu * @param blk The block to writeback. 4303860Sstever@eecs.umich.edu * @return The writeback request for the block. 4313860Sstever@eecs.umich.edu */ 43210815Sdavid.guillen@arm.com PacketPtr writebackBlk(CacheBlk *blk); 4333860Sstever@eecs.umich.edu 43410883Sali.jafri@arm.com /** 43510883Sali.jafri@arm.com * Create a CleanEvict request for the given block. 43610883Sali.jafri@arm.com * @param blk The block to evict. 43710883Sali.jafri@arm.com * @return The CleanEvict request for the block. 43810883Sali.jafri@arm.com */ 43910883Sali.jafri@arm.com PacketPtr cleanEvictBlk(CacheBlk *blk); 44010883Sali.jafri@arm.com 4419347SAndreas.Sandberg@arm.com 44211169Sandreas.hansson@arm.com void memWriteback() override; 44311169Sandreas.hansson@arm.com void memInvalidate() override; 44411169Sandreas.hansson@arm.com bool isDirty() const override; 4459347SAndreas.Sandberg@arm.com 4469347SAndreas.Sandberg@arm.com /** 4479347SAndreas.Sandberg@arm.com * Cache block visitor that writes back dirty cache blocks using 4489347SAndreas.Sandberg@arm.com * functional writes. 4499347SAndreas.Sandberg@arm.com * 4509347SAndreas.Sandberg@arm.com * \return Always returns true. 4519347SAndreas.Sandberg@arm.com */ 45210815Sdavid.guillen@arm.com bool writebackVisitor(CacheBlk &blk); 4539347SAndreas.Sandberg@arm.com /** 4549347SAndreas.Sandberg@arm.com * Cache block visitor that invalidates all blocks in the cache. 4559347SAndreas.Sandberg@arm.com * 4569347SAndreas.Sandberg@arm.com * @warn Dirty cache lines will not be written back to memory. 4579347SAndreas.Sandberg@arm.com * 4589347SAndreas.Sandberg@arm.com * \return Always returns true. 4599347SAndreas.Sandberg@arm.com */ 46010815Sdavid.guillen@arm.com bool invalidateVisitor(CacheBlk &blk); 4619347SAndreas.Sandberg@arm.com 4629445SAndreas.Sandberg@ARM.com /** 4635365Sstever@gmail.com * Generate an appropriate downstream bus request packet for the 4645365Sstever@gmail.com * given parameters. 4655365Sstever@gmail.com * @param cpu_pkt The upstream request that needs to be satisfied. 4665365Sstever@gmail.com * @param blk The block currently in the cache corresponding to 4675365Sstever@gmail.com * cpu_pkt (NULL if none). 4685365Sstever@gmail.com * @param needsExclusive Indicates that an exclusive copy is required 4695365Sstever@gmail.com * even if the request in cpu_pkt doesn't indicate that. 4705365Sstever@gmail.com * @return A new Packet containing the request, or NULL if the 4715365Sstever@gmail.com * current request in cpu_pkt should just be forwarded on. 4724626Sstever@eecs.umich.edu */ 47310815Sdavid.guillen@arm.com PacketPtr getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, 4749529Sandreas.hansson@arm.com bool needsExclusive) const; 4755365Sstever@gmail.com 4765365Sstever@gmail.com /** 47711375Sandreas.hansson@arm.com * Return the next queue entry to service, either a pending miss 47811375Sandreas.hansson@arm.com * from the MSHR queue, a buffered write from the write buffer, or 47911375Sandreas.hansson@arm.com * something from the prefetcher. This function is responsible 48011375Sandreas.hansson@arm.com * for prioritizing among those sources on the fly. 4815365Sstever@gmail.com */ 48211375Sandreas.hansson@arm.com QueueEntry* getNextQueueEntry(); 4835365Sstever@gmail.com 4845365Sstever@gmail.com /** 48510883Sali.jafri@arm.com * Send up a snoop request and find cached copies. If cached copies are 48610883Sali.jafri@arm.com * found, set the BLOCK_CACHED flag in pkt. 48710883Sali.jafri@arm.com */ 48811130Sali.jafri@arm.com bool isCachedAbove(PacketPtr pkt, bool is_timing = true) const; 48910883Sali.jafri@arm.com 49010883Sali.jafri@arm.com /** 4914626Sstever@eecs.umich.edu * Return whether there are any outstanding misses. 4924626Sstever@eecs.umich.edu */ 4934626Sstever@eecs.umich.edu bool outstandingMisses() const 4942810Srdreslin@umich.edu { 49511375Sandreas.hansson@arm.com return !mshrQueue.isEmpty(); 4962810Srdreslin@umich.edu } 4972810Srdreslin@umich.edu 49810028SGiacomo.Gabrielli@arm.com CacheBlk *findBlock(Addr addr, bool is_secure) const { 49910028SGiacomo.Gabrielli@arm.com return tags->findBlock(addr, is_secure); 5002810Srdreslin@umich.edu } 5012810Srdreslin@umich.edu 50211169Sandreas.hansson@arm.com bool inCache(Addr addr, bool is_secure) const override { 50310028SGiacomo.Gabrielli@arm.com return (tags->findBlock(addr, is_secure) != 0); 5043861Sstever@eecs.umich.edu } 5053861Sstever@eecs.umich.edu 50611169Sandreas.hansson@arm.com bool inMissQueue(Addr addr, bool is_secure) const override { 50710028SGiacomo.Gabrielli@arm.com return (mshrQueue.findMatch(addr, is_secure) != 0); 5083861Sstever@eecs.umich.edu } 5095875Ssteve.reinhardt@amd.com 5105875Ssteve.reinhardt@amd.com /** 5115875Ssteve.reinhardt@amd.com * Find next request ready time from among possible sources. 5125875Ssteve.reinhardt@amd.com */ 51311375Sandreas.hansson@arm.com Tick nextQueueReadyTime() const; 5149529Sandreas.hansson@arm.com 5159529Sandreas.hansson@arm.com public: 5169529Sandreas.hansson@arm.com /** Instantiates a basic cache object. */ 51711053Sandreas.hansson@arm.com Cache(const CacheParams *p); 5189529Sandreas.hansson@arm.com 5199813Srioshering@gmail.com /** Non-default destructor is needed to deallocate memory. */ 5209813Srioshering@gmail.com virtual ~Cache(); 5219813Srioshering@gmail.com 52211169Sandreas.hansson@arm.com void regStats() override; 5238985SAli.Saidi@ARM.com 52411375Sandreas.hansson@arm.com /** 52511375Sandreas.hansson@arm.com * Take an MSHR, turn it into a suitable downstream packet, and 52611375Sandreas.hansson@arm.com * send it out. This construct allows a queue entry to choose a suitable 52711375Sandreas.hansson@arm.com * approach based on its type. 52811375Sandreas.hansson@arm.com * 52911375Sandreas.hansson@arm.com * @param mshr The MSHR to turn into a packet and send 53011375Sandreas.hansson@arm.com * @return True if the port is waiting for a retry 53111375Sandreas.hansson@arm.com */ 53211375Sandreas.hansson@arm.com bool sendMSHRQueuePacket(MSHR* mshr); 53311375Sandreas.hansson@arm.com 53411375Sandreas.hansson@arm.com /** 53511375Sandreas.hansson@arm.com * Similar to sendMSHR, but for a write-queue entry 53611375Sandreas.hansson@arm.com * instead. Create the packet, and send it, and if successful also 53711375Sandreas.hansson@arm.com * mark the entry in service. 53811375Sandreas.hansson@arm.com * 53911375Sandreas.hansson@arm.com * @param wq_entry The write-queue entry to turn into a packet and send 54011375Sandreas.hansson@arm.com * @return True if the port is waiting for a retry 54111375Sandreas.hansson@arm.com */ 54211375Sandreas.hansson@arm.com bool sendWriteQueuePacket(WriteQueueEntry* wq_entry); 54311375Sandreas.hansson@arm.com 5448985SAli.Saidi@ARM.com /** serialize the state of the caches 5458985SAli.Saidi@ARM.com * We currently don't support checkpointing cache state, so this panics. 5468985SAli.Saidi@ARM.com */ 54711168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 54811168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 5492810Srdreslin@umich.edu}; 5502810Srdreslin@umich.edu 55110815Sdavid.guillen@arm.com/** 55210815Sdavid.guillen@arm.com * Wrap a method and present it as a cache block visitor. 55310815Sdavid.guillen@arm.com * 55410815Sdavid.guillen@arm.com * For example the forEachBlk method in the tag arrays expects a 55510815Sdavid.guillen@arm.com * callable object/function as their parameter. This class wraps a 55610815Sdavid.guillen@arm.com * method in an object and presents callable object that adheres to 55710815Sdavid.guillen@arm.com * the cache block visitor protocol. 55810815Sdavid.guillen@arm.com */ 55910815Sdavid.guillen@arm.comclass CacheBlkVisitorWrapper : public CacheBlkVisitor 56010815Sdavid.guillen@arm.com{ 56110815Sdavid.guillen@arm.com public: 56210815Sdavid.guillen@arm.com typedef bool (Cache::*VisitorPtr)(CacheBlk &blk); 56310815Sdavid.guillen@arm.com 56410815Sdavid.guillen@arm.com CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor) 56510815Sdavid.guillen@arm.com : cache(_cache), visitor(_visitor) {} 56610815Sdavid.guillen@arm.com 56711168Sandreas.hansson@arm.com bool operator()(CacheBlk &blk) override { 56810815Sdavid.guillen@arm.com return (cache.*visitor)(blk); 56910815Sdavid.guillen@arm.com } 57010815Sdavid.guillen@arm.com 57110815Sdavid.guillen@arm.com private: 57210815Sdavid.guillen@arm.com Cache &cache; 57310815Sdavid.guillen@arm.com VisitorPtr visitor; 57410815Sdavid.guillen@arm.com}; 57510815Sdavid.guillen@arm.com 57610815Sdavid.guillen@arm.com/** 57710815Sdavid.guillen@arm.com * Cache block visitor that determines if there are dirty blocks in a 57810815Sdavid.guillen@arm.com * cache. 57910815Sdavid.guillen@arm.com * 58010815Sdavid.guillen@arm.com * Use with the forEachBlk method in the tag array to determine if the 58110815Sdavid.guillen@arm.com * array contains dirty blocks. 58210815Sdavid.guillen@arm.com */ 58310815Sdavid.guillen@arm.comclass CacheBlkIsDirtyVisitor : public CacheBlkVisitor 58410815Sdavid.guillen@arm.com{ 58510815Sdavid.guillen@arm.com public: 58610815Sdavid.guillen@arm.com CacheBlkIsDirtyVisitor() 58710815Sdavid.guillen@arm.com : _isDirty(false) {} 58810815Sdavid.guillen@arm.com 58911168Sandreas.hansson@arm.com bool operator()(CacheBlk &blk) override { 59010815Sdavid.guillen@arm.com if (blk.isDirty()) { 59110815Sdavid.guillen@arm.com _isDirty = true; 59210815Sdavid.guillen@arm.com return false; 59310815Sdavid.guillen@arm.com } else { 59410815Sdavid.guillen@arm.com return true; 59510815Sdavid.guillen@arm.com } 59610815Sdavid.guillen@arm.com } 59710815Sdavid.guillen@arm.com 59810815Sdavid.guillen@arm.com /** 59910815Sdavid.guillen@arm.com * Does the array contain a dirty line? 60010815Sdavid.guillen@arm.com * 60110815Sdavid.guillen@arm.com * \return true if yes, false otherwise. 60210815Sdavid.guillen@arm.com */ 60310815Sdavid.guillen@arm.com bool isDirty() const { return _isDirty; }; 60410815Sdavid.guillen@arm.com 60510815Sdavid.guillen@arm.com private: 60610815Sdavid.guillen@arm.com bool _isDirty; 60710815Sdavid.guillen@arm.com}; 60810815Sdavid.guillen@arm.com 60911051Sandreas.hansson@arm.com#endif // __MEM_CACHE_CACHE_HH__ 610