cache.hh revision 10048
12810Srdreslin@umich.edu/* 29529Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited 38702Sandreas.hansson@arm.com * All rights reserved. 48702Sandreas.hansson@arm.com * 58702Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68702Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78702Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88702Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98702Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108702Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118702Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128702Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138702Sandreas.hansson@arm.com * 142810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Erik Hallnor 412810Srdreslin@umich.edu * Dave Greene 422810Srdreslin@umich.edu * Steve Reinhardt 434458Sstever@eecs.umich.edu * Ron Dreslinski 448856Sandreas.hansson@arm.com * Andreas Hansson 452810Srdreslin@umich.edu */ 462810Srdreslin@umich.edu 472810Srdreslin@umich.edu/** 482810Srdreslin@umich.edu * @file 492810Srdreslin@umich.edu * Describes a cache based on template policies. 502810Srdreslin@umich.edu */ 512810Srdreslin@umich.edu 522810Srdreslin@umich.edu#ifndef __CACHE_HH__ 532810Srdreslin@umich.edu#define __CACHE_HH__ 542810Srdreslin@umich.edu 552810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 565338Sstever@gmail.com#include "mem/cache/base.hh" 575338Sstever@gmail.com#include "mem/cache/blk.hh" 585338Sstever@gmail.com#include "mem/cache/mshr.hh" 594458Sstever@eecs.umich.edu#include "sim/eventq.hh" 604458Sstever@eecs.umich.edu 612813Srdreslin@umich.edu//Forward decleration 623861Sstever@eecs.umich.educlass BasePrefetcher; 632810Srdreslin@umich.edu 642810Srdreslin@umich.edu/** 652810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 662810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 679264Sdjordje.kovacevic@arm.com * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" 682810Srdreslin@umich.edu */ 694672Sstever@eecs.umich.edutemplate <class TagStore> 702810Srdreslin@umich.educlass Cache : public BaseCache 712810Srdreslin@umich.edu{ 722810Srdreslin@umich.edu public: 732810Srdreslin@umich.edu /** Define the type of cache block to use. */ 742810Srdreslin@umich.edu typedef typename TagStore::BlkType BlkType; 753860Sstever@eecs.umich.edu /** A typedef for a list of BlkType pointers. */ 763860Sstever@eecs.umich.edu typedef typename TagStore::BlkList BlkList; 772810Srdreslin@umich.edu 782810Srdreslin@umich.edu protected: 799347SAndreas.Sandberg@arm.com typedef CacheBlkVisitorWrapper<Cache<TagStore>, BlkType> WrappedBlkVisitor; 802810Srdreslin@umich.edu 818856Sandreas.hansson@arm.com /** 828856Sandreas.hansson@arm.com * The CPU-side port extends the base cache slave port with access 838856Sandreas.hansson@arm.com * functions for functional, atomic and timing requests. 848856Sandreas.hansson@arm.com */ 858856Sandreas.hansson@arm.com class CpuSidePort : public CacheSlavePort 863738Sstever@eecs.umich.edu { 878856Sandreas.hansson@arm.com private: 883738Sstever@eecs.umich.edu 898856Sandreas.hansson@arm.com // a pointer to our specific cache implementation 908856Sandreas.hansson@arm.com Cache<TagStore> *cache; 913738Sstever@eecs.umich.edu 928856Sandreas.hansson@arm.com protected: 934478Sstever@eecs.umich.edu 948975Sandreas.hansson@arm.com virtual bool recvTimingSnoopResp(PacketPtr pkt); 958948Sandreas.hansson@arm.com 968975Sandreas.hansson@arm.com virtual bool recvTimingReq(PacketPtr pkt); 973738Sstever@eecs.umich.edu 983738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 993738Sstever@eecs.umich.edu 1003738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1018856Sandreas.hansson@arm.com 1029090Sandreas.hansson@arm.com virtual AddrRangeList getAddrRanges() const; 1038856Sandreas.hansson@arm.com 1048856Sandreas.hansson@arm.com public: 1058856Sandreas.hansson@arm.com 1068856Sandreas.hansson@arm.com CpuSidePort(const std::string &_name, Cache<TagStore> *_cache, 1078856Sandreas.hansson@arm.com const std::string &_label); 1088856Sandreas.hansson@arm.com 1093738Sstever@eecs.umich.edu }; 1103738Sstever@eecs.umich.edu 1118856Sandreas.hansson@arm.com /** 1128914Sandreas.hansson@arm.com * Override the default behaviour of sendDeferredPacket to enable 1138914Sandreas.hansson@arm.com * the memory-side cache port to also send requests based on the 1148914Sandreas.hansson@arm.com * current MSHR status. This queue has a pointer to our specific 1158914Sandreas.hansson@arm.com * cache implementation and is used by the MemSidePort. 1168914Sandreas.hansson@arm.com */ 1178975Sandreas.hansson@arm.com class MemSidePacketQueue : public MasterPacketQueue 1188914Sandreas.hansson@arm.com { 1198914Sandreas.hansson@arm.com 1208914Sandreas.hansson@arm.com protected: 1218914Sandreas.hansson@arm.com 1228914Sandreas.hansson@arm.com Cache<TagStore> &cache; 1238914Sandreas.hansson@arm.com 1248914Sandreas.hansson@arm.com public: 1258914Sandreas.hansson@arm.com 1268975Sandreas.hansson@arm.com MemSidePacketQueue(Cache<TagStore> &cache, MasterPort &port, 1278914Sandreas.hansson@arm.com const std::string &label) : 1288975Sandreas.hansson@arm.com MasterPacketQueue(cache, port, label), cache(cache) { } 1298914Sandreas.hansson@arm.com 1308914Sandreas.hansson@arm.com /** 1318914Sandreas.hansson@arm.com * Override the normal sendDeferredPacket and do not only 1328914Sandreas.hansson@arm.com * consider the transmit list (used for responses), but also 1338914Sandreas.hansson@arm.com * requests. 1348914Sandreas.hansson@arm.com */ 1358914Sandreas.hansson@arm.com virtual void sendDeferredPacket(); 1368914Sandreas.hansson@arm.com 1378914Sandreas.hansson@arm.com }; 1388914Sandreas.hansson@arm.com 1398914Sandreas.hansson@arm.com /** 1408856Sandreas.hansson@arm.com * The memory-side port extends the base cache master port with 1418856Sandreas.hansson@arm.com * access functions for functional, atomic and timing snoops. 1428856Sandreas.hansson@arm.com */ 1438856Sandreas.hansson@arm.com class MemSidePort : public CacheMasterPort 1443738Sstever@eecs.umich.edu { 1458856Sandreas.hansson@arm.com private: 1463738Sstever@eecs.umich.edu 1478914Sandreas.hansson@arm.com /** The cache-specific queue. */ 1488914Sandreas.hansson@arm.com MemSidePacketQueue _queue; 1498914Sandreas.hansson@arm.com 1508856Sandreas.hansson@arm.com // a pointer to our specific cache implementation 1518856Sandreas.hansson@arm.com Cache<TagStore> *cache; 1523738Sstever@eecs.umich.edu 1538856Sandreas.hansson@arm.com protected: 1544478Sstever@eecs.umich.edu 1558975Sandreas.hansson@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt); 1568948Sandreas.hansson@arm.com 1578975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1583738Sstever@eecs.umich.edu 1598948Sandreas.hansson@arm.com virtual Tick recvAtomicSnoop(PacketPtr pkt); 1603738Sstever@eecs.umich.edu 1618948Sandreas.hansson@arm.com virtual void recvFunctionalSnoop(PacketPtr pkt); 1624458Sstever@eecs.umich.edu 1638856Sandreas.hansson@arm.com public: 1648856Sandreas.hansson@arm.com 1658856Sandreas.hansson@arm.com MemSidePort(const std::string &_name, Cache<TagStore> *_cache, 1668856Sandreas.hansson@arm.com const std::string &_label); 1673738Sstever@eecs.umich.edu }; 1683738Sstever@eecs.umich.edu 1692810Srdreslin@umich.edu /** Tag and data Storage */ 1702810Srdreslin@umich.edu TagStore *tags; 1714626Sstever@eecs.umich.edu 1722810Srdreslin@umich.edu /** Prefetcher */ 1733861Sstever@eecs.umich.edu BasePrefetcher *prefetcher; 1742810Srdreslin@umich.edu 1754671Sstever@eecs.umich.edu /** Temporary cache block for occasional transitory use */ 1764671Sstever@eecs.umich.edu BlkType *tempBlock; 1774671Sstever@eecs.umich.edu 1782810Srdreslin@umich.edu /** 1795707Shsul@eecs.umich.edu * This cache should allocate a block on a line-sized write miss. 1803860Sstever@eecs.umich.edu */ 1813860Sstever@eecs.umich.edu const bool doFastWrites; 1823860Sstever@eecs.umich.edu 1835875Ssteve.reinhardt@amd.com /** 1845875Ssteve.reinhardt@amd.com * Notify the prefetcher on every access, not just misses. 1855875Ssteve.reinhardt@amd.com */ 1865875Ssteve.reinhardt@amd.com const bool prefetchOnAccess; 1873860Sstever@eecs.umich.edu 1883860Sstever@eecs.umich.edu /** 1899063SAli.Saidi@ARM.com * @todo this is a temporary workaround until the 4-phase code is committed. 1909063SAli.Saidi@ARM.com * upstream caches need this packet until true is returned, so hold it for 1919063SAli.Saidi@ARM.com * deletion until a subsequent call 1929063SAli.Saidi@ARM.com */ 1939063SAli.Saidi@ARM.com std::vector<PacketPtr> pendingDelete; 1949063SAli.Saidi@ARM.com 1959063SAli.Saidi@ARM.com /** 1963860Sstever@eecs.umich.edu * Does all the processing necessary to perform the provided request. 1973860Sstever@eecs.umich.edu * @param pkt The memory request to perform. 19810048Saminfar@gmail.com * @param blk The cache block to be updated. 1993860Sstever@eecs.umich.edu * @param lat The latency of the access. 2003860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2015707Shsul@eecs.umich.edu * @return Boolean indicating whether the request was satisfied. 2023860Sstever@eecs.umich.edu */ 2035388Sstever@gmail.com bool access(PacketPtr pkt, BlkType *&blk, 2049288Sandreas.hansson@arm.com Cycles &lat, PacketList &writebacks); 2054219Srdreslin@umich.edu 2064219Srdreslin@umich.edu /** 2074219Srdreslin@umich.edu *Handle doing the Compare and Swap function for SPARC. 2084219Srdreslin@umich.edu */ 2094626Sstever@eecs.umich.edu void cmpAndSwap(BlkType *blk, PacketPtr pkt); 2103860Sstever@eecs.umich.edu 2113860Sstever@eecs.umich.edu /** 21210028SGiacomo.Gabrielli@arm.com * Find a block frame for new block at address addr targeting the 21310028SGiacomo.Gabrielli@arm.com * given security space, assuming that the block is not currently 21410028SGiacomo.Gabrielli@arm.com * in the cache. Append writebacks if any to provided packet 21510028SGiacomo.Gabrielli@arm.com * list. Return free block frame. May return NULL if there are 21610028SGiacomo.Gabrielli@arm.com * no replaceable blocks at the moment. 2175350Sstever@gmail.com */ 21810028SGiacomo.Gabrielli@arm.com BlkType *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); 2195350Sstever@gmail.com 2205350Sstever@gmail.com /** 2213860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 2223860Sstever@eecs.umich.edu * satisfied fill request. This version takes two memory requests. One 2233860Sstever@eecs.umich.edu * contains the fill data, the other is an optional target to satisfy. 2244626Sstever@eecs.umich.edu * @param pkt The memory request with the fill data. 2253860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 2263860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2273860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 2283860Sstever@eecs.umich.edu */ 2294626Sstever@eecs.umich.edu BlkType *handleFill(PacketPtr pkt, BlkType *blk, 2304626Sstever@eecs.umich.edu PacketList &writebacks); 2313860Sstever@eecs.umich.edu 2329548Sandreas.hansson@arm.com 2339548Sandreas.hansson@arm.com /** 2349548Sandreas.hansson@arm.com * Performs the access specified by the request. 2359548Sandreas.hansson@arm.com * @param pkt The request to perform. 2369548Sandreas.hansson@arm.com * @return The result of the access. 2379548Sandreas.hansson@arm.com */ 2389548Sandreas.hansson@arm.com bool recvTimingReq(PacketPtr pkt); 2399548Sandreas.hansson@arm.com 2409548Sandreas.hansson@arm.com /** 2419548Sandreas.hansson@arm.com * Handles a response (cache line fill/write ack) from the bus. 2429548Sandreas.hansson@arm.com * @param pkt The response packet 2439548Sandreas.hansson@arm.com */ 2449548Sandreas.hansson@arm.com void recvTimingResp(PacketPtr pkt); 2459548Sandreas.hansson@arm.com 2469548Sandreas.hansson@arm.com /** 2479548Sandreas.hansson@arm.com * Snoops bus transactions to maintain coherence. 2489548Sandreas.hansson@arm.com * @param pkt The current bus transaction. 2499548Sandreas.hansson@arm.com */ 2509548Sandreas.hansson@arm.com void recvTimingSnoopReq(PacketPtr pkt); 2519548Sandreas.hansson@arm.com 2529548Sandreas.hansson@arm.com /** 2539548Sandreas.hansson@arm.com * Handle a snoop response. 2549548Sandreas.hansson@arm.com * @param pkt Snoop response packet 2559548Sandreas.hansson@arm.com */ 2569548Sandreas.hansson@arm.com void recvTimingSnoopResp(PacketPtr pkt); 2579548Sandreas.hansson@arm.com 2589548Sandreas.hansson@arm.com /** 2599548Sandreas.hansson@arm.com * Performs the access specified by the request. 2609548Sandreas.hansson@arm.com * @param pkt The request to perform. 2619782Sandreas.hansson@arm.com * @return The number of ticks required for the access. 2629548Sandreas.hansson@arm.com */ 2639782Sandreas.hansson@arm.com Tick recvAtomic(PacketPtr pkt); 2649548Sandreas.hansson@arm.com 2659548Sandreas.hansson@arm.com /** 2669548Sandreas.hansson@arm.com * Snoop for the provided request in the cache and return the estimated 2679782Sandreas.hansson@arm.com * time taken. 2689548Sandreas.hansson@arm.com * @param pkt The memory request to snoop 2699782Sandreas.hansson@arm.com * @return The number of ticks required for the snoop. 2709548Sandreas.hansson@arm.com */ 2719782Sandreas.hansson@arm.com Tick recvAtomicSnoop(PacketPtr pkt); 2729548Sandreas.hansson@arm.com 2739548Sandreas.hansson@arm.com /** 2749548Sandreas.hansson@arm.com * Performs the access specified by the request. 2759548Sandreas.hansson@arm.com * @param pkt The request to perform. 2769548Sandreas.hansson@arm.com * @param fromCpuSide from the CPU side port or the memory side port 2779548Sandreas.hansson@arm.com */ 2789548Sandreas.hansson@arm.com void functionalAccess(PacketPtr pkt, bool fromCpuSide); 2799548Sandreas.hansson@arm.com 2807667Ssteve.reinhardt@amd.com void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk, 2817667Ssteve.reinhardt@amd.com bool deferred_response = false, 2827667Ssteve.reinhardt@amd.com bool pending_downgrade = false); 2834628Sstever@eecs.umich.edu bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); 2844626Sstever@eecs.umich.edu 2854670Sstever@eecs.umich.edu void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, 2865319Sstever@gmail.com bool already_copied, bool pending_inval); 2873860Sstever@eecs.umich.edu 2883860Sstever@eecs.umich.edu /** 2893860Sstever@eecs.umich.edu * Sets the blk to the new state. 2903860Sstever@eecs.umich.edu * @param blk The cache block being snooped. 2913860Sstever@eecs.umich.edu * @param new_state The new coherence state for the block. 2923860Sstever@eecs.umich.edu */ 2934670Sstever@eecs.umich.edu void handleSnoop(PacketPtr ptk, BlkType *blk, 2945319Sstever@gmail.com bool is_timing, bool is_deferred, bool pending_inval); 2953860Sstever@eecs.umich.edu 2963860Sstever@eecs.umich.edu /** 2973860Sstever@eecs.umich.edu * Create a writeback request for the given block. 2983860Sstever@eecs.umich.edu * @param blk The block to writeback. 2993860Sstever@eecs.umich.edu * @return The writeback request for the block. 3003860Sstever@eecs.umich.edu */ 3013860Sstever@eecs.umich.edu PacketPtr writebackBlk(BlkType *blk); 3023860Sstever@eecs.umich.edu 3039347SAndreas.Sandberg@arm.com 3049347SAndreas.Sandberg@arm.com void memWriteback(); 3059347SAndreas.Sandberg@arm.com void memInvalidate(); 3069347SAndreas.Sandberg@arm.com bool isDirty() const; 3079347SAndreas.Sandberg@arm.com 3089347SAndreas.Sandberg@arm.com /** 3099347SAndreas.Sandberg@arm.com * Cache block visitor that writes back dirty cache blocks using 3109347SAndreas.Sandberg@arm.com * functional writes. 3119347SAndreas.Sandberg@arm.com * 3129347SAndreas.Sandberg@arm.com * \return Always returns true. 3139347SAndreas.Sandberg@arm.com */ 3149347SAndreas.Sandberg@arm.com bool writebackVisitor(BlkType &blk); 3159347SAndreas.Sandberg@arm.com /** 3169347SAndreas.Sandberg@arm.com * Cache block visitor that invalidates all blocks in the cache. 3179347SAndreas.Sandberg@arm.com * 3189347SAndreas.Sandberg@arm.com * @warn Dirty cache lines will not be written back to memory. 3199347SAndreas.Sandberg@arm.com * 3209347SAndreas.Sandberg@arm.com * \return Always returns true. 3219347SAndreas.Sandberg@arm.com */ 3229347SAndreas.Sandberg@arm.com bool invalidateVisitor(BlkType &blk); 3239347SAndreas.Sandberg@arm.com 3249445SAndreas.Sandberg@ARM.com /** 3259445SAndreas.Sandberg@ARM.com * Flush a cache line due to an uncacheable memory access to the 3269445SAndreas.Sandberg@ARM.com * line. 3279445SAndreas.Sandberg@ARM.com * 3289445SAndreas.Sandberg@ARM.com * @note This shouldn't normally happen, but we need to handle it 3299445SAndreas.Sandberg@ARM.com * since some architecture models don't implement cache 3309445SAndreas.Sandberg@ARM.com * maintenance operations. We won't even try to get a decent 3319445SAndreas.Sandberg@ARM.com * timing here since the line should have been flushed earlier by 3329445SAndreas.Sandberg@ARM.com * a cache maintenance operation. 3339445SAndreas.Sandberg@ARM.com */ 3349445SAndreas.Sandberg@ARM.com void uncacheableFlush(PacketPtr pkt); 3359445SAndreas.Sandberg@ARM.com 3362810Srdreslin@umich.edu /** 3372982Sstever@eecs.umich.edu * Squash all requests associated with specified thread. 3382810Srdreslin@umich.edu * intended for use by I-cache. 3392982Sstever@eecs.umich.edu * @param threadNum The thread to squash. 3402810Srdreslin@umich.edu */ 3414626Sstever@eecs.umich.edu void squash(int threadNum); 3424626Sstever@eecs.umich.edu 3434626Sstever@eecs.umich.edu /** 3445365Sstever@gmail.com * Generate an appropriate downstream bus request packet for the 3455365Sstever@gmail.com * given parameters. 3465365Sstever@gmail.com * @param cpu_pkt The upstream request that needs to be satisfied. 3475365Sstever@gmail.com * @param blk The block currently in the cache corresponding to 3485365Sstever@gmail.com * cpu_pkt (NULL if none). 3495365Sstever@gmail.com * @param needsExclusive Indicates that an exclusive copy is required 3505365Sstever@gmail.com * even if the request in cpu_pkt doesn't indicate that. 3515365Sstever@gmail.com * @return A new Packet containing the request, or NULL if the 3525365Sstever@gmail.com * current request in cpu_pkt should just be forwarded on. 3534626Sstever@eecs.umich.edu */ 3544628Sstever@eecs.umich.edu PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 3559529Sandreas.hansson@arm.com bool needsExclusive) const; 3565365Sstever@gmail.com 3575365Sstever@gmail.com /** 3585365Sstever@gmail.com * Return the next MSHR to service, either a pending miss from the 3595365Sstever@gmail.com * mshrQueue, a buffered write from the write buffer, or something 3605365Sstever@gmail.com * from the prefetcher. This function is responsible for 3615365Sstever@gmail.com * prioritizing among those sources on the fly. 3625365Sstever@gmail.com */ 3634626Sstever@eecs.umich.edu MSHR *getNextMSHR(); 3645365Sstever@gmail.com 3655365Sstever@gmail.com /** 3665365Sstever@gmail.com * Selects an outstanding request to service. Called when the 3675365Sstever@gmail.com * cache gets granted the downstream bus in timing mode. 3685365Sstever@gmail.com * @return The request to service, NULL if none found. 3695365Sstever@gmail.com */ 3704628Sstever@eecs.umich.edu PacketPtr getTimingPacket(); 3714626Sstever@eecs.umich.edu 3724626Sstever@eecs.umich.edu /** 3734626Sstever@eecs.umich.edu * Marks a request as in service (sent on the bus). This can have side 3744626Sstever@eecs.umich.edu * effect since storage for no response commands is deallocated once they 3754626Sstever@eecs.umich.edu * are successfully sent. 3764626Sstever@eecs.umich.edu * @param pkt The request that was sent on the bus. 3774626Sstever@eecs.umich.edu */ 3787667Ssteve.reinhardt@amd.com void markInService(MSHR *mshr, PacketPtr pkt = 0); 3794626Sstever@eecs.umich.edu 3804626Sstever@eecs.umich.edu /** 3814626Sstever@eecs.umich.edu * Return whether there are any outstanding misses. 3824626Sstever@eecs.umich.edu */ 3834626Sstever@eecs.umich.edu bool outstandingMisses() const 3842810Srdreslin@umich.edu { 3854626Sstever@eecs.umich.edu return mshrQueue.allocated != 0; 3862810Srdreslin@umich.edu } 3872810Srdreslin@umich.edu 38810028SGiacomo.Gabrielli@arm.com CacheBlk *findBlock(Addr addr, bool is_secure) const { 38910028SGiacomo.Gabrielli@arm.com return tags->findBlock(addr, is_secure); 3902810Srdreslin@umich.edu } 3912810Srdreslin@umich.edu 39210028SGiacomo.Gabrielli@arm.com bool inCache(Addr addr, bool is_secure) const { 39310028SGiacomo.Gabrielli@arm.com return (tags->findBlock(addr, is_secure) != 0); 3943861Sstever@eecs.umich.edu } 3953861Sstever@eecs.umich.edu 39610028SGiacomo.Gabrielli@arm.com bool inMissQueue(Addr addr, bool is_secure) const { 39710028SGiacomo.Gabrielli@arm.com return (mshrQueue.findMatch(addr, is_secure) != 0); 3983861Sstever@eecs.umich.edu } 3995875Ssteve.reinhardt@amd.com 4005875Ssteve.reinhardt@amd.com /** 4015875Ssteve.reinhardt@amd.com * Find next request ready time from among possible sources. 4025875Ssteve.reinhardt@amd.com */ 4039529Sandreas.hansson@arm.com Tick nextMSHRReadyTime() const; 4049529Sandreas.hansson@arm.com 4059529Sandreas.hansson@arm.com public: 4069529Sandreas.hansson@arm.com /** Instantiates a basic cache object. */ 4079796Sprakash.ramrakhyani@arm.com Cache(const Params *p); 4089529Sandreas.hansson@arm.com 4099813Srioshering@gmail.com /** Non-default destructor is needed to deallocate memory. */ 4109813Srioshering@gmail.com virtual ~Cache(); 4119813Srioshering@gmail.com 4129529Sandreas.hansson@arm.com void regStats(); 4138985SAli.Saidi@ARM.com 4148985SAli.Saidi@ARM.com /** serialize the state of the caches 4158985SAli.Saidi@ARM.com * We currently don't support checkpointing cache state, so this panics. 4168985SAli.Saidi@ARM.com */ 4178985SAli.Saidi@ARM.com virtual void serialize(std::ostream &os); 4188985SAli.Saidi@ARM.com void unserialize(Checkpoint *cp, const std::string §ion); 4192810Srdreslin@umich.edu}; 4202810Srdreslin@umich.edu 4212810Srdreslin@umich.edu#endif // __CACHE_HH__ 422